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GET /api/patches/2219657/?format=api
{ "id": 2219657, "url": "http://patchwork.ozlabs.org/api/patches/2219657/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260403-winbond-v6-18-rc1-spi-nor-swp-v4-20-833dab5e7288@bootlin.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260403-winbond-v6-18-rc1-spi-nor-swp-v4-20-833dab5e7288@bootlin.com>", "list_archive_url": null, "date": "2026-04-03T16:09:38", "name": "[v4,20/27] mtd: spi-nor: swp: Add support for the complement feature", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "83ad0b8882ea3ea355fa04a3def0963bc8686abb", "submitter": { "id": 73368, "url": "http://patchwork.ozlabs.org/api/people/73368/?format=api", "name": "Miquel Raynal", "email": "miquel.raynal@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260403-winbond-v6-18-rc1-spi-nor-swp-v4-20-833dab5e7288@bootlin.com/mbox/", "series": [ { "id": 498652, "url": "http://patchwork.ozlabs.org/api/series/498652/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=498652", "date": "2026-04-03T16:09:18", "name": "mtd: spi-nor: Enhance software protection", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498652/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219657/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=RyBdczcJ;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=T2+m4DbZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:Message-Id\n\t:MIME-Version:Subject:Date:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=SDzell9ttQspSK05ec5PIJ5wbtOihDgHgdBm3Jv26Ac=; b=RyBdczcJQhcees\n\t0PPZ8oeCXRrKL0gaGAHT3pGhXh37uC/ACmP63tqxyuCcY4vp3uDmg4NPJGBvKJzwx3fG5TiCbFQJR\n\tdJ/VZdJ2kFurP3XwKZhwA1tBn/m9iNDRxaHPaZ/LOWJyxVgAE0caWLLwwOdPdCKTSZISh+TFxWCwZ\n\tuUCWFLuwmBlHsS1eZPMqTaP9D9Ng92exrkUr6y3oxIdK32Kkitx+xvljEB3xs51kMcODTjnWZUA9C\n\thOKQ/66tsOJ+Gj9VdoPrzheE7S27pNwEJ0VTG4auJP0UuMBM3E+tQN1f/SOyIlAhCJESRiLbACtVY\n\t8PWUs3hpw2Vr9hSTkf6w==;", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n\tt=1775232623; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=iXL5jH9mmaZPVtSclR9ZGgChE+rApa+9y59mJvYGhKE=;\n\tb=T2+m4DbZIst6dAQaDNBb9l/kol4P7Q+CpK8jTe9YY0zLd+xeLp53BEOKWc+wHYfTJuuxpv\n\tOt4u2QoR24QC4/ll3RQTxKSfaTQoEiSM2HO51/EJSzrfvC4IuPTc/xxAPsNaamGnOAZzDm\n\trDHJLOS8wS22LfqrEUZ2FdbM/t8zgPo64TluHMILrUQ5tVZyCEc0UOu7RP9E7wTHG09EIn\n\tHYLyl1NlacF2cW0wPI7eQ0wN7B+MAhfQBxBBGTLHyyaRkhDFcm+PlK6TXbI/MEzDFu5rCf\n\tqb5omfT27BQ4/F8mwidk5yXULELtntch7bLfiBEBB454s8digOv1ZInjHumUlA==" ], "From": "Miquel Raynal <miquel.raynal@bootlin.com>", "Date": "Fri, 03 Apr 2026 18:09:38 +0200", "Subject": "[PATCH v4 20/27] mtd: spi-nor: swp: Add support for the complement\n feature", "MIME-Version": "1.0", "Message-Id": "\n <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-20-833dab5e7288@bootlin.com>", "References": "\n <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-0-833dab5e7288@bootlin.com>", "In-Reply-To": "\n <20260403-winbond-v6-18-rc1-spi-nor-swp-v4-0-833dab5e7288@bootlin.com>", "To": "Pratyush Yadav <pratyush@kernel.org>, Michael Walle <mwalle@kernel.org>,\n Takahiro Kuwano <takahiro.kuwano@infineon.com>,\n Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,\n Jonathan Corbet <corbet@lwn.net>", "Cc": "Sean Anderson <sean.anderson@linux.dev>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Steam Lin <STLin2@winbond.com>, linux-mtd@lists.infradead.org,\n linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,\n Miquel Raynal <miquel.raynal@bootlin.com>", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260403_091657_544727_038CAD90 ", "X-CRM114-Status": "GOOD ( 28.80 )", "X-Spam-Score": "-2.1 (--)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: The current locking implementation allows to select a power\n of two number of blocks, which is going to be the protected amount,\n as well\n as telling whether this is the data at the top (end of the devic [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [185.246.85.4 listed in sa-accredit.habeas.com]\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [185.246.85.4 listed in\n sa-trusted.bondedsender.org]\n 0.0 RCVD_IN_VALIDITY_RPBL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [185.246.85.4 listed in bl.score.senderscore.com]\n -0.0 SPF_HELO_PASS SPF: HELO matches SPF record\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "The current locking implementation allows to select a power of two\nnumber of blocks, which is going to be the protected amount, as well as\ntelling whether this is the data at the top (end of the device) or the\nbottom (beginning of the device). This means at most we can cover half\nof the device or the entire device, but nothing in between.\n\nThe complement feature allows a much finer grain of configuration, by\nallowing to invert what is considered locked and unlocked.\n\nAdd support for this feature. The only known position for the CMP bit is\nbit 6 of the configuration register.\n\nThe locking and unlocking logics are kept unchanged if the CMP bit is\nunavailable. Otherwise, once the regular logic has been applied, we\ncheck if we already found an optimal configuration. If not, we try with\nthe CMP bit set. If the coverage is closer to the request, we use it.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\n drivers/mtd/spi-nor/core.c | 3 +\n drivers/mtd/spi-nor/core.h | 4 +\n drivers/mtd/spi-nor/debugfs.c | 1 +\n drivers/mtd/spi-nor/swp.c | 196 +++++++++++++++++++++++++++++++++++-------\n include/linux/mtd/spi-nor.h | 1 +\n 5 files changed, 173 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c\nindex eb7744926e44..c1e1d6d7cdf0 100644\n--- a/drivers/mtd/spi-nor/core.c\n+++ b/drivers/mtd/spi-nor/core.c\n@@ -2974,6 +2974,9 @@ static void spi_nor_init_flags(struct spi_nor *nor)\n \t\t\tnor->flags |= SNOR_F_HAS_SR_BP3_BIT6;\n \t}\n \n+\tif (flags & SPI_NOR_HAS_CMP)\n+\t\tnor->flags |= SNOR_F_HAS_SR2_CMP_BIT6;\n+\n \tif (flags & SPI_NOR_RWW && nor->params->n_banks > 1 &&\n \t !nor->controller_ops)\n \t\tnor->flags |= SNOR_F_RWW;\ndiff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h\nindex 8717a0ad90f0..842ab2a5a903 100644\n--- a/drivers/mtd/spi-nor/core.h\n+++ b/drivers/mtd/spi-nor/core.h\n@@ -141,6 +141,7 @@ enum spi_nor_option_flags {\n \tSNOR_F_ECC\t\t= BIT(15),\n \tSNOR_F_NO_WP\t\t= BIT(16),\n \tSNOR_F_SWAP16\t\t= BIT(17),\n+\tSNOR_F_HAS_SR2_CMP_BIT6\t= BIT(18),\n };\n \n struct spi_nor_read_command {\n@@ -483,6 +484,8 @@ struct spi_nor_id {\n * SPI_NOR_NO_ERASE: no erase command needed.\n * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program.\n * SPI_NOR_RWW: flash supports reads while write.\n+ * SPI_NOR_HAS_CMP: flash SR2 has complement (CMP) protect bit. Must\n+ * be used with SPI_NOR_HAS_LOCK.\n *\n * @no_sfdp_flags: flags that indicate support that can be discovered via SFDP.\n * Used when SFDP tables are not defined in the flash. These\n@@ -531,6 +534,7 @@ struct flash_info {\n #define SPI_NOR_NO_ERASE\t\tBIT(6)\n #define SPI_NOR_QUAD_PP\t\t\tBIT(8)\n #define SPI_NOR_RWW\t\t\tBIT(9)\n+#define SPI_NOR_HAS_CMP\t\t\tBIT(10)\n \n \tu8 no_sfdp_flags;\n #define SPI_NOR_SKIP_SFDP\t\tBIT(0)\ndiff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c\nindex 1ed1a0bbef3b..e1b3406d489b 100644\n--- a/drivers/mtd/spi-nor/debugfs.c\n+++ b/drivers/mtd/spi-nor/debugfs.c\n@@ -30,6 +30,7 @@ static const char *const snor_f_names[] = {\n \tSNOR_F_NAME(ECC),\n \tSNOR_F_NAME(NO_WP),\n \tSNOR_F_NAME(SWAP16),\n+\tSNOR_F_NAME(HAS_SR2_CMP_BIT6),\n };\n #undef SNOR_F_NAME\n \ndiff --git a/drivers/mtd/spi-nor/swp.c b/drivers/mtd/spi-nor/swp.c\nindex d75ed83eb787..f5a2d667379a 100644\n--- a/drivers/mtd/spi-nor/swp.c\n+++ b/drivers/mtd/spi-nor/swp.c\n@@ -32,6 +32,15 @@ static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)\n \t\treturn SR_TB_BIT5;\n }\n \n+static u8 spi_nor_get_sr_cmp_mask(struct spi_nor *nor)\n+{\n+\tif (!(nor->flags & SNOR_F_NO_READ_CR) &&\n+\t nor->flags & SNOR_F_HAS_SR2_CMP_BIT6)\n+\t\treturn SR2_CMP_BIT6;\n+\telse\n+\t\treturn 0;\n+}\n+\n u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)\n {\n \tunsigned int bp_slots, bp_slots_needed;\n@@ -59,8 +68,10 @@ void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr, loff_t *ofs,\n \tu64 min_prot_len;\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n \tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n+\tu8 cmp_mask = spi_nor_get_sr_tb_mask(nor);\n \tu8 bp, val = sr[0] & bp_mask;\n \tbool tb = (nor->flags & SNOR_F_HAS_SR_TB) ? sr[0] & tb_mask : 0;\n+\tbool cmp = sr[1] & cmp_mask;\n \n \tif (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6)\n \t\tval = (val & ~SR_BP3_BIT6) | SR_BP3;\n@@ -68,22 +79,37 @@ void spi_nor_get_locked_range_sr(struct spi_nor *nor, const u8 *sr, loff_t *ofs,\n \tbp = val >> SR_BP_SHIFT;\n \n \tif (!bp) {\n-\t\t/* No protection */\n-\t\t*ofs = 0;\n-\t\t*len = 0;\n-\t\treturn;\n+\t\tif (!cmp) {\n+\t\t\t/* No protection */\n+\t\t\t*ofs = 0;\n+\t\t\t*len = 0;\n+\t\t\treturn;\n+\t\t} else {\n+\t\t\t/* Full protection */\n+\t\t\t*ofs = 0;\n+\t\t\t*len = nor->params->size;\n+\t\t}\n \t}\n \n \tmin_prot_len = spi_nor_get_min_prot_length_sr(nor);\n \t*len = min_prot_len << (bp - 1);\n-\n \tif (*len > nor->params->size)\n \t\t*len = nor->params->size;\n \n-\tif (tb)\n-\t\t*ofs = 0;\n-\telse\n-\t\t*ofs = nor->params->size - *len;\n+\tif (cmp)\n+\t\t*len = nor->params->size - *len;\n+\n+\tif (!cmp) {\n+\t\tif (tb)\n+\t\t\t*ofs = 0;\n+\t\telse\n+\t\t\t*ofs = nor->params->size - *len;\n+\t} else {\n+\t\tif (tb)\n+\t\t\t*ofs = nor->params->size - *len;\n+\t\telse\n+\t\t\t*ofs = 0;\n+\t}\n }\n \n /*\n@@ -140,13 +166,15 @@ static int spi_nor_sr_set_bp_mask(struct spi_nor *nor, u8 *sr, u8 pow)\n }\n \n static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new_sr,\n-\t\t\t u8 pow, bool use_top)\n+\t\t\t u8 pow, bool use_top, bool cmp)\n {\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n \tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n+\tu8 cmp_mask = spi_nor_get_sr_cmp_mask(nor);\n \tint ret;\n \n \tnew_sr[0] = old_sr[0] & ~bp_mask & ~tb_mask;\n+\tnew_sr[1] = old_sr[1] & ~cmp_mask;\n \n \t/* Build BP field */\n \tret = spi_nor_sr_set_bp_mask(nor, &new_sr[0], pow);\n@@ -154,9 +182,13 @@ static int spi_nor_build_sr(struct spi_nor *nor, const u8 *old_sr, u8 *new_sr,\n \t\treturn ret;\n \n \t/* Build TB field */\n-\tif (!use_top)\n+\tif ((!cmp && !use_top) || (cmp && use_top))\n \t\tnew_sr[0] |= tb_mask;\n \n+\t/* Build CMP field */\n+\tif (cmp)\n+\t\tnew_sr[1] |= cmp_mask;\n+\n \treturn 0;\n }\n \n@@ -168,15 +200,22 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)\n {\n \tu8 bp_mask = spi_nor_get_sr_bp_mask(nor);\n \tu8 tb_mask = spi_nor_get_sr_tb_mask(nor);\n+\tu8 cmp_mask = spi_nor_get_sr_cmp_mask(nor);\n \n \tif (!sr) {\n \t\tif (spi_nor_read_sr(nor, nor->bouncebuf))\n \t\t\treturn;\n \n+\t\tif (!(nor->flags & SNOR_F_NO_READ_CR)) {\n+\t\t\tif (spi_nor_read_cr(nor, nor->bouncebuf + 1))\n+\t\t\t\treturn;\n+\t\t}\n+\n \t\tsr = nor->bouncebuf;\n \t}\n \n \tnor->dfs_sr_cache[0] = sr[0] & (bp_mask | tb_mask | SR_SRWD);\n+\tnor->dfs_sr_cache[1] = sr[1] & cmp_mask;\n }\n \n /*\n@@ -185,10 +224,11 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)\n * register\n * (SR). Does not support these features found in newer SR bitfields:\n * - SEC: sector/block protect - only handle SEC=0 (block protect)\n- * - CMP: complement protect - only support CMP=0 (range is not complemented)\n *\n * Support for the following is provided conditionally for some flash:\n * - TB: top/bottom protect\n+ * - CMP: complement protect (BP and TP describe the unlocked part, while\n+ * the reminder is locked)\n *\n * Sample table portion for 8MB flash (Winbond w25q64fw):\n *\n@@ -215,11 +255,13 @@ void spi_nor_cache_sr_lock_bits(struct spi_nor *nor, u8 *sr)\n static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n {\n \tu64 min_prot_len = spi_nor_get_min_prot_length_sr(nor);\n-\tu8 status_old[1] = {}, status_new[1] = {};\n-\tloff_t ofs_old, ofs_new;\n-\tu64 len_old, len_new;\n+\tu8 status_old[2] = {}, status_new[2] = {}, status_new_cmp[2] = {};\n+\tu8 *best_status_new = status_new;\n+\tloff_t ofs_old, ofs_new, ofs_new_cmp;\n+\tu64 len_old, len_new, len_new_cmp;\n \tloff_t lock_len;\n-\tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n+\tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB,\n+\t\tcan_be_cmp = spi_nor_get_sr_cmp_mask(nor);\n \tbool use_top;\n \tint ret;\n \tu8 pow;\n@@ -230,6 +272,14 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \n \tstatus_old[0] = nor->bouncebuf[0];\n \n+\tif (!(nor->flags & SNOR_F_NO_READ_CR)) {\n+\t\tret = spi_nor_read_cr(nor, nor->bouncebuf + 1);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tstatus_old[1] = nor->bouncebuf[1];\n+\t}\n+\n \t/* If nothing in our range is unlocked, we don't need to do anything */\n \tif (spi_nor_is_locked_sr(nor, ofs, len, status_old))\n \t\treturn 0;\n@@ -260,24 +310,56 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \telse\n \t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n \n-\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top);\n+\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top, false);\n \tif (ret)\n \t\treturn ret;\n \n+\t/*\n+\t * In case the region asked is not fully met, maybe we can try with the\n+\t * complement feature\n+\t */\n+\tspi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new);\n+\tif (can_be_cmp && len_new != lock_len) {\n+\t\tpow = ilog2(nor->params->size - lock_len) - ilog2(min_prot_len) + 1;\n+\t\tret = spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, true);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/*\n+\t\t * ilog2() \"floors\" the result, which means in some cases we may have to\n+\t\t * manually reduce the scope when the complement feature is used.\n+\t\t * The uAPI is to never lock more than what is requested, but less is accepted.\n+\t\t * Make sure we are not covering a too wide range, reduce it otherwise.\n+\t\t */\n+\t\tspi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_cmp);\n+\t\tif (len_new_cmp > lock_len) {\n+\t\t\tpow++;\n+\t\t\tret = spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, true);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* Pick the CMP configuration if we cover a closer range */\n+\t\tspi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new);\n+\t\tspi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_cmp);\n+\t\tif (len_new_cmp > len_new)\n+\t\t\tbest_status_new = status_new_cmp;\n+\t}\n+\n \t/*\n \t * Disallow further writes if WP# pin is neither left floating nor\n \t * wrongly tied to GND (that includes internal pull-downs).\n \t * WP# pin hard strapped to GND can be a valid use case.\n \t */\n \tif (!(nor->flags & SNOR_F_NO_WP))\n-\t\tstatus_new[0] |= SR_SRWD;\n+\t\tbest_status_new[0] |= SR_SRWD;\n \n \t/* Don't bother if they're the same */\n-\tif (status_new[0] == status_old[0])\n+\tif (best_status_new[0] == status_old[0] && best_status_new[1] == status_old[1])\n \t\treturn 0;\n \n \tspi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old);\n-\tspi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new);\n+\tspi_nor_get_locked_range_sr(nor, best_status_new, &ofs_new, &len_new);\n \n \t/* Don't \"lock\" with no region! */\n \tif (!len_new)\n@@ -288,11 +370,11 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, u64 len)\n \t (ofs_old < ofs_new || (ofs_new + len_new) < (ofs_old + len_old)))\n \t\treturn -EINVAL;\n \n-\tret = spi_nor_write_sr_and_check(nor, status_new[0]);\n+\tret = spi_nor_write_sr_cr_and_check(nor, best_status_new);\n \tif (ret)\n \t\treturn ret;\n \n-\tspi_nor_cache_sr_lock_bits(nor, status_new);\n+\tspi_nor_cache_sr_lock_bits(nor, best_status_new);\n \n \treturn 0;\n }\n@@ -306,11 +388,13 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n {\n \tu64 min_prot_len = spi_nor_get_min_prot_length_sr(nor);\n \tint ret;\n-\tu8 status_old[1], status_new[1];\n-\tloff_t ofs_old, ofs_new;\n-\tu64 len_old, len_new;\n+\tu8 status_old[2], status_new[2], status_new_cmp[2];\n+\tu8 *best_status_new = status_new;\n+\tloff_t ofs_old, ofs_new, ofs_new_cmp;\n+\tu64 len_old, len_new, len_new_cmp;\n \tloff_t lock_len;\n-\tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;\n+\tbool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB,\n+\t\tcan_be_cmp = spi_nor_get_sr_cmp_mask(nor);\n \tbool use_top;\n \tu8 pow;\n \n@@ -320,6 +404,14 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n \n \tstatus_old[0] = nor->bouncebuf[0];\n \n+\tif (!(nor->flags & SNOR_F_NO_READ_CR)) {\n+\t\tret = spi_nor_read_cr(nor, nor->bouncebuf + 1);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tstatus_old[1] = nor->bouncebuf[1];\n+\t}\n+\n \t/* If nothing in our range is locked, we don't need to do anything */\n \tif (spi_nor_is_unlocked_sr(nor, ofs, len, status_old))\n \t\treturn 0;\n@@ -357,30 +449,62 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, u64 len)\n \telse\n \t\tpow = ilog2(lock_len) - ilog2(min_prot_len) + 1;\n \n-\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top);\n+\tret = spi_nor_build_sr(nor, status_old, status_new, pow, use_top, false);\n \tif (ret)\n \t\treturn ret;\n \n+\t/*\n+\t * In case the region asked is not fully met, maybe we can try with the\n+\t * complement feature\n+\t */\n+\tspi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new);\n+\tif (can_be_cmp && len_new != lock_len) {\n+\t\tpow = ilog2(nor->params->size - lock_len) - ilog2(min_prot_len) + 1;\n+\t\tret = spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, true);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\t/*\n+\t\t * ilog2() \"floors\" the result, which means in some cases we may have to\n+\t\t * manually reduce the scope when the complement feature is used.\n+\t\t * The uAPI is to never unlock more than what is requested, but less is accepted.\n+\t\t * Make sure we are not covering a too small range, increase it otherwise.\n+\t\t */\n+\t\tspi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_cmp);\n+\t\tif (len_new_cmp < lock_len) {\n+\t\t\tpow--;\n+\t\t\tret = spi_nor_build_sr(nor, status_old, status_new_cmp, pow, use_top, true);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* Pick the CMP configuration if we cover a closer range */\n+\t\tspi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new);\n+\t\tspi_nor_get_locked_range_sr(nor, status_new_cmp, &ofs_new_cmp, &len_new_cmp);\n+\t\tif (len_new_cmp > len_new)\n+\t\t\tbest_status_new = status_new_cmp;\n+\t}\n+\n \t/* Don't protect status register if we're fully unlocked */\n \tif (lock_len == 0)\n-\t\tstatus_new[0] &= ~SR_SRWD;\n+\t\tbest_status_new[0] &= ~SR_SRWD;\n \n \t/* Don't bother if they're the same */\n-\tif (status_new[0] == status_old[0])\n+\tif (best_status_new[0] == status_old[0] && best_status_new[1] == status_old[1])\n \t\treturn 0;\n \n \t/* Only modify protection if it will not lock other areas */\n \tspi_nor_get_locked_range_sr(nor, status_old, &ofs_old, &len_old);\n-\tspi_nor_get_locked_range_sr(nor, status_new, &ofs_new, &len_new);\n+\tspi_nor_get_locked_range_sr(nor, best_status_new, &ofs_new, &len_new);\n \tif (len_old && len_new &&\n \t (ofs_new < ofs_old || (ofs_old + len_old) < (ofs_new + len_new)))\n \t\treturn -EINVAL;\n \n-\tret = spi_nor_write_sr_and_check(nor, status_new[0]);\n+\tret = spi_nor_write_sr_cr_and_check(nor, best_status_new);\n \tif (ret)\n \t\treturn ret;\n \n-\tspi_nor_cache_sr_lock_bits(nor, status_new);\n+\tspi_nor_cache_sr_lock_bits(nor, best_status_new);\n \n \treturn 0;\n }\n@@ -400,6 +524,14 @@ static int spi_nor_sr_is_locked(struct spi_nor *nor, loff_t ofs, u64 len)\n \tif (ret)\n \t\treturn ret;\n \n+\tif (!(nor->flags & SNOR_F_NO_READ_CR)) {\n+\t\tret = spi_nor_read_cr(nor, nor->bouncebuf + 1);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t} else {\n+\t\tnor->bouncebuf[1] = 0;\n+\t}\n+\n \treturn spi_nor_is_locked_sr(nor, ofs, len, nor->bouncebuf);\n }\n \ndiff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h\nindex 9ad77f9e76c2..4b92494827b1 100644\n--- a/include/linux/mtd/spi-nor.h\n+++ b/include/linux/mtd/spi-nor.h\n@@ -125,6 +125,7 @@\n #define SR2_LB1\t\t\tBIT(3)\t/* Security Register Lock Bit 1 */\n #define SR2_LB2\t\t\tBIT(4)\t/* Security Register Lock Bit 2 */\n #define SR2_LB3\t\t\tBIT(5)\t/* Security Register Lock Bit 3 */\n+#define SR2_CMP_BIT6\t\tBIT(6)\n #define SR2_QUAD_EN_BIT7\tBIT(7)\n \n /* Supported SPI protocols */\n", "prefixes": [ "v4", "20/27" ] }