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GET /api/patches/2219610/?format=api
{ "id": 2219610, "url": "http://patchwork.ozlabs.org/api/patches/2219610/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/2b8af6022aba06aa98a249ae67922de29d82d86f.1775228029.git.balaton@eik.bme.hu/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<2b8af6022aba06aa98a249ae67922de29d82d86f.1775228029.git.balaton@eik.bme.hu>", "list_archive_url": null, "date": "2026-04-03T14:59:27", "name": "[1/2] ati-vga: Fix setting CRTC_OFFSET", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e4d92ee879822805fcacd54ece50c73a4c7a5137", "submitter": { "id": 16148, "url": "http://patchwork.ozlabs.org/api/people/16148/?format=api", "name": "BALATON Zoltan", "email": "balaton@eik.bme.hu" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/2b8af6022aba06aa98a249ae67922de29d82d86f.1775228029.git.balaton@eik.bme.hu/mbox/", "series": [ { "id": 498641, "url": "http://patchwork.ozlabs.org/api/series/498641/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498641", "date": "2026-04-03T14:59:27", "name": "More ati-vga fixes for 11.0", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498641/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219610/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219610/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnMN36yVYz1yCt\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 04 Apr 2026 02:00:19 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8fzy-0003b6-Dj; Fri, 03 Apr 2026 10:59:50 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <balaton@eik.bme.hu>)\n id 1w8fzk-0003Yq-BA\n for qemu-devel@nongnu.org; Fri, 03 Apr 2026 10:59:36 -0400", "from zero.eik.bme.hu ([152.66.115.2])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <balaton@eik.bme.hu>)\n id 1w8fzi-0006kc-Bt\n for qemu-devel@nongnu.org; Fri, 03 Apr 2026 10:59:36 -0400", "from localhost (localhost [127.0.0.1])\n by zero.eik.bme.hu (Postfix) with ESMTP id 4F238596A24;\n Fri, 03 Apr 2026 16:59:29 +0200 (CEST)", "from zero.eik.bme.hu ([127.0.0.1])\n by localhost (zero.eik.bme.hu [127.0.0.1]) (amavis, port 10028) with ESMTP\n id c2VB2pSCuHUt; Fri, 3 Apr 2026 16:59:27 +0200 (CEST)", "by zero.eik.bme.hu (Postfix, from userid 432)\n id 3F955596A2A; Fri, 03 Apr 2026 16:59:27 +0200 (CEST)" ], "X-Virus-Scanned": "amavis at eik.bme.hu", "Message-ID": "\n <2b8af6022aba06aa98a249ae67922de29d82d86f.1775228029.git.balaton@eik.bme.hu>", "In-Reply-To": "<cover.1775228029.git.balaton@eik.bme.hu>", "References": "<cover.1775228029.git.balaton@eik.bme.hu>", "From": "BALATON Zoltan <balaton@eik.bme.hu>", "Subject": "[PATCH 1/2] ati-vga: Fix setting CRTC_OFFSET", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "To": "qemu-devel@nongnu.org", "Cc": "Gerd Hoffmann <kraxel@redhat.com>, marcandre.lureau@redhat.com,\n Chad Jablonski <chad@jablonski.xyz>,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>", "Date": "Fri, 03 Apr 2026 16:59:27 +0200 (CEST)", "Received-SPF": "pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu;\n helo=zero.eik.bme.hu", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Offset (display start address) should also be updated when changing\nthe register value not only on mode change. Fix the register write\nmask to hard code bits 0:2 to 0 as the chip docs say and update the\nstart address on register write. This fixes virtual screen panning for\nscreens larger than displayed resolution.\n\nAs this register allows values that cannot be handled by the VBE_DISPI\nX and Y offsets (which is restricted by line length) we add a function\nto set it directly not through the VBE offsets.\n\nSigned-off-by: BALATON Zoltan <balaton@eik.bme.hu>\n---\n hw/display/ati.c | 34 +++++++++++++++++-----------------\n 1 file changed, 17 insertions(+), 17 deletions(-)", "diff": "diff --git a/hw/display/ati.c b/hw/display/ati.c\nindex eb00382902..3976f5f01c 100644\n--- a/hw/display/ati.c\n+++ b/hw/display/ati.c\n@@ -48,6 +48,19 @@ static const struct {\n \n enum { VGA_MODE, EXT_MODE };\n \n+static void ati_vga_set_offset(VGACommonState *vga, uint32_t offs)\n+{\n+ int bypp = DIV_ROUND_UP(vga->vbe_regs[VBE_DISPI_INDEX_BPP], BITS_PER_BYTE);\n+\n+ if (!bypp ||\n+ vga->vbe_regs[VBE_DISPI_INDEX_YRES] *\n+ vga->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] * bypp + offs >\n+ vga->vbe_size) {\n+ return;\n+ }\n+ vga->vbe_start_addr = offs / 4;\n+}\n+\n static void ati_vga_switch_mode(ATIVGAState *s)\n {\n DPRINTF(\"%d -> %d\\n\",\n@@ -110,26 +123,12 @@ static void ati_vga_switch_mode(ATIVGAState *s)\n vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_ENABLED |\n VBE_DISPI_LFB_ENABLED | VBE_DISPI_NOCLEARMEM |\n (s->regs.dac_cntl & DAC_8BIT_EN ? VBE_DISPI_8BIT_DAC : 0));\n- /* now set offset and stride after enable as that resets these */\n+ /* now set offset and stride because enable resets these */\n if (stride) {\n- int bypp = DIV_ROUND_UP(bpp, BITS_PER_BYTE);\n-\n vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_VIRT_WIDTH);\n vbe_ioport_write_data(&s->vga, 0, stride);\n- stride *= bypp;\n- if (offs % stride) {\n- DPRINTF(\"CRTC offset is not multiple of pitch\\n\");\n- vbe_ioport_write_index(&s->vga, 0,\n- VBE_DISPI_INDEX_X_OFFSET);\n- vbe_ioport_write_data(&s->vga, 0, offs % stride / bypp);\n- }\n- vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_Y_OFFSET);\n- vbe_ioport_write_data(&s->vga, 0, offs / stride);\n- DPRINTF(\"VBE offset (%d,%d), vbe_start_addr=%x\\n\",\n- s->vga.vbe_regs[VBE_DISPI_INDEX_X_OFFSET],\n- s->vga.vbe_regs[VBE_DISPI_INDEX_Y_OFFSET],\n- s->vga.vbe_start_addr);\n }\n+ ati_vga_set_offset(&s->vga, offs);\n }\n } else {\n /* VGA mode enabled */\n@@ -752,7 +751,8 @@ static void ati_mm_write(void *opaque, hwaddr addr,\n s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff;\n break;\n case CRTC_OFFSET:\n- s->regs.crtc_offset = data & 0xc7ffffff;\n+ s->regs.crtc_offset = data & 0x87fffff8;\n+ ati_vga_set_offset(&s->vga, s->regs.crtc_offset & 0x07ffffff);\n break;\n case CRTC_OFFSET_CNTL:\n s->regs.crtc_offset_cntl = data; /* FIXME */\n", "prefixes": [ "1/2" ] }