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GET /api/patches/2219589/?format=api
{ "id": 2219589, "url": "http://patchwork.ozlabs.org/api/patches/2219589/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403142446.36964-9-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260403142446.36964-9-mohamed@unpredictable.fr>", "list_archive_url": null, "date": "2026-04-03T14:24:45", "name": "[v5,8/9] whpx: i386: kernel-irqchip=off fixes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5b85dc040b742fac352c74020b8a93a3274f8541", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403142446.36964-9-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 498635, "url": "http://patchwork.ozlabs.org/api/series/498635/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498635", "date": "2026-04-03T14:24:37", "name": "whpx: i386: bug fixes, feature probing and CPUID", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498635/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219589/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219589/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=EjMJW3dE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Fri, 03 Apr 2026 10:25:21 -0400", "from outbound.st.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-6 (Postfix) with ESMTPS id\n C6EA61800107; Fri, 03 Apr 2026 14:25:14 +0000 (UTC)", "from localhost.localdomain (unknown [17.42.251.67])\n by p00-icloudmta-asmtp-us-east-1a-100-percent-6 (Postfix) with ESMTPSA id\n 9E4D71800108; Fri, 03 Apr 2026 14:25:00 +0000 (UTC)" ], "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1775226318; x=1777818318;\n bh=oH6KYZnB9Pjiqg2T3vBHoqVmmC1KdQmN+M0nU3YJCD8=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=EjMJW3dEqxpmBXLuzY1TB3zIQepF+qgt1VOT8tyrBuzHbOvoQorIsiLq8z2WkvnWf2g46aMfkyb5NScmSUpP/51Mw78y8yhsXqnRt3ausZb33/jiihzBxKvuKk8NnwaKpbS1NUyGxZ5BohqelHNkijT/OeVk46hQcDVJepCD/nXTvtS7P3PWSjxBZnN3g8NFo50LrlaQWr+sgauntlcb6V+KVZLK3Y31avyZUjHADyAUtcXkrpiwyC4QG2QFasT7drVUcG+4iuF6an+HZMwW6/VqJwcfxya/fzgwWqopbW5HZW5u/Jk215qBzSfe4+en+vvAt4XW2yo5b1qb6XlSNA==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "Phil Dennis-Jordan <phil@philjordan.eu>,\n Mohamed Mediouni <mohamed@unpredictable.fr>,\n Paolo Bonzini <pbonzini@redhat.com>, Zhao Liu <zhao1.liu@intel.com>,\n Pedro Barbuda <pbarbuda@microsoft.com>, Wei Liu <wei.liu@kernel.org>,\n Roman Bolshakov <rbolshakov@ddn.com>", "Subject": "[PATCH v5 8/9] whpx: i386: kernel-irqchip=off fixes", "Date": "Fri, 3 Apr 2026 16:24:45 +0200", "Message-ID": "<20260403142446.36964-9-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260403142446.36964-1-mohamed@unpredictable.fr>", "References": "<20260403142446.36964-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAzMDEyOCBTYWx0ZWRfXyO0ucY9GbeKB\n Z7ZoMxRQRkMp4QhYdznH9/IfFELv7TDyeglTXg9II2UCG+z/RBW8aMKGrNqYcWjzG3X0oWNS0/O\n Hke4UHmtBUS9QUD/WDf1/Xz+RNdChCjEUwv0ifIpex3qtndPlED8ENnjdzK2eC+YcNYleWhOULF\n 99QZX8uEGNNT8LN50hq8PTaftC8VNa2dHweO7JA+2Jkq7h+62fMl9nYsn/169zrqmq2UvJWPToD\n u0RqaJFqU7GsMQp6n2vdWz05bA0bca1g1bVBQnS2uEygs6Q5k42tJIlyKjcusxPNPJmURum4GtC\n 3Cl5uXfBChL0xOmjvcDtxu4daH0MH4NMQn41njoJad3GWKqGoEjd0dGiZDAPAU=", "X-Authority-Info-Out": "v=2.4 cv=AqnjHe9P c=1 sm=1 tr=0 ts=69cfcdcb\n cx=c_apl:c_pps:t_out a=YrL12D//S6tul8v/L+6tKg==:117\n a=YrL12D//S6tul8v/L+6tKg==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RxDqNW836w1vIOo4GgAA:9", "X-Proofpoint-ORIG-GUID": "r87hl6hJv0TAkJSDlM_6sluI8isR8pbC", "X-Proofpoint-GUID": "r87hl6hJv0TAkJSDlM_6sluI8isR8pbC", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-03_04,2026-04-03_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=notspam policy=default score=0 suspectscore=0\n clxscore=1030 mlxscore=0 bulkscore=0\n mlxlogscore=999 lowpriorityscore=0\n phishscore=0 malwarescore=0 spamscore=0 adultscore=0 classifier=spam\n authscore=0 adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000\n definitions=main-2604030128", "Received-SPF": "pass client-ip=57.103.78.123;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This was really... quite broken. After fixing this,\nWindows boots with kernel-irqchip=off.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n target/i386/whpx/whpx-all.c | 51 +++++++++----------------------------\n 1 file changed, 12 insertions(+), 39 deletions(-)", "diff": "diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 3e006496be..db2e85514c 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -371,28 +371,6 @@ static int whpx_set_tsc(CPUState *cpu)\n return 0;\n }\n \n-/*\n- * The CR8 register in the CPU is mapped to the TPR register of the APIC,\n- * however, they use a slightly different encoding. Specifically:\n- *\n- * APIC.TPR[bits 7:4] = CR8[bits 3:0]\n- *\n- * This mechanism is described in section 10.8.6.1 of Volume 3 of Intel 64\n- * and IA-32 Architectures Software Developer's Manual.\n- *\n- * The functions below translate the value of CR8 to TPR and vice versa.\n- */\n-\n-static uint64_t whpx_apic_tpr_to_cr8(uint64_t tpr)\n-{\n- return tpr >> 4;\n-}\n-\n-static uint64_t whpx_cr8_to_apic_tpr(uint64_t cr8)\n-{\n- return cr8 << 4;\n-}\n-\n void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n {\n struct whpx_state *whpx = &whpx_global;\n@@ -421,7 +399,7 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n v86 = (env->eflags & VM_MASK);\n r86 = !(env->cr[0] & CR0_PE_MASK);\n \n- vcpu->tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ vcpu->tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n vcpu->apic_base = cpu_get_apic_base(x86_cpu->apic_state);\n \n idx = 0;\n@@ -692,17 +670,6 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n hr);\n }\n \n- if (whpx_irqchip_in_kernel()) {\n- /*\n- * Fetch the TPR value from the emulated APIC. It may get overwritten\n- * below with the value from CR8 returned by\n- * WHvGetVirtualProcessorRegisters().\n- */\n- whpx_apic_get(x86_cpu->apic_state);\n- vcpu->tpr = whpx_apic_tpr_to_cr8(\n- cpu_get_apic_tpr(x86_cpu->apic_state));\n- }\n-\n idx = 0;\n \n /* Indexes for first 16 registers match between HV and QEMU definitions */\n@@ -751,7 +718,7 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n tpr = vcxt.values[idx++].Reg64;\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1605,6 +1572,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n UINT32 reg_count = 0;\n WHV_REGISTER_VALUE reg_values[3];\n WHV_REGISTER_NAME reg_names[3];\n+ int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);\n \n memset(&new_int, 0, sizeof(new_int));\n memset(reg_values, 0, sizeof(reg_values));\n@@ -1643,7 +1611,8 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n /* Get pending hard interruption or replay one that was overwritten */\n if (!whpx_irqchip_in_kernel()) {\n if (!vcpu->interruption_pending &&\n- vcpu->interruptable && (env->eflags & IF_MASK)) {\n+ vcpu->interruptable && (env->eflags & IF_MASK)\n+ && (irr == -1 || vcpu->tpr < irr)) {\n assert(!new_int.InterruptionPending);\n if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);\n@@ -1690,7 +1659,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n }\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n- tpr = whpx_apic_tpr_to_cr8(cpu_get_apic_tpr(x86_cpu->apic_state));\n+ tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n if (tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n@@ -1702,9 +1671,13 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n /* Update the state of the interrupt delivery notification */\n if (!vcpu->window_registered &&\n cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n+ if (irr == -1) {\n+ irr = 0;\n+ }\n reg_values[reg_count].DeliverabilityNotifications =\n (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {\n- .InterruptNotification = 1\n+ .InterruptNotification = 1,\n+ .InterruptPriority = irr\n };\n vcpu->window_registered = 1;\n reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;\n@@ -1737,7 +1710,7 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n if (vcpu->tpr != tpr) {\n vcpu->tpr = tpr;\n bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, whpx_cr8_to_apic_tpr(vcpu->tpr));\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n bql_unlock();\n }\n \n", "prefixes": [ "v5", "8/9" ] }