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{
    "id": 2219573,
    "url": "http://patchwork.ozlabs.org/api/patches/2219573/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
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        "list_archive_url": "",
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    "msgid": "<20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com>",
    "list_archive_url": null,
    "date": "2026-04-03T13:27:56",
    "name": "[2/3] pinctrl: qcom: add the TLMM driver for the Nord platforms",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "81477c4da05aad55565a2438c84bb57463083c15",
    "submitter": {
        "id": 92196,
        "url": "http://patchwork.ozlabs.org/api/people/92196/?format=api",
        "name": "Bartosz Golaszewski",
        "email": "bartosz.golaszewski@oss.qualcomm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com/mbox/",
    "series": [
        {
            "id": 498631,
            "url": "http://patchwork.ozlabs.org/api/series/498631/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498631",
            "date": "2026-04-03T13:27:54",
            "name": "pinctrl: qcom: add support for the TLMM controller on Nord platforms",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/498631/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2219573/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2219573/checks/",
    "tags": {},
    "related": [],
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        ],
        "From": "Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>",
        "Date": "Fri, 03 Apr 2026 15:27:56 +0200",
        "Subject": "[PATCH 2/3] pinctrl: qcom: add the TLMM driver for the Nord\n platforms",
        "Precedence": "bulk",
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        "Message-Id": "<20260403-nord-tlmm-v1-2-4864f400c700@oss.qualcomm.com>",
        "References": "<20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com>",
        "In-Reply-To": "<20260403-nord-tlmm-v1-0-4864f400c700@oss.qualcomm.com>",
        "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n        Rob Herring <robh@kernel.org>,\n        Krzysztof Kozlowski <krzk+dt@kernel.org>,\n        Conor Dooley <conor+dt@kernel.org>,\n        Richard Cochran <richardcochran@gmail.com>,\n        Bartosz Golaszewski <brgl@kernel.org>,\n        Shawn Guo <shengchao.guo@oss.qualcomm.com>,\n        Arnd Bergmann <arnd@arndb.de>",
        "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n        Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>",
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    },
    "content": "Add support for the TLMM controller on the Qualcomm Nord platform.\n\nCo-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\nSigned-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>\nSigned-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/Kconfig.msm    |    7 +\n drivers/pinctrl/qcom/Makefile       |    1 +\n drivers/pinctrl/qcom/pinctrl-nord.c | 3297 +++++++++++++++++++++++++++++++++++\n 3 files changed, 3305 insertions(+)",
    "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm\nindex 6df6159fa5f89f9f0470e700b4698dc8849ed515..6698e2a50b2f67b1aadb4a840339e769c92f95f8 100644\n--- a/drivers/pinctrl/qcom/Kconfig.msm\n+++ b/drivers/pinctrl/qcom/Kconfig.msm\n@@ -261,6 +261,13 @@ config PINCTRL_SA8775P\n \t  This is the pinctrl, pinmux and pinconf driver for the Qualcomm\n \t  TLMM block found on the Qualcomm SA8775P platforms.\n \n+config PINCTRL_NORD\n+\ttristate \"Qualcomm Technologies Inc NORD (SA8797p) pin controller driver\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\thelp\n+\t  This is the pinctrl, pinmux and pinconf driver for the Qualcomm\n+\t  TLMM block found on the Qualcomm NORD platforms.\n+\n config PINCTRL_SAR2130P\n \ttristate \"Qualcomm Technologies Inc SAR2130P pin controller driver\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex a8fd12f90d6e6f8e139097cc0a81d6f178f09000..ba6e9408373ff4327bb0c092f1f30889998503a1 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -35,6 +35,7 @@ obj-$(CONFIG_PINCTRL_MDM9607)\t+= pinctrl-mdm9607.o\n obj-$(CONFIG_PINCTRL_MDM9615)\t+= pinctrl-mdm9615.o\n obj-$(CONFIG_PINCTRL_MILOS) += pinctrl-milos.o\n obj-$(CONFIG_PINCTRL_MILOS_LPASS_LPI) += pinctrl-milos-lpass-lpi.o\n+obj-$(CONFIG_PINCTRL_NORD)\t+= pinctrl-nord.o\n obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o\n obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o\n obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-nord.c b/drivers/pinctrl/qcom/pinctrl-nord.c\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..82e519abaf75771817a0f811c6af80c4f98e93ed\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-nord.c\n@@ -0,0 +1,3297 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2026 Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+\n+#include \"pinctrl-msm.h\"\n+\n+#define REG_SIZE 0x1000\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)    \\\n+\t{                                                             \\\n+\t\t.grp = PINCTRL_PINGROUP(\"gpio\" #id,                   \\\n+\t\t\t\t\tgpio##id##_pins,              \\\n+\t\t\t\t\tARRAY_SIZE(gpio##id##_pins)), \\\n+\t\t.ctl_reg = REG_SIZE * id,                             \\\n+\t\t.io_reg = 0x4 + REG_SIZE * id,                        \\\n+\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id,                  \\\n+\t\t.intr_status_reg = 0xc + REG_SIZE * id,               \\\n+\t\t.intr_target_reg = 0x8 + REG_SIZE * id,               \\\n+\t\t.mux_bit = 2,                                         \\\n+\t\t.pull_bit = 0,                                        \\\n+\t\t.drv_bit = 6,                                         \\\n+\t\t.egpio_enable = 12,                                   \\\n+\t\t.egpio_present = 11,                                  \\\n+\t\t.oe_bit = 9,                                          \\\n+\t\t.in_bit = 0,                                          \\\n+\t\t.out_bit = 1,                                         \\\n+\t\t.intr_enable_bit = 0,                                 \\\n+\t\t.intr_status_bit = 0,                                 \\\n+\t\t.intr_target_bit = 5,                                 \\\n+\t\t.intr_target_kpss_val = 3,                            \\\n+\t\t.intr_raw_status_bit = 4,                             \\\n+\t\t.intr_polarity_bit = 1,                               \\\n+\t\t.intr_detection_bit = 2,                              \\\n+\t\t.intr_detection_width = 2,                            \\\n+\t\t.funcs = (int[]){                                     \\\n+\t\t\tmsm_mux_gpio, /* gpio mode */                 \\\n+\t\t\tmsm_mux_##f1,                                 \\\n+\t\t\tmsm_mux_##f2,                                 \\\n+\t\t\tmsm_mux_##f3,                                 \\\n+\t\t\tmsm_mux_##f4,                                 \\\n+\t\t\tmsm_mux_##f5,                                 \\\n+\t\t\tmsm_mux_##f6,                                 \\\n+\t\t\tmsm_mux_##f7,                                 \\\n+\t\t\tmsm_mux_##f8,                                 \\\n+\t\t\tmsm_mux_##f9,                                 \\\n+\t\t\tmsm_mux_##f10,                                \\\n+\t\t\tmsm_mux_##f11 /* egpio mode */                \\\n+\t\t},                                                    \\\n+\t\t.nfuncs = 12,                                         \\\n+\t}\n+\n+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)                   \\\n+\t{                                                            \\\n+\t\t.grp = PINCTRL_PINGROUP(#pg_name,                    \\\n+\t\t\t\t\tpg_name##_pins,              \\\n+\t\t\t\t\tARRAY_SIZE(pg_name##_pins)), \\\n+\t\t.ctl_reg = ctl,                                      \\\n+\t\t.io_reg = 0,                                         \\\n+\t\t.intr_cfg_reg = 0,                                   \\\n+\t\t.intr_status_reg = 0,                                \\\n+\t\t.intr_target_reg = 0,                                \\\n+\t\t.mux_bit = -1,                                       \\\n+\t\t.pull_bit = pull,                                    \\\n+\t\t.drv_bit = drv,                                      \\\n+\t\t.oe_bit = -1,                                        \\\n+\t\t.in_bit = -1,                                        \\\n+\t\t.out_bit = -1,                                       \\\n+\t\t.intr_enable_bit = -1,                               \\\n+\t\t.intr_status_bit = -1,                               \\\n+\t\t.intr_target_bit = -1,                               \\\n+\t\t.intr_raw_status_bit = -1,                           \\\n+\t\t.intr_polarity_bit = -1,                             \\\n+\t\t.intr_detection_bit = -1,                            \\\n+\t\t.intr_detection_width = -1,                          \\\n+\t}\n+\n+#define UFS_RESET(pg_name, offset)                                   \\\n+\t{                                                            \\\n+\t\t.grp = PINCTRL_PINGROUP(#pg_name,                    \\\n+\t\t\t\t\tpg_name##_pins,              \\\n+\t\t\t\t\tARRAY_SIZE(pg_name##_pins)), \\\n+\t\t.ctl_reg = offset,                                   \\\n+\t\t.io_reg = offset + 0x4,                              \\\n+\t\t.intr_cfg_reg = 0,                                   \\\n+\t\t.intr_status_reg = 0,                                \\\n+\t\t.intr_target_reg = 0,                                \\\n+\t\t.mux_bit = -1,                                       \\\n+\t\t.pull_bit = 3,                                       \\\n+\t\t.drv_bit = 0,                                        \\\n+\t\t.oe_bit = -1,                                        \\\n+\t\t.in_bit = -1,                                        \\\n+\t\t.out_bit = 0,                                        \\\n+\t\t.intr_enable_bit = -1,                               \\\n+\t\t.intr_status_bit = -1,                               \\\n+\t\t.intr_target_bit = -1,                               \\\n+\t\t.intr_raw_status_bit = -1,                           \\\n+\t\t.intr_polarity_bit = -1,                             \\\n+\t\t.intr_detection_bit = -1,                            \\\n+\t\t.intr_detection_width = -1,                          \\\n+\t}\n+\n+#define QUP_I3C(qup_mode, qup_offset) \\\n+\t{                             \\\n+\t\t.mode = qup_mode,     \\\n+\t\t.offset = qup_offset, \\\n+\t}\n+\n+static const struct pinctrl_pin_desc nord_pins[] = {\n+\tPINCTRL_PIN(0, \"GPIO_0\"),\n+\tPINCTRL_PIN(1, \"GPIO_1\"),\n+\tPINCTRL_PIN(2, \"GPIO_2\"),\n+\tPINCTRL_PIN(3, \"GPIO_3\"),\n+\tPINCTRL_PIN(4, \"GPIO_4\"),\n+\tPINCTRL_PIN(5, \"GPIO_5\"),\n+\tPINCTRL_PIN(6, \"GPIO_6\"),\n+\tPINCTRL_PIN(7, \"GPIO_7\"),\n+\tPINCTRL_PIN(8, \"GPIO_8\"),\n+\tPINCTRL_PIN(9, \"GPIO_9\"),\n+\tPINCTRL_PIN(10, \"GPIO_10\"),\n+\tPINCTRL_PIN(11, \"GPIO_11\"),\n+\tPINCTRL_PIN(12, \"GPIO_12\"),\n+\tPINCTRL_PIN(13, \"GPIO_13\"),\n+\tPINCTRL_PIN(14, \"GPIO_14\"),\n+\tPINCTRL_PIN(15, \"GPIO_15\"),\n+\tPINCTRL_PIN(16, \"GPIO_16\"),\n+\tPINCTRL_PIN(17, \"GPIO_17\"),\n+\tPINCTRL_PIN(18, \"GPIO_18\"),\n+\tPINCTRL_PIN(19, \"GPIO_19\"),\n+\tPINCTRL_PIN(20, \"GPIO_20\"),\n+\tPINCTRL_PIN(21, \"GPIO_21\"),\n+\tPINCTRL_PIN(22, \"GPIO_22\"),\n+\tPINCTRL_PIN(23, \"GPIO_23\"),\n+\tPINCTRL_PIN(24, \"GPIO_24\"),\n+\tPINCTRL_PIN(25, \"GPIO_25\"),\n+\tPINCTRL_PIN(26, \"GPIO_26\"),\n+\tPINCTRL_PIN(27, \"GPIO_27\"),\n+\tPINCTRL_PIN(28, \"GPIO_28\"),\n+\tPINCTRL_PIN(29, \"GPIO_29\"),\n+\tPINCTRL_PIN(30, \"GPIO_30\"),\n+\tPINCTRL_PIN(31, \"GPIO_31\"),\n+\tPINCTRL_PIN(32, \"GPIO_32\"),\n+\tPINCTRL_PIN(33, \"GPIO_33\"),\n+\tPINCTRL_PIN(34, \"GPIO_34\"),\n+\tPINCTRL_PIN(35, \"GPIO_35\"),\n+\tPINCTRL_PIN(36, \"GPIO_36\"),\n+\tPINCTRL_PIN(37, \"GPIO_37\"),\n+\tPINCTRL_PIN(38, \"GPIO_38\"),\n+\tPINCTRL_PIN(39, \"GPIO_39\"),\n+\tPINCTRL_PIN(40, \"GPIO_40\"),\n+\tPINCTRL_PIN(41, \"GPIO_41\"),\n+\tPINCTRL_PIN(42, \"GPIO_42\"),\n+\tPINCTRL_PIN(43, \"GPIO_43\"),\n+\tPINCTRL_PIN(44, \"GPIO_44\"),\n+\tPINCTRL_PIN(45, \"GPIO_45\"),\n+\tPINCTRL_PIN(46, \"GPIO_46\"),\n+\tPINCTRL_PIN(47, \"GPIO_47\"),\n+\tPINCTRL_PIN(48, \"GPIO_48\"),\n+\tPINCTRL_PIN(49, \"GPIO_49\"),\n+\tPINCTRL_PIN(50, \"GPIO_50\"),\n+\tPINCTRL_PIN(51, \"GPIO_51\"),\n+\tPINCTRL_PIN(52, \"GPIO_52\"),\n+\tPINCTRL_PIN(53, \"GPIO_53\"),\n+\tPINCTRL_PIN(54, \"GPIO_54\"),\n+\tPINCTRL_PIN(55, \"GPIO_55\"),\n+\tPINCTRL_PIN(56, \"GPIO_56\"),\n+\tPINCTRL_PIN(57, \"GPIO_57\"),\n+\tPINCTRL_PIN(58, \"GPIO_58\"),\n+\tPINCTRL_PIN(59, \"GPIO_59\"),\n+\tPINCTRL_PIN(60, \"GPIO_60\"),\n+\tPINCTRL_PIN(61, \"GPIO_61\"),\n+\tPINCTRL_PIN(62, \"GPIO_62\"),\n+\tPINCTRL_PIN(63, \"GPIO_63\"),\n+\tPINCTRL_PIN(64, \"GPIO_64\"),\n+\tPINCTRL_PIN(65, \"GPIO_65\"),\n+\tPINCTRL_PIN(66, \"GPIO_66\"),\n+\tPINCTRL_PIN(67, \"GPIO_67\"),\n+\tPINCTRL_PIN(68, \"GPIO_68\"),\n+\tPINCTRL_PIN(69, \"GPIO_69\"),\n+\tPINCTRL_PIN(70, \"GPIO_70\"),\n+\tPINCTRL_PIN(71, \"GPIO_71\"),\n+\tPINCTRL_PIN(72, \"GPIO_72\"),\n+\tPINCTRL_PIN(73, \"GPIO_73\"),\n+\tPINCTRL_PIN(74, \"GPIO_74\"),\n+\tPINCTRL_PIN(75, \"GPIO_75\"),\n+\tPINCTRL_PIN(76, \"GPIO_76\"),\n+\tPINCTRL_PIN(77, \"GPIO_77\"),\n+\tPINCTRL_PIN(78, \"GPIO_78\"),\n+\tPINCTRL_PIN(79, \"GPIO_79\"),\n+\tPINCTRL_PIN(80, \"GPIO_80\"),\n+\tPINCTRL_PIN(81, \"GPIO_81\"),\n+\tPINCTRL_PIN(82, \"GPIO_82\"),\n+\tPINCTRL_PIN(83, \"GPIO_83\"),\n+\tPINCTRL_PIN(84, \"GPIO_84\"),\n+\tPINCTRL_PIN(85, \"GPIO_85\"),\n+\tPINCTRL_PIN(86, \"GPIO_86\"),\n+\tPINCTRL_PIN(87, \"GPIO_87\"),\n+\tPINCTRL_PIN(88, \"GPIO_88\"),\n+\tPINCTRL_PIN(89, \"GPIO_89\"),\n+\tPINCTRL_PIN(90, \"GPIO_90\"),\n+\tPINCTRL_PIN(91, \"GPIO_91\"),\n+\tPINCTRL_PIN(92, \"GPIO_92\"),\n+\tPINCTRL_PIN(93, \"GPIO_93\"),\n+\tPINCTRL_PIN(94, \"GPIO_94\"),\n+\tPINCTRL_PIN(95, \"GPIO_95\"),\n+\tPINCTRL_PIN(96, \"GPIO_96\"),\n+\tPINCTRL_PIN(97, \"GPIO_97\"),\n+\tPINCTRL_PIN(98, \"GPIO_98\"),\n+\tPINCTRL_PIN(99, \"GPIO_99\"),\n+\tPINCTRL_PIN(100, \"GPIO_100\"),\n+\tPINCTRL_PIN(101, \"GPIO_101\"),\n+\tPINCTRL_PIN(102, \"GPIO_102\"),\n+\tPINCTRL_PIN(103, \"GPIO_103\"),\n+\tPINCTRL_PIN(104, \"GPIO_104\"),\n+\tPINCTRL_PIN(105, \"GPIO_105\"),\n+\tPINCTRL_PIN(106, \"GPIO_106\"),\n+\tPINCTRL_PIN(107, \"GPIO_107\"),\n+\tPINCTRL_PIN(108, \"GPIO_108\"),\n+\tPINCTRL_PIN(109, \"GPIO_109\"),\n+\tPINCTRL_PIN(110, \"GPIO_110\"),\n+\tPINCTRL_PIN(111, \"GPIO_111\"),\n+\tPINCTRL_PIN(112, \"GPIO_112\"),\n+\tPINCTRL_PIN(113, \"GPIO_113\"),\n+\tPINCTRL_PIN(114, \"GPIO_114\"),\n+\tPINCTRL_PIN(115, \"GPIO_115\"),\n+\tPINCTRL_PIN(116, \"GPIO_116\"),\n+\tPINCTRL_PIN(117, \"GPIO_117\"),\n+\tPINCTRL_PIN(118, \"GPIO_118\"),\n+\tPINCTRL_PIN(119, \"GPIO_119\"),\n+\tPINCTRL_PIN(120, \"GPIO_120\"),\n+\tPINCTRL_PIN(121, \"GPIO_121\"),\n+\tPINCTRL_PIN(122, \"GPIO_122\"),\n+\tPINCTRL_PIN(123, \"GPIO_123\"),\n+\tPINCTRL_PIN(124, \"GPIO_124\"),\n+\tPINCTRL_PIN(125, \"GPIO_125\"),\n+\tPINCTRL_PIN(126, \"GPIO_126\"),\n+\tPINCTRL_PIN(127, \"GPIO_127\"),\n+\tPINCTRL_PIN(128, \"GPIO_128\"),\n+\tPINCTRL_PIN(129, \"GPIO_129\"),\n+\tPINCTRL_PIN(130, \"GPIO_130\"),\n+\tPINCTRL_PIN(131, \"GPIO_131\"),\n+\tPINCTRL_PIN(132, \"GPIO_132\"),\n+\tPINCTRL_PIN(133, \"GPIO_133\"),\n+\tPINCTRL_PIN(134, \"GPIO_134\"),\n+\tPINCTRL_PIN(135, \"GPIO_135\"),\n+\tPINCTRL_PIN(136, \"GPIO_136\"),\n+\tPINCTRL_PIN(137, \"GPIO_137\"),\n+\tPINCTRL_PIN(138, \"GPIO_138\"),\n+\tPINCTRL_PIN(139, \"GPIO_139\"),\n+\tPINCTRL_PIN(140, \"GPIO_140\"),\n+\tPINCTRL_PIN(141, \"GPIO_141\"),\n+\tPINCTRL_PIN(142, \"GPIO_142\"),\n+\tPINCTRL_PIN(143, \"GPIO_143\"),\n+\tPINCTRL_PIN(144, \"GPIO_144\"),\n+\tPINCTRL_PIN(145, \"GPIO_145\"),\n+\tPINCTRL_PIN(146, \"GPIO_146\"),\n+\tPINCTRL_PIN(147, \"GPIO_147\"),\n+\tPINCTRL_PIN(148, \"GPIO_148\"),\n+\tPINCTRL_PIN(149, \"GPIO_149\"),\n+\tPINCTRL_PIN(150, \"GPIO_150\"),\n+\tPINCTRL_PIN(151, \"GPIO_151\"),\n+\tPINCTRL_PIN(152, \"GPIO_152\"),\n+\tPINCTRL_PIN(153, \"GPIO_153\"),\n+\tPINCTRL_PIN(154, \"GPIO_154\"),\n+\tPINCTRL_PIN(155, \"GPIO_155\"),\n+\tPINCTRL_PIN(156, \"GPIO_156\"),\n+\tPINCTRL_PIN(157, \"GPIO_157\"),\n+\tPINCTRL_PIN(158, \"GPIO_158\"),\n+\tPINCTRL_PIN(159, \"GPIO_159\"),\n+\tPINCTRL_PIN(160, \"GPIO_160\"),\n+\tPINCTRL_PIN(161, \"GPIO_161\"),\n+\tPINCTRL_PIN(162, \"GPIO_162\"),\n+\tPINCTRL_PIN(163, \"GPIO_163\"),\n+\tPINCTRL_PIN(164, \"GPIO_164\"),\n+\tPINCTRL_PIN(165, \"GPIO_165\"),\n+\tPINCTRL_PIN(166, \"GPIO_166\"),\n+\tPINCTRL_PIN(167, \"GPIO_167\"),\n+\tPINCTRL_PIN(168, \"GPIO_168\"),\n+\tPINCTRL_PIN(169, \"GPIO_169\"),\n+\tPINCTRL_PIN(170, \"GPIO_170\"),\n+\tPINCTRL_PIN(171, \"GPIO_171\"),\n+\tPINCTRL_PIN(172, \"GPIO_172\"),\n+\tPINCTRL_PIN(173, \"GPIO_173\"),\n+\tPINCTRL_PIN(174, \"GPIO_174\"),\n+\tPINCTRL_PIN(175, \"GPIO_175\"),\n+\tPINCTRL_PIN(176, \"GPIO_176\"),\n+\tPINCTRL_PIN(177, \"GPIO_177\"),\n+\tPINCTRL_PIN(178, \"GPIO_178\"),\n+\tPINCTRL_PIN(179, \"GPIO_179\"),\n+\tPINCTRL_PIN(180, \"GPIO_180\"),\n+\tPINCTRL_PIN(181, \"UFS_RESET\"),\n+};\n+\n+#define DECLARE_MSM_GPIO_PINS(pin) \\\n+\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n+DECLARE_MSM_GPIO_PINS(0);\n+DECLARE_MSM_GPIO_PINS(1);\n+DECLARE_MSM_GPIO_PINS(2);\n+DECLARE_MSM_GPIO_PINS(3);\n+DECLARE_MSM_GPIO_PINS(4);\n+DECLARE_MSM_GPIO_PINS(5);\n+DECLARE_MSM_GPIO_PINS(6);\n+DECLARE_MSM_GPIO_PINS(7);\n+DECLARE_MSM_GPIO_PINS(8);\n+DECLARE_MSM_GPIO_PINS(9);\n+DECLARE_MSM_GPIO_PINS(10);\n+DECLARE_MSM_GPIO_PINS(11);\n+DECLARE_MSM_GPIO_PINS(12);\n+DECLARE_MSM_GPIO_PINS(13);\n+DECLARE_MSM_GPIO_PINS(14);\n+DECLARE_MSM_GPIO_PINS(15);\n+DECLARE_MSM_GPIO_PINS(16);\n+DECLARE_MSM_GPIO_PINS(17);\n+DECLARE_MSM_GPIO_PINS(18);\n+DECLARE_MSM_GPIO_PINS(19);\n+DECLARE_MSM_GPIO_PINS(20);\n+DECLARE_MSM_GPIO_PINS(21);\n+DECLARE_MSM_GPIO_PINS(22);\n+DECLARE_MSM_GPIO_PINS(23);\n+DECLARE_MSM_GPIO_PINS(24);\n+DECLARE_MSM_GPIO_PINS(25);\n+DECLARE_MSM_GPIO_PINS(26);\n+DECLARE_MSM_GPIO_PINS(27);\n+DECLARE_MSM_GPIO_PINS(28);\n+DECLARE_MSM_GPIO_PINS(29);\n+DECLARE_MSM_GPIO_PINS(30);\n+DECLARE_MSM_GPIO_PINS(31);\n+DECLARE_MSM_GPIO_PINS(32);\n+DECLARE_MSM_GPIO_PINS(33);\n+DECLARE_MSM_GPIO_PINS(34);\n+DECLARE_MSM_GPIO_PINS(35);\n+DECLARE_MSM_GPIO_PINS(36);\n+DECLARE_MSM_GPIO_PINS(37);\n+DECLARE_MSM_GPIO_PINS(38);\n+DECLARE_MSM_GPIO_PINS(39);\n+DECLARE_MSM_GPIO_PINS(40);\n+DECLARE_MSM_GPIO_PINS(41);\n+DECLARE_MSM_GPIO_PINS(42);\n+DECLARE_MSM_GPIO_PINS(43);\n+DECLARE_MSM_GPIO_PINS(44);\n+DECLARE_MSM_GPIO_PINS(45);\n+DECLARE_MSM_GPIO_PINS(46);\n+DECLARE_MSM_GPIO_PINS(47);\n+DECLARE_MSM_GPIO_PINS(48);\n+DECLARE_MSM_GPIO_PINS(49);\n+DECLARE_MSM_GPIO_PINS(50);\n+DECLARE_MSM_GPIO_PINS(51);\n+DECLARE_MSM_GPIO_PINS(52);\n+DECLARE_MSM_GPIO_PINS(53);\n+DECLARE_MSM_GPIO_PINS(54);\n+DECLARE_MSM_GPIO_PINS(55);\n+DECLARE_MSM_GPIO_PINS(56);\n+DECLARE_MSM_GPIO_PINS(57);\n+DECLARE_MSM_GPIO_PINS(58);\n+DECLARE_MSM_GPIO_PINS(59);\n+DECLARE_MSM_GPIO_PINS(60);\n+DECLARE_MSM_GPIO_PINS(61);\n+DECLARE_MSM_GPIO_PINS(62);\n+DECLARE_MSM_GPIO_PINS(63);\n+DECLARE_MSM_GPIO_PINS(64);\n+DECLARE_MSM_GPIO_PINS(65);\n+DECLARE_MSM_GPIO_PINS(66);\n+DECLARE_MSM_GPIO_PINS(67);\n+DECLARE_MSM_GPIO_PINS(68);\n+DECLARE_MSM_GPIO_PINS(69);\n+DECLARE_MSM_GPIO_PINS(70);\n+DECLARE_MSM_GPIO_PINS(71);\n+DECLARE_MSM_GPIO_PINS(72);\n+DECLARE_MSM_GPIO_PINS(73);\n+DECLARE_MSM_GPIO_PINS(74);\n+DECLARE_MSM_GPIO_PINS(75);\n+DECLARE_MSM_GPIO_PINS(76);\n+DECLARE_MSM_GPIO_PINS(77);\n+DECLARE_MSM_GPIO_PINS(78);\n+DECLARE_MSM_GPIO_PINS(79);\n+DECLARE_MSM_GPIO_PINS(80);\n+DECLARE_MSM_GPIO_PINS(81);\n+DECLARE_MSM_GPIO_PINS(82);\n+DECLARE_MSM_GPIO_PINS(83);\n+DECLARE_MSM_GPIO_PINS(84);\n+DECLARE_MSM_GPIO_PINS(85);\n+DECLARE_MSM_GPIO_PINS(86);\n+DECLARE_MSM_GPIO_PINS(87);\n+DECLARE_MSM_GPIO_PINS(88);\n+DECLARE_MSM_GPIO_PINS(89);\n+DECLARE_MSM_GPIO_PINS(90);\n+DECLARE_MSM_GPIO_PINS(91);\n+DECLARE_MSM_GPIO_PINS(92);\n+DECLARE_MSM_GPIO_PINS(93);\n+DECLARE_MSM_GPIO_PINS(94);\n+DECLARE_MSM_GPIO_PINS(95);\n+DECLARE_MSM_GPIO_PINS(96);\n+DECLARE_MSM_GPIO_PINS(97);\n+DECLARE_MSM_GPIO_PINS(98);\n+DECLARE_MSM_GPIO_PINS(99);\n+DECLARE_MSM_GPIO_PINS(100);\n+DECLARE_MSM_GPIO_PINS(101);\n+DECLARE_MSM_GPIO_PINS(102);\n+DECLARE_MSM_GPIO_PINS(103);\n+DECLARE_MSM_GPIO_PINS(104);\n+DECLARE_MSM_GPIO_PINS(105);\n+DECLARE_MSM_GPIO_PINS(106);\n+DECLARE_MSM_GPIO_PINS(107);\n+DECLARE_MSM_GPIO_PINS(108);\n+DECLARE_MSM_GPIO_PINS(109);\n+DECLARE_MSM_GPIO_PINS(110);\n+DECLARE_MSM_GPIO_PINS(111);\n+DECLARE_MSM_GPIO_PINS(112);\n+DECLARE_MSM_GPIO_PINS(113);\n+DECLARE_MSM_GPIO_PINS(114);\n+DECLARE_MSM_GPIO_PINS(115);\n+DECLARE_MSM_GPIO_PINS(116);\n+DECLARE_MSM_GPIO_PINS(117);\n+DECLARE_MSM_GPIO_PINS(118);\n+DECLARE_MSM_GPIO_PINS(119);\n+DECLARE_MSM_GPIO_PINS(120);\n+DECLARE_MSM_GPIO_PINS(121);\n+DECLARE_MSM_GPIO_PINS(122);\n+DECLARE_MSM_GPIO_PINS(123);\n+DECLARE_MSM_GPIO_PINS(124);\n+DECLARE_MSM_GPIO_PINS(125);\n+DECLARE_MSM_GPIO_PINS(126);\n+DECLARE_MSM_GPIO_PINS(127);\n+DECLARE_MSM_GPIO_PINS(128);\n+DECLARE_MSM_GPIO_PINS(129);\n+DECLARE_MSM_GPIO_PINS(130);\n+DECLARE_MSM_GPIO_PINS(131);\n+DECLARE_MSM_GPIO_PINS(132);\n+DECLARE_MSM_GPIO_PINS(133);\n+DECLARE_MSM_GPIO_PINS(134);\n+DECLARE_MSM_GPIO_PINS(135);\n+DECLARE_MSM_GPIO_PINS(136);\n+DECLARE_MSM_GPIO_PINS(137);\n+DECLARE_MSM_GPIO_PINS(138);\n+DECLARE_MSM_GPIO_PINS(139);\n+DECLARE_MSM_GPIO_PINS(140);\n+DECLARE_MSM_GPIO_PINS(141);\n+DECLARE_MSM_GPIO_PINS(142);\n+DECLARE_MSM_GPIO_PINS(143);\n+DECLARE_MSM_GPIO_PINS(144);\n+DECLARE_MSM_GPIO_PINS(145);\n+DECLARE_MSM_GPIO_PINS(146);\n+DECLARE_MSM_GPIO_PINS(147);\n+DECLARE_MSM_GPIO_PINS(148);\n+DECLARE_MSM_GPIO_PINS(149);\n+DECLARE_MSM_GPIO_PINS(150);\n+DECLARE_MSM_GPIO_PINS(151);\n+DECLARE_MSM_GPIO_PINS(152);\n+DECLARE_MSM_GPIO_PINS(153);\n+DECLARE_MSM_GPIO_PINS(154);\n+DECLARE_MSM_GPIO_PINS(155);\n+DECLARE_MSM_GPIO_PINS(156);\n+DECLARE_MSM_GPIO_PINS(157);\n+DECLARE_MSM_GPIO_PINS(158);\n+DECLARE_MSM_GPIO_PINS(159);\n+DECLARE_MSM_GPIO_PINS(160);\n+DECLARE_MSM_GPIO_PINS(161);\n+DECLARE_MSM_GPIO_PINS(162);\n+DECLARE_MSM_GPIO_PINS(163);\n+DECLARE_MSM_GPIO_PINS(164);\n+DECLARE_MSM_GPIO_PINS(165);\n+DECLARE_MSM_GPIO_PINS(166);\n+DECLARE_MSM_GPIO_PINS(167);\n+DECLARE_MSM_GPIO_PINS(168);\n+DECLARE_MSM_GPIO_PINS(169);\n+DECLARE_MSM_GPIO_PINS(170);\n+DECLARE_MSM_GPIO_PINS(171);\n+DECLARE_MSM_GPIO_PINS(172);\n+DECLARE_MSM_GPIO_PINS(173);\n+DECLARE_MSM_GPIO_PINS(174);\n+DECLARE_MSM_GPIO_PINS(175);\n+DECLARE_MSM_GPIO_PINS(176);\n+DECLARE_MSM_GPIO_PINS(177);\n+DECLARE_MSM_GPIO_PINS(178);\n+DECLARE_MSM_GPIO_PINS(179);\n+DECLARE_MSM_GPIO_PINS(180);\n+\n+static const unsigned int ufs_reset_pins[] = { 181 };\n+\n+enum nord_functions {\n+\tmsm_mux_gpio,\n+\tmsm_mux_aoss_cti,\n+\tmsm_mux_atest_char0,\n+\tmsm_mux_atest_char1,\n+\tmsm_mux_atest_char2,\n+\tmsm_mux_atest_char3,\n+\tmsm_mux_atest_char_start,\n+\tmsm_mux_atest_usb20,\n+\tmsm_mux_atest_usb21,\n+\tmsm_mux_aud_intfc0_clk,\n+\tmsm_mux_aud_intfc0_data0,\n+\tmsm_mux_aud_intfc0_data1,\n+\tmsm_mux_aud_intfc0_data2,\n+\tmsm_mux_aud_intfc0_data3,\n+\tmsm_mux_aud_intfc0_data4,\n+\tmsm_mux_aud_intfc0_data5,\n+\tmsm_mux_aud_intfc0_data6,\n+\tmsm_mux_aud_intfc0_data7,\n+\tmsm_mux_aud_intfc0_ws,\n+\tmsm_mux_aud_intfc10_clk,\n+\tmsm_mux_aud_intfc10_data0,\n+\tmsm_mux_aud_intfc10_data1,\n+\tmsm_mux_aud_intfc10_ws,\n+\tmsm_mux_aud_intfc1_clk,\n+\tmsm_mux_aud_intfc1_data0,\n+\tmsm_mux_aud_intfc1_data1,\n+\tmsm_mux_aud_intfc1_data2,\n+\tmsm_mux_aud_intfc1_data3,\n+\tmsm_mux_aud_intfc1_data4,\n+\tmsm_mux_aud_intfc1_data5,\n+\tmsm_mux_aud_intfc1_data6,\n+\tmsm_mux_aud_intfc1_data7,\n+\tmsm_mux_aud_intfc1_ws,\n+\tmsm_mux_aud_intfc2_clk,\n+\tmsm_mux_aud_intfc2_data0,\n+\tmsm_mux_aud_intfc2_data1,\n+\tmsm_mux_aud_intfc2_data2,\n+\tmsm_mux_aud_intfc2_data3,\n+\tmsm_mux_aud_intfc2_ws,\n+\tmsm_mux_aud_intfc3_clk,\n+\tmsm_mux_aud_intfc3_data0,\n+\tmsm_mux_aud_intfc3_data1,\n+\tmsm_mux_aud_intfc3_ws,\n+\tmsm_mux_aud_intfc4_clk,\n+\tmsm_mux_aud_intfc4_data0,\n+\tmsm_mux_aud_intfc4_data1,\n+\tmsm_mux_aud_intfc4_ws,\n+\tmsm_mux_aud_intfc5_clk,\n+\tmsm_mux_aud_intfc5_data0,\n+\tmsm_mux_aud_intfc5_data1,\n+\tmsm_mux_aud_intfc5_ws,\n+\tmsm_mux_aud_intfc6_clk,\n+\tmsm_mux_aud_intfc6_data0,\n+\tmsm_mux_aud_intfc6_data1,\n+\tmsm_mux_aud_intfc6_ws,\n+\tmsm_mux_aud_intfc7_clk,\n+\tmsm_mux_aud_intfc7_data0,\n+\tmsm_mux_aud_intfc7_data1,\n+\tmsm_mux_aud_intfc7_ws,\n+\tmsm_mux_aud_intfc8_clk,\n+\tmsm_mux_aud_intfc8_data0,\n+\tmsm_mux_aud_intfc8_data1,\n+\tmsm_mux_aud_intfc8_ws,\n+\tmsm_mux_aud_intfc9_clk,\n+\tmsm_mux_aud_intfc9_data0,\n+\tmsm_mux_aud_intfc9_ws,\n+\tmsm_mux_aud_mclk0_mira,\n+\tmsm_mux_aud_mclk0_mirb,\n+\tmsm_mux_aud_mclk1_mira,\n+\tmsm_mux_aud_mclk1_mirb,\n+\tmsm_mux_aud_mclk2_mira,\n+\tmsm_mux_aud_mclk2_mirb,\n+\tmsm_mux_aud_refclk0,\n+\tmsm_mux_aud_refclk1,\n+\tmsm_mux_bist_done,\n+\tmsm_mux_ccu_async_in0,\n+\tmsm_mux_ccu_async_in1,\n+\tmsm_mux_ccu_async_in2,\n+\tmsm_mux_ccu_async_in3,\n+\tmsm_mux_ccu_async_in4,\n+\tmsm_mux_ccu_async_in5,\n+\tmsm_mux_ccu_i2c_scl0,\n+\tmsm_mux_ccu_i2c_scl1,\n+\tmsm_mux_ccu_i2c_scl2,\n+\tmsm_mux_ccu_i2c_scl3,\n+\tmsm_mux_ccu_i2c_scl4,\n+\tmsm_mux_ccu_i2c_scl5,\n+\tmsm_mux_ccu_i2c_scl6,\n+\tmsm_mux_ccu_i2c_scl7,\n+\tmsm_mux_ccu_i2c_scl8,\n+\tmsm_mux_ccu_i2c_scl9,\n+\tmsm_mux_ccu_i2c_sda0,\n+\tmsm_mux_ccu_i2c_sda1,\n+\tmsm_mux_ccu_i2c_sda2,\n+\tmsm_mux_ccu_i2c_sda3,\n+\tmsm_mux_ccu_i2c_sda4,\n+\tmsm_mux_ccu_i2c_sda5,\n+\tmsm_mux_ccu_i2c_sda6,\n+\tmsm_mux_ccu_i2c_sda7,\n+\tmsm_mux_ccu_i2c_sda8,\n+\tmsm_mux_ccu_i2c_sda9,\n+\tmsm_mux_ccu_timer0,\n+\tmsm_mux_ccu_timer1,\n+\tmsm_mux_ccu_timer10,\n+\tmsm_mux_ccu_timer11,\n+\tmsm_mux_ccu_timer12,\n+\tmsm_mux_ccu_timer13,\n+\tmsm_mux_ccu_timer14,\n+\tmsm_mux_ccu_timer15,\n+\tmsm_mux_ccu_timer2,\n+\tmsm_mux_ccu_timer3,\n+\tmsm_mux_ccu_timer4,\n+\tmsm_mux_ccu_timer5,\n+\tmsm_mux_ccu_timer6,\n+\tmsm_mux_ccu_timer7,\n+\tmsm_mux_ccu_timer8,\n+\tmsm_mux_ccu_timer9,\n+\tmsm_mux_clink_debug,\n+\tmsm_mux_dbg_out,\n+\tmsm_mux_dbg_out_clk,\n+\tmsm_mux_ddr_bist_complete,\n+\tmsm_mux_ddr_bist_fail,\n+\tmsm_mux_ddr_bist_start,\n+\tmsm_mux_ddr_bist_stop,\n+\tmsm_mux_ddr_pxi0,\n+\tmsm_mux_ddr_pxi1,\n+\tmsm_mux_ddr_pxi10,\n+\tmsm_mux_ddr_pxi11,\n+\tmsm_mux_ddr_pxi12,\n+\tmsm_mux_ddr_pxi13,\n+\tmsm_mux_ddr_pxi14,\n+\tmsm_mux_ddr_pxi15,\n+\tmsm_mux_ddr_pxi2,\n+\tmsm_mux_ddr_pxi3,\n+\tmsm_mux_ddr_pxi4,\n+\tmsm_mux_ddr_pxi5,\n+\tmsm_mux_ddr_pxi6,\n+\tmsm_mux_ddr_pxi7,\n+\tmsm_mux_ddr_pxi8,\n+\tmsm_mux_ddr_pxi9,\n+\tmsm_mux_dp_rx0,\n+\tmsm_mux_dp_rx00,\n+\tmsm_mux_dp_rx01,\n+\tmsm_mux_dp_rx0_mute,\n+\tmsm_mux_dp_rx1,\n+\tmsm_mux_dp_rx10,\n+\tmsm_mux_dp_rx11,\n+\tmsm_mux_dp_rx1_mute,\n+\tmsm_mux_edp0_hot,\n+\tmsm_mux_edp0_lcd,\n+\tmsm_mux_edp1_hot,\n+\tmsm_mux_edp1_lcd,\n+\tmsm_mux_edp2_hot,\n+\tmsm_mux_edp2_lcd,\n+\tmsm_mux_edp3_hot,\n+\tmsm_mux_edp3_lcd,\n+\tmsm_mux_emac0_mcg0,\n+\tmsm_mux_emac0_mcg1,\n+\tmsm_mux_emac0_mcg2,\n+\tmsm_mux_emac0_mcg3,\n+\tmsm_mux_emac0_mdc,\n+\tmsm_mux_emac0_mdio,\n+\tmsm_mux_emac0_ptp,\n+\tmsm_mux_emac1_mcg0,\n+\tmsm_mux_emac1_mcg1,\n+\tmsm_mux_emac1_mcg2,\n+\tmsm_mux_emac1_mcg3,\n+\tmsm_mux_emac1_mdc,\n+\tmsm_mux_emac1_mdio,\n+\tmsm_mux_emac1_ptp,\n+\tmsm_mux_gcc_gp1_clk,\n+\tmsm_mux_gcc_gp2_clk,\n+\tmsm_mux_gcc_gp3_clk,\n+\tmsm_mux_gcc_gp4_clk,\n+\tmsm_mux_gcc_gp5_clk,\n+\tmsm_mux_gcc_gp6_clk,\n+\tmsm_mux_gcc_gp7_clk,\n+\tmsm_mux_gcc_gp8_clk,\n+\tmsm_mux_jitter_bist,\n+\tmsm_mux_lbist_pass,\n+\tmsm_mux_mbist_pass,\n+\tmsm_mux_mdp0_vsync0_out,\n+\tmsm_mux_mdp0_vsync10_out,\n+\tmsm_mux_mdp0_vsync1_out,\n+\tmsm_mux_mdp0_vsync2_out,\n+\tmsm_mux_mdp0_vsync3_out,\n+\tmsm_mux_mdp0_vsync4_out,\n+\tmsm_mux_mdp0_vsync5_out,\n+\tmsm_mux_mdp0_vsync6_out,\n+\tmsm_mux_mdp0_vsync7_out,\n+\tmsm_mux_mdp0_vsync8_out,\n+\tmsm_mux_mdp0_vsync9_out,\n+\tmsm_mux_mdp1_vsync0_out,\n+\tmsm_mux_mdp1_vsync10_out,\n+\tmsm_mux_mdp1_vsync1_out,\n+\tmsm_mux_mdp1_vsync2_out,\n+\tmsm_mux_mdp1_vsync3_out,\n+\tmsm_mux_mdp1_vsync4_out,\n+\tmsm_mux_mdp1_vsync5_out,\n+\tmsm_mux_mdp1_vsync6_out,\n+\tmsm_mux_mdp1_vsync7_out,\n+\tmsm_mux_mdp1_vsync8_out,\n+\tmsm_mux_mdp1_vsync9_out,\n+\tmsm_mux_mdp_vsync_e,\n+\tmsm_mux_mdp_vsync_p,\n+\tmsm_mux_mdp_vsync_s,\n+\tmsm_mux_pcie0_clk_req_n,\n+\tmsm_mux_pcie1_clk_req_n,\n+\tmsm_mux_pcie2_clk_req_n,\n+\tmsm_mux_pcie3_clk_req_n,\n+\tmsm_mux_phase_flag0,\n+\tmsm_mux_phase_flag1,\n+\tmsm_mux_phase_flag10,\n+\tmsm_mux_phase_flag11,\n+\tmsm_mux_phase_flag12,\n+\tmsm_mux_phase_flag13,\n+\tmsm_mux_phase_flag14,\n+\tmsm_mux_phase_flag15,\n+\tmsm_mux_phase_flag16,\n+\tmsm_mux_phase_flag17,\n+\tmsm_mux_phase_flag18,\n+\tmsm_mux_phase_flag19,\n+\tmsm_mux_phase_flag2,\n+\tmsm_mux_phase_flag20,\n+\tmsm_mux_phase_flag21,\n+\tmsm_mux_phase_flag22,\n+\tmsm_mux_phase_flag23,\n+\tmsm_mux_phase_flag24,\n+\tmsm_mux_phase_flag25,\n+\tmsm_mux_phase_flag26,\n+\tmsm_mux_phase_flag27,\n+\tmsm_mux_phase_flag28,\n+\tmsm_mux_phase_flag29,\n+\tmsm_mux_phase_flag3,\n+\tmsm_mux_phase_flag30,\n+\tmsm_mux_phase_flag31,\n+\tmsm_mux_phase_flag4,\n+\tmsm_mux_phase_flag5,\n+\tmsm_mux_phase_flag6,\n+\tmsm_mux_phase_flag7,\n+\tmsm_mux_phase_flag8,\n+\tmsm_mux_phase_flag9,\n+\tmsm_mux_pll_bist_sync,\n+\tmsm_mux_pll_clk_aux,\n+\tmsm_mux_prng_rosc0,\n+\tmsm_mux_prng_rosc1,\n+\tmsm_mux_pwrbrk_i_n,\n+\tmsm_mux_qdss_cti,\n+\tmsm_mux_qdss_gpio,\n+\tmsm_mux_qdss_gpio0,\n+\tmsm_mux_qdss_gpio1,\n+\tmsm_mux_qdss_gpio10,\n+\tmsm_mux_qdss_gpio11,\n+\tmsm_mux_qdss_gpio12,\n+\tmsm_mux_qdss_gpio13,\n+\tmsm_mux_qdss_gpio14,\n+\tmsm_mux_qdss_gpio15,\n+\tmsm_mux_qdss_gpio2,\n+\tmsm_mux_qdss_gpio3,\n+\tmsm_mux_qdss_gpio4,\n+\tmsm_mux_qdss_gpio5,\n+\tmsm_mux_qdss_gpio6,\n+\tmsm_mux_qdss_gpio7,\n+\tmsm_mux_qdss_gpio8,\n+\tmsm_mux_qdss_gpio9,\n+\tmsm_mux_qspi0,\n+\tmsm_mux_qspi1,\n+\tmsm_mux_qspi2,\n+\tmsm_mux_qspi3,\n+\tmsm_mux_qspi_clk,\n+\tmsm_mux_qspi_cs0_n,\n+\tmsm_mux_qspi_cs1_n,\n+\tmsm_mux_qup0_se0_l0,\n+\tmsm_mux_qup0_se0_l1,\n+\tmsm_mux_qup0_se0_l2,\n+\tmsm_mux_qup0_se0_l3,\n+\tmsm_mux_qup0_se1_l0,\n+\tmsm_mux_qup0_se1_l1,\n+\tmsm_mux_qup0_se1_l2,\n+\tmsm_mux_qup0_se1_l3,\n+\tmsm_mux_qup0_se2_l0,\n+\tmsm_mux_qup0_se2_l1,\n+\tmsm_mux_qup0_se2_l2,\n+\tmsm_mux_qup0_se2_l3,\n+\tmsm_mux_qup0_se3_l0,\n+\tmsm_mux_qup0_se3_l1,\n+\tmsm_mux_qup0_se3_l2,\n+\tmsm_mux_qup0_se3_l3,\n+\tmsm_mux_qup0_se4_l0,\n+\tmsm_mux_qup0_se4_l1,\n+\tmsm_mux_qup0_se4_l2,\n+\tmsm_mux_qup0_se4_l3,\n+\tmsm_mux_qup0_se5_l0,\n+\tmsm_mux_qup0_se5_l1,\n+\tmsm_mux_qup0_se5_l2,\n+\tmsm_mux_qup0_se5_l3,\n+\tmsm_mux_qup1_se0_l0,\n+\tmsm_mux_qup1_se0_l1,\n+\tmsm_mux_qup1_se0_l2,\n+\tmsm_mux_qup1_se0_l3,\n+\tmsm_mux_qup1_se1_l0,\n+\tmsm_mux_qup1_se1_l1,\n+\tmsm_mux_qup1_se1_l2,\n+\tmsm_mux_qup1_se1_l3,\n+\tmsm_mux_qup1_se2_l0,\n+\tmsm_mux_qup1_se2_l1,\n+\tmsm_mux_qup1_se2_l2,\n+\tmsm_mux_qup1_se2_l3,\n+\tmsm_mux_qup1_se3_l0,\n+\tmsm_mux_qup1_se3_l1,\n+\tmsm_mux_qup1_se3_l2,\n+\tmsm_mux_qup1_se3_l3,\n+\tmsm_mux_qup1_se4_l0,\n+\tmsm_mux_qup1_se4_l1,\n+\tmsm_mux_qup1_se4_l2,\n+\tmsm_mux_qup1_se4_l3,\n+\tmsm_mux_qup1_se5_l0,\n+\tmsm_mux_qup1_se5_l1,\n+\tmsm_mux_qup1_se5_l2,\n+\tmsm_mux_qup1_se5_l3,\n+\tmsm_mux_qup1_se6_l0,\n+\tmsm_mux_qup1_se6_l1,\n+\tmsm_mux_qup1_se6_l2,\n+\tmsm_mux_qup1_se6_l3,\n+\tmsm_mux_qup2_se0_l0,\n+\tmsm_mux_qup2_se0_l1,\n+\tmsm_mux_qup2_se0_l2,\n+\tmsm_mux_qup2_se0_l3,\n+\tmsm_mux_qup2_se1_l0,\n+\tmsm_mux_qup2_se1_l1,\n+\tmsm_mux_qup2_se1_l2,\n+\tmsm_mux_qup2_se1_l3,\n+\tmsm_mux_qup2_se2_l0,\n+\tmsm_mux_qup2_se2_l1,\n+\tmsm_mux_qup2_se2_l2,\n+\tmsm_mux_qup2_se2_l3,\n+\tmsm_mux_qup2_se2_l4,\n+\tmsm_mux_qup2_se3_l0,\n+\tmsm_mux_qup2_se3_l1,\n+\tmsm_mux_qup2_se3_l2,\n+\tmsm_mux_qup2_se3_l3,\n+\tmsm_mux_qup2_se4_l0,\n+\tmsm_mux_qup2_se4_l1,\n+\tmsm_mux_qup2_se4_l2,\n+\tmsm_mux_qup2_se4_l3,\n+\tmsm_mux_qup2_se4_l4,\n+\tmsm_mux_qup2_se4_l5,\n+\tmsm_mux_qup2_se4_l6,\n+\tmsm_mux_qup2_se5_l0,\n+\tmsm_mux_qup2_se5_l1,\n+\tmsm_mux_qup2_se5_l2,\n+\tmsm_mux_qup2_se5_l3,\n+\tmsm_mux_qup2_se6_l0,\n+\tmsm_mux_qup2_se6_l1,\n+\tmsm_mux_qup2_se6_l2,\n+\tmsm_mux_qup2_se6_l3,\n+\tmsm_mux_qup3_se0_l0_mira,\n+\tmsm_mux_qup3_se0_l0_mirb,\n+\tmsm_mux_qup3_se0_l1_mira,\n+\tmsm_mux_qup3_se0_l1_mirb,\n+\tmsm_mux_qup3_se0_l2,\n+\tmsm_mux_qup3_se0_l3,\n+\tmsm_mux_qup3_se0_l4,\n+\tmsm_mux_qup3_se0_l5,\n+\tmsm_mux_qup3_se0_l6,\n+\tmsm_mux_sailss_ospi,\n+\tmsm_mux_sdc4_clk,\n+\tmsm_mux_sdc4_cmd,\n+\tmsm_mux_sdc4_data,\n+\tmsm_mux_smb_alert,\n+\tmsm_mux_smb_alert_n,\n+\tmsm_mux_smb_clk,\n+\tmsm_mux_smb_dat,\n+\tmsm_mux_tb_trig_sdc4,\n+\tmsm_mux_tmess_prng0,\n+\tmsm_mux_tmess_prng1,\n+\tmsm_mux_tsc_timer0,\n+\tmsm_mux_tsc_timer1,\n+\tmsm_mux_tsc_timer2,\n+\tmsm_mux_tsc_timer3,\n+\tmsm_mux_tsc_timer4,\n+\tmsm_mux_tsc_timer5,\n+\tmsm_mux_tsc_timer6,\n+\tmsm_mux_tsc_timer7,\n+\tmsm_mux_tsc_timer8,\n+\tmsm_mux_tsc_timer9,\n+\tmsm_mux_tsense_pwm1,\n+\tmsm_mux_tsense_pwm2,\n+\tmsm_mux_tsense_pwm3,\n+\tmsm_mux_tsense_pwm4,\n+\tmsm_mux_tsense_pwm5,\n+\tmsm_mux_tsense_pwm6,\n+\tmsm_mux_tsense_pwm7,\n+\tmsm_mux_tsense_pwm8,\n+\tmsm_mux_usb0_hs,\n+\tmsm_mux_usb0_phy_ps,\n+\tmsm_mux_usb1_hs,\n+\tmsm_mux_usb1_phy_ps,\n+\tmsm_mux_usb2_hs,\n+\tmsm_mux_usxgmii0_phy,\n+\tmsm_mux_usxgmii1_phy,\n+\tmsm_mux_vsense_trigger_mirnat,\n+\tmsm_mux_wcn_sw,\n+\tmsm_mux_wcn_sw_ctrl,\n+\tmsm_mux__,\n+};\n+\n+static const char *const gpio_groups[] = {\n+\t\"gpio0\",   \"gpio1\",   \"gpio2\",\t \"gpio3\",   \"gpio4\",   \"gpio5\",\n+\t\"gpio6\",   \"gpio7\",   \"gpio8\",\t \"gpio9\",   \"gpio10\",  \"gpio11\",\n+\t\"gpio12\",  \"gpio13\",  \"gpio14\",\t \"gpio15\",  \"gpio16\",  \"gpio17\",\n+\t\"gpio18\",  \"gpio19\",  \"gpio20\",\t \"gpio21\",  \"gpio22\",  \"gpio23\",\n+\t\"gpio24\",  \"gpio25\",  \"gpio26\",\t \"gpio27\",  \"gpio28\",  \"gpio29\",\n+\t\"gpio30\",  \"gpio31\",  \"gpio32\",\t \"gpio33\",  \"gpio34\",  \"gpio35\",\n+\t\"gpio36\",  \"gpio37\",  \"gpio38\",\t \"gpio39\",  \"gpio40\",  \"gpio41\",\n+\t\"gpio42\",  \"gpio43\",  \"gpio44\",\t \"gpio45\",  \"gpio46\",  \"gpio47\",\n+\t\"gpio48\",  \"gpio49\",  \"gpio50\",\t \"gpio51\",  \"gpio52\",  \"gpio53\",\n+\t\"gpio54\",  \"gpio55\",  \"gpio56\",\t \"gpio57\",  \"gpio58\",  \"gpio59\",\n+\t\"gpio60\",  \"gpio61\",  \"gpio62\",\t \"gpio63\",  \"gpio64\",  \"gpio65\",\n+\t\"gpio66\",  \"gpio67\",  \"gpio68\",\t \"gpio69\",  \"gpio70\",  \"gpio71\",\n+\t\"gpio72\",  \"gpio73\",  \"gpio74\",\t \"gpio75\",  \"gpio76\",  \"gpio77\",\n+\t\"gpio78\",  \"gpio79\",  \"gpio80\",\t \"gpio81\",  \"gpio82\",  \"gpio83\",\n+\t\"gpio84\",  \"gpio85\",  \"gpio86\",\t \"gpio87\",  \"gpio88\",  \"gpio89\",\n+\t\"gpio90\",  \"gpio91\",  \"gpio92\",\t \"gpio93\",  \"gpio94\",  \"gpio95\",\n+\t\"gpio96\",  \"gpio97\",  \"gpio98\",\t \"gpio99\",  \"gpio100\", \"gpio101\",\n+\t\"gpio102\", \"gpio103\", \"gpio104\", \"gpio105\", \"gpio106\", \"gpio107\",\n+\t\"gpio108\", \"gpio109\", \"gpio110\", \"gpio111\", \"gpio112\", \"gpio113\",\n+\t\"gpio114\", \"gpio115\", \"gpio116\", \"gpio117\", \"gpio118\", \"gpio119\",\n+\t\"gpio120\", \"gpio121\", \"gpio122\", \"gpio123\", \"gpio124\", \"gpio125\",\n+\t\"gpio126\", \"gpio127\", \"gpio128\", \"gpio129\", \"gpio130\", \"gpio131\",\n+\t\"gpio132\", \"gpio133\", \"gpio134\", \"gpio135\", \"gpio136\", \"gpio137\",\n+\t\"gpio138\", \"gpio139\", \"gpio140\", \"gpio141\", \"gpio142\", \"gpio143\",\n+\t\"gpio144\", \"gpio145\", \"gpio146\", \"gpio147\", \"gpio148\", \"gpio149\",\n+\t\"gpio150\", \"gpio151\", \"gpio152\", \"gpio153\", \"gpio154\", \"gpio155\",\n+\t\"gpio156\", \"gpio157\", \"gpio158\", \"gpio159\", \"gpio160\", \"gpio161\",\n+\t\"gpio162\", \"gpio163\", \"gpio164\", \"gpio165\", \"gpio166\", \"gpio167\",\n+\t\"gpio168\", \"gpio169\", \"gpio170\", \"gpio171\", \"gpio172\", \"gpio173\",\n+\t\"gpio174\", \"gpio175\", \"gpio176\", \"gpio177\", \"gpio178\", \"gpio179\",\n+\t\"gpio180\",\n+};\n+\n+static const char *const aoss_cti_groups[] = {\n+\t\"gpio83\",\n+\t\"gpio84\",\n+\t\"gpio85\",\n+\t\"gpio86\",\n+};\n+\n+static const char *const atest_char0_groups[] = {\n+\t\"gpio177\",\n+};\n+\n+static const char *const atest_char1_groups[] = {\n+\t\"gpio178\",\n+};\n+\n+static const char *const atest_char2_groups[] = {\n+\t\"gpio179\",\n+};\n+\n+static const char *const atest_char3_groups[] = {\n+\t\"gpio180\",\n+};\n+\n+static const char *const atest_char_start_groups[] = {\n+\t\"gpio176\",\n+};\n+\n+static const char *const atest_usb20_groups[] = {\n+\t\"gpio126\",\n+\t\"gpio128\",\n+\t\"gpio130\",\n+};\n+\n+static const char *const atest_usb21_groups[] = {\n+\t\"gpio127\",\n+\t\"gpio129\",\n+\t\"gpio131\",\n+};\n+\n+static const char *const aud_intfc0_clk_groups[] = {\n+\t\"gpio57\",\n+};\n+\n+static const char *const aud_intfc0_data0_groups[] = {\n+\t\"gpio59\",\n+};\n+\n+static const char *const aud_intfc0_data1_groups[] = {\n+\t\"gpio60\",\n+};\n+\n+static const char *const aud_intfc0_data2_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char *const aud_intfc0_data3_groups[] = {\n+\t\"gpio62\",\n+};\n+\n+static const char *const aud_intfc0_data4_groups[] = {\n+\t\"gpio63\",\n+};\n+\n+static const char *const aud_intfc0_data5_groups[] = {\n+\t\"gpio64\",\n+};\n+\n+static const char *const aud_intfc0_data6_groups[] = {\n+\t\"gpio65\",\n+};\n+\n+static const char *const aud_intfc0_data7_groups[] = {\n+\t\"gpio66\",\n+};\n+\n+static const char *const aud_intfc0_ws_groups[] = {\n+\t\"gpio58\",\n+};\n+\n+static const char *const aud_intfc10_clk_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char *const aud_intfc10_data0_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const char *const aud_intfc10_data1_groups[] = {\n+\t\"gpio82\",\n+};\n+\n+static const char *const aud_intfc10_ws_groups[] = {\n+\t\"gpio62\",\n+};\n+\n+static const char *const aud_intfc1_clk_groups[] = {\n+\t\"gpio67\",\n+};\n+\n+static const char *const aud_intfc1_data0_groups[] = {\n+\t\"gpio69\",\n+};\n+\n+static const char *const aud_intfc1_data1_groups[] = {\n+\t\"gpio70\",\n+};\n+\n+static const char *const aud_intfc1_data2_groups[] = {\n+\t\"gpio71\",\n+};\n+\n+static const char *const aud_intfc1_data3_groups[] = {\n+\t\"gpio72\",\n+};\n+\n+static const char *const aud_intfc1_data4_groups[] = {\n+\t\"gpio73\",\n+};\n+\n+static const char *const aud_intfc1_data5_groups[] = {\n+\t\"gpio74\",\n+};\n+\n+static const char *const aud_intfc1_data6_groups[] = {\n+\t\"gpio75\",\n+};\n+\n+static const char *const aud_intfc1_data7_groups[] = {\n+\t\"gpio76\",\n+};\n+\n+static const char *const aud_intfc1_ws_groups[] = {\n+\t\"gpio68\",\n+};\n+\n+static const char *const aud_intfc2_clk_groups[] = {\n+\t\"gpio77\",\n+};\n+\n+static const char *const aud_intfc2_data0_groups[] = {\n+\t\"gpio79\",\n+};\n+\n+static const char *const aud_intfc2_data1_groups[] = {\n+\t\"gpio80\",\n+};\n+\n+static const char *const aud_intfc2_data2_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const char *const aud_intfc2_data3_groups[] = {\n+\t\"gpio82\",\n+};\n+\n+static const char *const aud_intfc2_ws_groups[] = {\n+\t\"gpio78\",\n+};\n+\n+static const char *const aud_intfc3_clk_groups[] = {\n+\t\"gpio83\",\n+};\n+\n+static const char *const aud_intfc3_data0_groups[] = {\n+\t\"gpio85\",\n+};\n+\n+static const char *const aud_intfc3_data1_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const aud_intfc3_ws_groups[] = {\n+\t\"gpio84\",\n+};\n+\n+static const char *const aud_intfc4_clk_groups[] = {\n+\t\"gpio87\",\n+};\n+\n+static const char *const aud_intfc4_data0_groups[] = {\n+\t\"gpio89\",\n+};\n+\n+static const char *const aud_intfc4_data1_groups[] = {\n+\t\"gpio90\",\n+};\n+\n+static const char *const aud_intfc4_ws_groups[] = {\n+\t\"gpio88\",\n+};\n+\n+static const char *const aud_intfc5_clk_groups[] = {\n+\t\"gpio91\",\n+};\n+\n+static const char *const aud_intfc5_data0_groups[] = {\n+\t\"gpio93\",\n+};\n+\n+static const char *const aud_intfc5_data1_groups[] = {\n+\t\"gpio94\",\n+};\n+\n+static const char *const aud_intfc5_ws_groups[] = {\n+\t\"gpio92\",\n+};\n+\n+static const char *const aud_intfc6_clk_groups[] = {\n+\t\"gpio95\",\n+};\n+\n+static const char *const aud_intfc6_data0_groups[] = {\n+\t\"gpio97\",\n+};\n+\n+static const char *const aud_intfc6_data1_groups[] = {\n+\t\"gpio98\",\n+};\n+\n+static const char *const aud_intfc6_ws_groups[] = {\n+\t\"gpio96\",\n+};\n+\n+static const char *const aud_intfc7_clk_groups[] = {\n+\t\"gpio63\",\n+};\n+\n+static const char *const aud_intfc7_data0_groups[] = {\n+\t\"gpio65\",\n+};\n+\n+static const char *const aud_intfc7_data1_groups[] = {\n+\t\"gpio66\",\n+};\n+\n+static const char *const aud_intfc7_ws_groups[] = {\n+\t\"gpio64\",\n+};\n+\n+static const char *const aud_intfc8_clk_groups[] = {\n+\t\"gpio73\",\n+};\n+\n+static const char *const aud_intfc8_data0_groups[] = {\n+\t\"gpio75\",\n+};\n+\n+static const char *const aud_intfc8_data1_groups[] = {\n+\t\"gpio76\",\n+};\n+\n+static const char *const aud_intfc8_ws_groups[] = {\n+\t\"gpio74\",\n+};\n+\n+static const char *const aud_intfc9_clk_groups[] = {\n+\t\"gpio70\",\n+};\n+\n+static const char *const aud_intfc9_data0_groups[] = {\n+\t\"gpio72\",\n+};\n+\n+static const char *const aud_intfc9_ws_groups[] = {\n+\t\"gpio71\",\n+};\n+\n+static const char *const aud_mclk0_mira_groups[] = {\n+\t\"gpio99\",\n+};\n+\n+static const char *const aud_mclk0_mirb_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const aud_mclk1_mira_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const aud_mclk1_mirb_groups[] = {\n+\t\"gpio90\",\n+};\n+\n+static const char *const aud_mclk2_mira_groups[] = {\n+\t\"gpio101\",\n+};\n+\n+static const char *const aud_mclk2_mirb_groups[] = {\n+\t\"gpio94\",\n+};\n+\n+static const char *const aud_refclk0_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const aud_refclk1_groups[] = {\n+\t\"gpio101\",\n+};\n+\n+static const char *const bist_done_groups[] = {\n+\t\"gpio168\",\n+};\n+\n+static const char *const ccu_async_in0_groups[] = {\n+\t\"gpio176\",\n+};\n+\n+static const char *const ccu_async_in1_groups[] = {\n+\t\"gpio177\",\n+};\n+\n+static const char *const ccu_async_in2_groups[] = {\n+\t\"gpio178\",\n+};\n+\n+static const char *const ccu_async_in3_groups[] = {\n+\t\"gpio179\",\n+};\n+\n+static const char *const ccu_async_in4_groups[] = {\n+\t\"gpio180\",\n+};\n+\n+static const char *const ccu_async_in5_groups[] = {\n+\t\"gpio45\",\n+};\n+\n+static const char *const ccu_i2c_scl0_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char *const ccu_i2c_scl1_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char *const ccu_i2c_scl2_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char *const ccu_i2c_scl3_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char *const ccu_i2c_scl4_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char *const ccu_i2c_scl5_groups[] = {\n+\t\"gpio114\",\n+};\n+\n+static const char *const ccu_i2c_scl6_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const ccu_i2c_scl7_groups[] = {\n+\t\"gpio126\",\n+};\n+\n+static const char *const ccu_i2c_scl8_groups[] = {\n+\t\"gpio130\",\n+};\n+\n+static const char *const ccu_i2c_scl9_groups[] = {\n+\t\"gpio132\",\n+};\n+\n+static const char *const ccu_i2c_sda0_groups[] = {\n+\t\"gpio15\",\n+};\n+\n+static const char *const ccu_i2c_sda1_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char *const ccu_i2c_sda2_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char *const ccu_i2c_sda3_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char *const ccu_i2c_sda4_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char *const ccu_i2c_sda5_groups[] = {\n+\t\"gpio113\",\n+};\n+\n+static const char *const ccu_i2c_sda6_groups[] = {\n+\t\"gpio115\",\n+};\n+\n+static const char *const ccu_i2c_sda7_groups[] = {\n+\t\"gpio125\",\n+};\n+\n+static const char *const ccu_i2c_sda8_groups[] = {\n+\t\"gpio129\",\n+};\n+\n+static const char *const ccu_i2c_sda9_groups[] = {\n+\t\"gpio131\",\n+};\n+\n+static const char *const ccu_timer0_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char *const ccu_timer1_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char *const ccu_timer10_groups[] = {\n+\t\"gpio143\",\n+};\n+\n+static const char *const ccu_timer11_groups[] = {\n+\t\"gpio144\",\n+};\n+\n+static const char *const ccu_timer12_groups[] = {\n+\t\"gpio150\",\n+};\n+\n+static const char *const ccu_timer13_groups[] = {\n+\t\"gpio151\",\n+};\n+\n+static const char *const ccu_timer14_groups[] = {\n+\t\"gpio152\",\n+};\n+\n+static const char *const ccu_timer15_groups[] = {\n+\t\"gpio153\",\n+};\n+\n+static const char *const ccu_timer2_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char *const ccu_timer3_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char *const ccu_timer4_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char *const ccu_timer5_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char *const ccu_timer6_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char *const ccu_timer7_groups[] = {\n+\t\"gpio32\",\n+};\n+\n+static const char *const ccu_timer8_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char *const ccu_timer9_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char *const clink_debug_groups[] = {\n+\t\"gpio12\", \"gpio13\", \"gpio14\", \"gpio51\",\n+\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio55\",\n+};\n+\n+static const char *const dbg_out_groups[] = {\n+\t\"gpio113\",\n+};\n+\n+static const char *const dbg_out_clk_groups[] = {\n+\t\"gpio165\",\n+};\n+\n+static const char *const ddr_bist_complete_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char *const ddr_bist_fail_groups[] = {\n+\t\"gpio39\",\n+};\n+\n+static const char *const ddr_bist_start_groups[] = {\n+\t\"gpio36\",\n+};\n+\n+static const char *const ddr_bist_stop_groups[] = {\n+\t\"gpio38\",\n+};\n+\n+static const char *const ddr_pxi0_groups[] = {\n+\t\"gpio99\",\n+\t\"gpio100\",\n+};\n+\n+static const char *const ddr_pxi1_groups[] = {\n+\t\"gpio109\",\n+\t\"gpio110\",\n+};\n+\n+static const char *const ddr_pxi10_groups[] = {\n+\t\"gpio130\",\n+\t\"gpio131\",\n+};\n+\n+static const char *const ddr_pxi11_groups[] = {\n+\t\"gpio132\",\n+\t\"gpio133\",\n+};\n+\n+static const char *const ddr_pxi12_groups[] = {\n+\t\"gpio134\",\n+\t\"gpio135\",\n+};\n+\n+static const char *const ddr_pxi13_groups[] = {\n+\t\"gpio136\",\n+\t\"gpio137\",\n+};\n+\n+static const char *const ddr_pxi14_groups[] = {\n+\t\"gpio138\",\n+\t\"gpio139\",\n+};\n+\n+static const char *const ddr_pxi15_groups[] = {\n+\t\"gpio162\",\n+\t\"gpio163\",\n+};\n+\n+static const char *const ddr_pxi2_groups[] = {\n+\t\"gpio113\",\n+\t\"gpio114\",\n+};\n+\n+static const char *const ddr_pxi3_groups[] = {\n+\t\"gpio115\",\n+\t\"gpio116\",\n+};\n+\n+static const char *const ddr_pxi4_groups[] = {\n+\t\"gpio117\",\n+\t\"gpio118\",\n+};\n+\n+static const char *const ddr_pxi5_groups[] = {\n+\t\"gpio164\",\n+\t\"gpio165\",\n+};\n+\n+static const char *const ddr_pxi6_groups[] = {\n+\t\"gpio119\",\n+\t\"gpio120\",\n+};\n+\n+static const char *const ddr_pxi7_groups[] = {\n+\t\"gpio121\",\n+\t\"gpio122\",\n+};\n+\n+static const char *const ddr_pxi8_groups[] = {\n+\t\"gpio126\",\n+\t\"gpio127\",\n+};\n+\n+static const char *const ddr_pxi9_groups[] = {\n+\t\"gpio128\",\n+\t\"gpio129\",\n+};\n+\n+static const char *const dp_rx0_groups[] = {\n+\t\"gpio55\", \"gpio83\", \"gpio84\",  \"gpio85\",  \"gpio86\",\n+\t\"gpio88\", \"gpio89\", \"gpio137\", \"gpio138\",\n+};\n+\n+static const char *const dp_rx00_groups[] = {\n+\t\"gpio99\",\n+};\n+\n+static const char *const dp_rx01_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const dp_rx0_mute_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char *const dp_rx1_groups[] = {\n+\t\"gpio56\", \"gpio92\", \"gpio93\",  \"gpio95\",  \"gpio96\",\n+\t\"gpio97\", \"gpio98\", \"gpio158\", \"gpio159\",\n+};\n+\n+static const char *const dp_rx10_groups[] = {\n+\t\"gpio121\",\n+};\n+\n+static const char *const dp_rx11_groups[] = {\n+\t\"gpio122\",\n+};\n+\n+static const char *const dp_rx1_mute_groups[] = {\n+\t\"gpio36\",\n+};\n+\n+static const char *const edp0_hot_groups[] = {\n+\t\"gpio51\",\n+};\n+\n+static const char *const edp0_lcd_groups[] = {\n+\t\"gpio47\",\n+};\n+\n+static const char *const edp1_hot_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const edp1_lcd_groups[] = {\n+\t\"gpio48\",\n+};\n+\n+static const char *const edp2_hot_groups[] = {\n+\t\"gpio53\",\n+};\n+\n+static const char *const edp2_lcd_groups[] = {\n+\t\"gpio49\",\n+};\n+\n+static const char *const edp3_hot_groups[] = {\n+\t\"gpio54\",\n+};\n+\n+static const char *const edp3_lcd_groups[] = {\n+\t\"gpio50\",\n+};\n+\n+static const char *const emac0_mcg0_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char *const emac0_mcg1_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char *const emac0_mcg2_groups[] = {\n+\t\"gpio18\",\n+};\n+\n+static const char *const emac0_mcg3_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char *const emac0_mdc_groups[] = {\n+\t\"gpio47\",\n+};\n+\n+static const char *const emac0_mdio_groups[] = {\n+\t\"gpio48\",\n+};\n+\n+static const char *const emac0_ptp_groups[] = {\n+\t\"gpio133\", \"gpio134\", \"gpio135\", \"gpio136\",\n+\t\"gpio139\", \"gpio140\", \"gpio141\", \"gpio142\",\n+};\n+\n+static const char *const emac1_mcg0_groups[] = {\n+\t\"gpio20\",\n+};\n+\n+static const char *const emac1_mcg1_groups[] = {\n+\t\"gpio21\",\n+};\n+\n+static const char *const emac1_mcg2_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char *const emac1_mcg3_groups[] = {\n+\t\"gpio23\",\n+};\n+\n+static const char *const emac1_mdc_groups[] = {\n+\t\"gpio49\",\n+};\n+\n+static const char *const emac1_mdio_groups[] = {\n+\t\"gpio50\",\n+};\n+\n+static const char *const emac1_ptp_groups[] = {\n+\t\"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\",\n+\t\"gpio41\", \"gpio42\", \"gpio43\", \"gpio44\",\n+};\n+\n+static const char *const gcc_gp1_clk_groups[] = {\n+\t\"gpio51\",\n+};\n+\n+static const char *const gcc_gp2_clk_groups[] = {\n+\t\"gpio52\",\n+};\n+\n+static const char *const gcc_gp3_clk_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char *const gcc_gp4_clk_groups[] = {\n+\t\"gpio43\",\n+};\n+\n+static const char *const gcc_gp5_clk_groups[] = {\n+\t\"gpio105\",\n+};\n+\n+static const char *const gcc_gp6_clk_groups[] = {\n+\t\"gpio106\",\n+};\n+\n+static const char *const gcc_gp7_clk_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char *const gcc_gp8_clk_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char *const jitter_bist_groups[] = {\n+\t\"gpio123\",\n+\t\"gpio138\",\n+};\n+\n+static const char *const lbist_pass_groups[] = {\n+\t\"gpio121\",\n+};\n+\n+static const char *const mbist_pass_groups[] = {\n+\t\"gpio122\",\n+};\n+\n+static const char *const mdp0_vsync0_out_groups[] = {\n+\t\"gpio113\",\n+};\n+\n+static const char *const mdp0_vsync10_out_groups[] = {\n+\t\"gpio143\",\n+};\n+\n+static const char *const mdp0_vsync1_out_groups[] = {\n+\t\"gpio114\",\n+};\n+\n+static const char *const mdp0_vsync2_out_groups[] = {\n+\t\"gpio115\",\n+};\n+\n+static const char *const mdp0_vsync3_out_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const mdp0_vsync4_out_groups[] = {\n+\t\"gpio121\",\n+};\n+\n+static const char *const mdp0_vsync5_out_groups[] = {\n+\t\"gpio122\",\n+};\n+\n+static const char *const mdp0_vsync6_out_groups[] = {\n+\t\"gpio139\",\n+};\n+\n+static const char *const mdp0_vsync7_out_groups[] = {\n+\t\"gpio140\",\n+};\n+\n+static const char *const mdp0_vsync8_out_groups[] = {\n+\t\"gpio141\",\n+};\n+\n+static const char *const mdp0_vsync9_out_groups[] = {\n+\t\"gpio142\",\n+};\n+\n+static const char *const mdp1_vsync0_out_groups[] = {\n+\t\"gpio123\",\n+};\n+\n+static const char *const mdp1_vsync10_out_groups[] = {\n+\t\"gpio135\",\n+};\n+\n+static const char *const mdp1_vsync1_out_groups[] = {\n+\t\"gpio124\",\n+};\n+\n+static const char *const mdp1_vsync2_out_groups[] = {\n+\t\"gpio125\",\n+};\n+\n+static const char *const mdp1_vsync3_out_groups[] = {\n+\t\"gpio126\",\n+};\n+\n+static const char *const mdp1_vsync4_out_groups[] = {\n+\t\"gpio129\",\n+};\n+\n+static const char *const mdp1_vsync5_out_groups[] = {\n+\t\"gpio130\",\n+};\n+\n+static const char *const mdp1_vsync6_out_groups[] = {\n+\t\"gpio131\",\n+};\n+\n+static const char *const mdp1_vsync7_out_groups[] = {\n+\t\"gpio132\",\n+};\n+\n+static const char *const mdp1_vsync8_out_groups[] = {\n+\t\"gpio133\",\n+};\n+\n+static const char *const mdp1_vsync9_out_groups[] = {\n+\t\"gpio134\",\n+};\n+\n+static const char *const mdp_vsync_e_groups[] = {\n+\t\"gpio109\",\n+};\n+\n+static const char *const mdp_vsync_p_groups[] = {\n+\t\"gpio110\",\n+};\n+\n+static const char *const mdp_vsync_s_groups[] = {\n+\t\"gpio144\",\n+};\n+\n+static const char *const pcie0_clk_req_n_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char *const pcie1_clk_req_n_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char *const pcie2_clk_req_n_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char *const pcie3_clk_req_n_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char *const phase_flag0_groups[] = {\n+\t\"gpio98\",\n+};\n+\n+static const char *const phase_flag1_groups[] = {\n+\t\"gpio82\",\n+};\n+\n+static const char *const phase_flag10_groups[] = {\n+\t\"gpio90\",\n+};\n+\n+static const char *const phase_flag11_groups[] = {\n+\t\"gpio91\",\n+};\n+\n+static const char *const phase_flag12_groups[] = {\n+\t\"gpio92\",\n+};\n+\n+static const char *const phase_flag13_groups[] = {\n+\t\"gpio93\",\n+};\n+\n+static const char *const phase_flag14_groups[] = {\n+\t\"gpio94\",\n+};\n+\n+static const char *const phase_flag15_groups[] = {\n+\t\"gpio95\",\n+};\n+\n+static const char *const phase_flag16_groups[] = {\n+\t\"gpio96\",\n+};\n+\n+static const char *const phase_flag17_groups[] = {\n+\t\"gpio101\",\n+};\n+\n+static const char *const phase_flag18_groups[] = {\n+\t\"gpio67\",\n+};\n+\n+static const char *const phase_flag19_groups[] = {\n+\t\"gpio68\",\n+};\n+\n+static const char *const phase_flag2_groups[] = {\n+\t\"gpio81\",\n+};\n+\n+static const char *const phase_flag20_groups[] = {\n+\t\"gpio69\",\n+};\n+\n+static const char *const phase_flag21_groups[] = {\n+\t\"gpio70\",\n+};\n+\n+static const char *const phase_flag22_groups[] = {\n+\t\"gpio71\",\n+};\n+\n+static const char *const phase_flag23_groups[] = {\n+\t\"gpio72\",\n+};\n+\n+static const char *const phase_flag24_groups[] = {\n+\t\"gpio73\",\n+};\n+\n+static const char *const phase_flag25_groups[] = {\n+\t\"gpio74\",\n+};\n+\n+static const char *const phase_flag26_groups[] = {\n+\t\"gpio75\",\n+};\n+\n+static const char *const phase_flag27_groups[] = {\n+\t\"gpio76\",\n+};\n+\n+static const char *const phase_flag28_groups[] = {\n+\t\"gpio83\",\n+};\n+\n+static const char *const phase_flag29_groups[] = {\n+\t\"gpio84\",\n+};\n+\n+static const char *const phase_flag3_groups[] = {\n+\t\"gpio80\",\n+};\n+\n+static const char *const phase_flag30_groups[] = {\n+\t\"gpio85\",\n+};\n+\n+static const char *const phase_flag31_groups[] = {\n+\t\"gpio86\",\n+};\n+\n+static const char *const phase_flag4_groups[] = {\n+\t\"gpio79\",\n+};\n+\n+static const char *const phase_flag5_groups[] = {\n+\t\"gpio78\",\n+};\n+\n+static const char *const phase_flag6_groups[] = {\n+\t\"gpio77\",\n+};\n+\n+static const char *const phase_flag7_groups[] = {\n+\t\"gpio87\",\n+};\n+\n+static const char *const phase_flag8_groups[] = {\n+\t\"gpio88\",\n+};\n+\n+static const char *const phase_flag9_groups[] = {\n+\t\"gpio89\",\n+};\n+\n+static const char *const pll_bist_sync_groups[] = {\n+\t\"gpio176\",\n+};\n+\n+static const char *const pll_clk_aux_groups[] = {\n+\t\"gpio100\",\n+};\n+\n+static const char *const prng_rosc0_groups[] = {\n+\t\"gpio117\",\n+};\n+\n+static const char *const prng_rosc1_groups[] = {\n+\t\"gpio118\",\n+};\n+\n+static const char *const pwrbrk_i_n_groups[] = {\n+\t\"gpio167\",\n+};\n+\n+static const char *const qdss_cti_groups[] = {\n+\t\"gpio41\",  \"gpio42\",  \"gpio110\", \"gpio138\",\n+\t\"gpio142\", \"gpio144\", \"gpio162\", \"gpio163\",\n+};\n+\n+static const char *const qdss_gpio_groups[] = {\n+\t\"gpio75\",\n+\t\"gpio76\",\n+\t\"gpio93\",\n+\t\"gpio108\",\n+};\n+\n+static const char *const qdss_gpio0_groups[] = {\n+\t\"gpio67\",\n+\t\"gpio85\",\n+};\n+\n+static const char *const qdss_gpio1_groups[] = {\n+\t\"gpio68\",\n+\t\"gpio86\",\n+};\n+\n+static const char *const qdss_gpio10_groups[] = {\n+\t\"gpio79\",\n+\t\"gpio96\",\n+};\n+\n+static const char *const qdss_gpio11_groups[] = {\n+\t\"gpio80\",\n+\t\"gpio97\",\n+};\n+\n+static const char *const qdss_gpio12_groups[] = {\n+\t\"gpio81\",\n+\t\"gpio98\",\n+};\n+\n+static const char *const qdss_gpio13_groups[] = {\n+\t\"gpio82\",\n+\t\"gpio99\",\n+};\n+\n+static const char *const qdss_gpio14_groups[] = {\n+\t\"gpio83\",\n+\t\"gpio100\",\n+};\n+\n+static const char *const qdss_gpio15_groups[] = {\n+\t\"gpio84\",\n+\t\"gpio101\",\n+};\n+\n+static const char *const qdss_gpio2_groups[] = {\n+\t\"gpio69\",\n+\t\"gpio87\",\n+};\n+\n+static const char *const qdss_gpio3_groups[] = {\n+\t\"gpio70\",\n+\t\"gpio88\",\n+};\n+\n+static const char *const qdss_gpio4_groups[] = {\n+\t\"gpio71\",\n+\t\"gpio89\",\n+};\n+\n+static const char *const qdss_gpio5_groups[] = {\n+\t\"gpio72\",\n+\t\"gpio90\",\n+};\n+\n+static const char *const qdss_gpio6_groups[] = {\n+\t\"gpio73\",\n+\t\"gpio91\",\n+};\n+\n+static const char *const qdss_gpio7_groups[] = {\n+\t\"gpio74\",\n+\t\"gpio92\",\n+};\n+\n+static const char *const qdss_gpio8_groups[] = {\n+\t\"gpio77\",\n+\t\"gpio94\",\n+};\n+\n+static const char *const qdss_gpio9_groups[] = {\n+\t\"gpio78\",\n+\t\"gpio95\",\n+};\n+\n+static const char *const qspi0_groups[] = {\n+\t\"gpio102\",\n+};\n+\n+static const char *const qspi1_groups[] = {\n+\t\"gpio103\",\n+};\n+\n+static const char *const qspi2_groups[] = {\n+\t\"gpio106\",\n+};\n+\n+static const char *const qspi3_groups[] = {\n+\t\"gpio107\",\n+};\n+\n+static const char *const qspi_clk_groups[] = {\n+\t\"gpio104\",\n+};\n+\n+static const char *const qspi_cs0_n_groups[] = {\n+\t\"gpio105\",\n+};\n+\n+static const char *const qspi_cs1_n_groups[] = {\n+\t\"gpio108\",\n+};\n+\n+static const char *const qup0_se0_l0_groups[] = {\n+\t\"gpio111\",\n+};\n+\n+static const char *const qup0_se0_l1_groups[] = {\n+\t\"gpio112\",\n+};\n+\n+static const char *const qup0_se0_l2_groups[] = {\n+\t\"gpio109\",\n+};\n+\n+static const char *const qup0_se0_l3_groups[] = {\n+\t\"gpio110\",\n+};\n+\n+static const char *const qup0_se1_l0_groups[] = {\n+\t\"gpio111\",\n+};\n+\n+static const char *const qup0_se1_l1_groups[] = {\n+\t\"gpio112\",\n+};\n+\n+static const char *const qup0_se1_l2_groups[] = {\n+\t\"gpio109\",\n+};\n+\n+static const char *const qup0_se1_l3_groups[] = {\n+\t\"gpio110\",\n+};\n+\n+static const char *const qup0_se2_l0_groups[] = {\n+\t\"gpio113\",\n+};\n+\n+static const char *const qup0_se2_l1_groups[] = {\n+\t\"gpio114\",\n+};\n+\n+static const char *const qup0_se2_l2_groups[] = {\n+\t\"gpio115\",\n+};\n+\n+static const char *const qup0_se2_l3_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const qup0_se3_l0_groups[] = {\n+\t\"gpio115\",\n+};\n+\n+static const char *const qup0_se3_l1_groups[] = {\n+\t\"gpio116\",\n+};\n+\n+static const char *const qup0_se3_l2_groups[] = {\n+\t\"gpio113\",\n+};\n+\n+static const char *const qup0_se3_l3_groups[] = {\n+\t\"gpio114\",\n+};\n+\n+static const char *const qup0_se4_l0_groups[] = {\n+\t\"gpio117\",\n+};\n+\n+static const char *const qup0_se4_l1_groups[] = {\n+\t\"gpio118\",\n+};\n+\n+static const char *const qup0_se4_l2_groups[] = {\n+\t\"gpio119\",\n+};\n+\n+static const char *const qup0_se4_l3_groups[] = {\n+\t\"gpio120\",\n+};\n+\n+static const char *const qup0_se5_l0_groups[] = {\n+\t\"gpio121\",\n+};\n+\n+static const char *const qup0_se5_l1_groups[] = {\n+\t\"gpio122\",\n+};\n+\n+static const char *const qup0_se5_l2_groups[] = {\n+\t\"gpio109\",\n+};\n+\n+static const char *const qup0_se5_l3_groups[] = {\n+\t\"gpio110\",\n+};\n+\n+static const char *const qup1_se0_l0_groups[] = {\n+\t\"gpio123\",\n+};\n+\n+static const char *const qup1_se0_l1_groups[] = {\n+\t\"gpio124\",\n+};\n+\n+static const char *const qup1_se0_l2_groups[] = {\n+\t\"gpio125\",\n+};\n+\n+static const char *const qup1_se0_l3_groups[] = {\n+\t\"gpio126\",\n+};\n+\n+static const char *const qup1_se1_l0_groups[] = {\n+\t\"gpio125\",\n+};\n+\n+static const char *const qup1_se1_l1_groups[] = {\n+\t\"gpio126\",\n+};\n+\n+static const char *const qup1_se1_l2_groups[] = {\n+\t\"gpio123\",\n+};\n+\n+static const char *const qup1_se1_l3_groups[] = {\n+\t\"gpio124\",\n+};\n+\n+static const char *const qup1_se2_l0_groups[] = {\n+\t\"gpio127\",\n+};\n+\n+static const char *const qup1_se2_l1_groups[] = {\n+\t\"gpio128\",\n+};\n+\n+static const char *const qup1_se2_l2_groups[] = {\n+\t\"gpio127\",\n+};\n+\n+static const char *const qup1_se2_l3_groups[] = {\n+\t\"gpio128\",\n+};\n+\n+static const char *const qup1_se3_l0_groups[] = {\n+\t\"gpio129\",\n+};\n+\n+static const char *const qup1_se3_l1_groups[] = {\n+\t\"gpio130\",\n+};\n+\n+static const char *const qup1_se3_l2_groups[] = {\n+\t\"gpio129\",\n+};\n+\n+static const char *const qup1_se3_l3_groups[] = {\n+\t\"gpio130\",\n+};\n+\n+static const char *const qup1_se4_l0_groups[] = {\n+\t\"gpio131\",\n+};\n+\n+static const char *const qup1_se4_l1_groups[] = {\n+\t\"gpio132\",\n+};\n+\n+static const char *const qup1_se4_l2_groups[] = {\n+\t\"gpio137\",\n+};\n+\n+static const char *const qup1_se4_l3_groups[] = {\n+\t\"gpio138\",\n+};\n+\n+static const char *const qup1_se5_l0_groups[] = {\n+\t\"gpio133\",\n+};\n+\n+static const char *const qup1_se5_l1_groups[] = {\n+\t\"gpio134\",\n+};\n+\n+static const char *const qup1_se5_l2_groups[] = {\n+\t\"gpio135\",\n+};\n+\n+static const char *const qup1_se5_l3_groups[] = {\n+\t\"gpio136\",\n+};\n+\n+static const char *const qup1_se6_l0_groups[] = {\n+\t\"gpio137\",\n+};\n+\n+static const char *const qup1_se6_l1_groups[] = {\n+\t\"gpio138\",\n+};\n+\n+static const char *const qup1_se6_l2_groups[] = {\n+\t\"gpio131\",\n+};\n+\n+static const char *const qup1_se6_l3_groups[] = {\n+\t\"gpio132\",\n+};\n+\n+static const char *const qup2_se0_l0_groups[] = {\n+\t\"gpio139\",\n+};\n+\n+static const char *const qup2_se0_l1_groups[] = {\n+\t\"gpio140\",\n+};\n+\n+static const char *const qup2_se0_l2_groups[] = {\n+\t\"gpio141\",\n+};\n+\n+static const char *const qup2_se0_l3_groups[] = {\n+\t\"gpio142\",\n+};\n+\n+static const char *const qup2_se1_l0_groups[] = {\n+\t\"gpio154\",\n+};\n+\n+static const char *const qup2_se1_l1_groups[] = {\n+\t\"gpio155\",\n+};\n+\n+static const char *const qup2_se1_l2_groups[] = {\n+\t\"gpio143\",\n+};\n+\n+static const char *const qup2_se1_l3_groups[] = {\n+\t\"gpio144\",\n+};\n+\n+static const char *const qup2_se2_l0_groups[] = {\n+\t\"gpio145\",\n+};\n+\n+static const char *const qup2_se2_l1_groups[] = {\n+\t\"gpio146\",\n+};\n+\n+static const char *const qup2_se2_l2_groups[] = {\n+\t\"gpio147\",\n+};\n+\n+static const char *const qup2_se2_l3_groups[] = {\n+\t\"gpio148\",\n+};\n+\n+static const char *const qup2_se2_l4_groups[] = {\n+\t\"gpio149\",\n+};\n+\n+static const char *const qup2_se3_l0_groups[] = {\n+\t\"gpio150\",\n+};\n+\n+static const char *const qup2_se3_l1_groups[] = {\n+\t\"gpio151\",\n+};\n+\n+static const char *const qup2_se3_l2_groups[] = {\n+\t\"gpio152\",\n+};\n+\n+static const char *const qup2_se3_l3_groups[] = {\n+\t\"gpio153\",\n+};\n+\n+static const char *const qup2_se4_l0_groups[] = {\n+\t\"gpio154\",\n+};\n+\n+static const char *const qup2_se4_l1_groups[] = {\n+\t\"gpio155\",\n+};\n+\n+static const char *const qup2_se4_l2_groups[] = {\n+\t\"gpio143\",\n+};\n+\n+static const char *const qup2_se4_l3_groups[] = {\n+\t\"gpio144\",\n+};\n+\n+static const char *const qup2_se4_l4_groups[] = {\n+\t\"gpio150\",\n+};\n+\n+static const char *const qup2_se4_l5_groups[] = {\n+\t\"gpio151\",\n+};\n+\n+static const char *const qup2_se4_l6_groups[] = {\n+\t\"gpio152\",\n+};\n+\n+static const char *const qup2_se5_l0_groups[] = {\n+\t\"gpio156\",\n+};\n+\n+static const char *const qup2_se5_l1_groups[] = {\n+\t\"gpio157\",\n+};\n+\n+static const char *const qup2_se5_l2_groups[] = {\n+\t\"gpio158\",\n+};\n+\n+static const char *const qup2_se5_l3_groups[] = {\n+\t\"gpio159\",\n+};\n+\n+static const char *const qup2_se6_l0_groups[] = {\n+\t\"gpio158\",\n+};\n+\n+static const char *const qup2_se6_l1_groups[] = {\n+\t\"gpio159\",\n+};\n+\n+static const char *const qup2_se6_l2_groups[] = {\n+\t\"gpio156\",\n+};\n+\n+static const char *const qup2_se6_l3_groups[] = {\n+\t\"gpio157\",\n+};\n+\n+static const char *const qup3_se0_l0_mira_groups[] = {\n+\t\"gpio102\",\n+};\n+\n+static const char *const qup3_se0_l0_mirb_groups[] = {\n+\t\"gpio103\",\n+};\n+\n+static const char *const qup3_se0_l1_mira_groups[] = {\n+\t\"gpio103\",\n+};\n+\n+static const char *const qup3_se0_l1_mirb_groups[] = {\n+\t\"gpio102\",\n+};\n+\n+static const char *const qup3_se0_l2_groups[] = {\n+\t\"gpio104\",\n+};\n+\n+static const char *const qup3_se0_l3_groups[] = {\n+\t\"gpio105\",\n+};\n+\n+static const char *const qup3_se0_l4_groups[] = {\n+\t\"gpio106\",\n+};\n+\n+static const char *const qup3_se0_l5_groups[] = {\n+\t\"gpio107\",\n+};\n+\n+static const char *const qup3_se0_l6_groups[] = {\n+\t\"gpio108\",\n+};\n+\n+static const char *const sailss_ospi_groups[] = {\n+\t\"gpio164\",\n+\t\"gpio165\",\n+};\n+\n+static const char *const sdc4_clk_groups[] = {\n+\t\"gpio175\",\n+};\n+\n+static const char *const sdc4_cmd_groups[] = {\n+\t\"gpio174\",\n+};\n+\n+static const char *const sdc4_data_groups[] = {\n+\t\"gpio170\",\n+\t\"gpio171\",\n+\t\"gpio172\",\n+\t\"gpio173\",\n+};\n+\n+static const char *const smb_alert_groups[] = {\n+\t\"gpio110\",\n+};\n+\n+static const char *const smb_alert_n_groups[] = {\n+\t\"gpio109\",\n+};\n+\n+static const char *const smb_clk_groups[] = {\n+\t\"gpio112\",\n+};\n+\n+static const char *const smb_dat_groups[] = {\n+\t\"gpio111\",\n+};\n+\n+static const char *const tb_trig_sdc4_groups[] = {\n+\t\"gpio169\",\n+};\n+\n+static const char *const tmess_prng0_groups[] = {\n+\t\"gpio94\",\n+};\n+\n+static const char *const tmess_prng1_groups[] = {\n+\t\"gpio95\",\n+};\n+\n+static const char *const tsc_timer0_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char *const tsc_timer1_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char *const tsc_timer2_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char *const tsc_timer3_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char *const tsc_timer4_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char *const tsc_timer5_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char *const tsc_timer6_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char *const tsc_timer7_groups[] = {\n+\t\"gpio32\",\n+};\n+\n+static const char *const tsc_timer8_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char *const tsc_timer9_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char *const tsense_pwm1_groups[] = {\n+\t\"gpio43\",\n+};\n+\n+static const char *const tsense_pwm2_groups[] = {\n+\t\"gpio44\",\n+};\n+\n+static const char *const tsense_pwm3_groups[] = {\n+\t\"gpio45\",\n+};\n+\n+static const char *const tsense_pwm4_groups[] = {\n+\t\"gpio46\",\n+};\n+\n+static const char *const tsense_pwm5_groups[] = {\n+\t\"gpio47\",\n+};\n+\n+static const char *const tsense_pwm6_groups[] = {\n+\t\"gpio48\",\n+};\n+\n+static const char *const tsense_pwm7_groups[] = {\n+\t\"gpio49\",\n+};\n+\n+static const char *const tsense_pwm8_groups[] = {\n+\t\"gpio50\",\n+};\n+\n+static const char *const usb0_hs_groups[] = {\n+\t\"gpio12\",\n+};\n+\n+static const char *const usb0_phy_ps_groups[] = {\n+\t\"gpio164\",\n+};\n+\n+static const char *const usb1_hs_groups[] = {\n+\t\"gpio13\",\n+};\n+\n+static const char *const usb1_phy_ps_groups[] = {\n+\t\"gpio165\",\n+};\n+\n+static const char *const usb2_hs_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char *const usxgmii0_phy_groups[] = {\n+\t\"gpio45\",\n+};\n+\n+static const char *const usxgmii1_phy_groups[] = {\n+\t\"gpio46\",\n+};\n+\n+static const char *const vsense_trigger_mirnat_groups[] = {\n+\t\"gpio132\",\n+};\n+\n+static const char *const wcn_sw_groups[] = {\n+\t\"gpio161\",\n+};\n+\n+static const char *const wcn_sw_ctrl_groups[] = {\n+\t\"gpio160\",\n+};\n+\n+static const struct pinfunction nord_functions[] = {\n+\tMSM_GPIO_PIN_FUNCTION(gpio),\n+\tMSM_PIN_FUNCTION(aoss_cti),\n+\tMSM_PIN_FUNCTION(atest_char0),\n+\tMSM_PIN_FUNCTION(atest_char1),\n+\tMSM_PIN_FUNCTION(atest_char2),\n+\tMSM_PIN_FUNCTION(atest_char3),\n+\tMSM_PIN_FUNCTION(atest_char_start),\n+\tMSM_PIN_FUNCTION(atest_usb20),\n+\tMSM_PIN_FUNCTION(atest_usb21),\n+\tMSM_PIN_FUNCTION(aud_intfc0_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data2),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data3),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data4),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data5),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data6),\n+\tMSM_PIN_FUNCTION(aud_intfc0_data7),\n+\tMSM_PIN_FUNCTION(aud_intfc0_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc10_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc10_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc10_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc10_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc1_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data2),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data3),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data4),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data5),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data6),\n+\tMSM_PIN_FUNCTION(aud_intfc1_data7),\n+\tMSM_PIN_FUNCTION(aud_intfc1_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc2_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc2_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc2_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc2_data2),\n+\tMSM_PIN_FUNCTION(aud_intfc2_data3),\n+\tMSM_PIN_FUNCTION(aud_intfc2_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc3_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc3_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc3_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc3_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc4_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc4_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc4_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc4_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc5_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc5_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc5_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc5_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc6_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc6_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc6_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc6_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc7_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc7_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc7_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc7_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc8_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc8_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc8_data1),\n+\tMSM_PIN_FUNCTION(aud_intfc8_ws),\n+\tMSM_PIN_FUNCTION(aud_intfc9_clk),\n+\tMSM_PIN_FUNCTION(aud_intfc9_data0),\n+\tMSM_PIN_FUNCTION(aud_intfc9_ws),\n+\tMSM_PIN_FUNCTION(aud_mclk0_mira),\n+\tMSM_PIN_FUNCTION(aud_mclk0_mirb),\n+\tMSM_PIN_FUNCTION(aud_mclk1_mira),\n+\tMSM_PIN_FUNCTION(aud_mclk1_mirb),\n+\tMSM_PIN_FUNCTION(aud_mclk2_mira),\n+\tMSM_PIN_FUNCTION(aud_mclk2_mirb),\n+\tMSM_PIN_FUNCTION(aud_refclk0),\n+\tMSM_PIN_FUNCTION(aud_refclk1),\n+\tMSM_PIN_FUNCTION(bist_done),\n+\tMSM_PIN_FUNCTION(ccu_async_in0),\n+\tMSM_PIN_FUNCTION(ccu_async_in1),\n+\tMSM_PIN_FUNCTION(ccu_async_in2),\n+\tMSM_PIN_FUNCTION(ccu_async_in3),\n+\tMSM_PIN_FUNCTION(ccu_async_in4),\n+\tMSM_PIN_FUNCTION(ccu_async_in5),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl0),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl1),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl2),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl3),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl4),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl5),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl6),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl7),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl8),\n+\tMSM_PIN_FUNCTION(ccu_i2c_scl9),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda0),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda1),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda2),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda3),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda4),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda5),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda6),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda7),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda8),\n+\tMSM_PIN_FUNCTION(ccu_i2c_sda9),\n+\tMSM_PIN_FUNCTION(ccu_timer0),\n+\tMSM_PIN_FUNCTION(ccu_timer1),\n+\tMSM_PIN_FUNCTION(ccu_timer10),\n+\tMSM_PIN_FUNCTION(ccu_timer11),\n+\tMSM_PIN_FUNCTION(ccu_timer12),\n+\tMSM_PIN_FUNCTION(ccu_timer13),\n+\tMSM_PIN_FUNCTION(ccu_timer14),\n+\tMSM_PIN_FUNCTION(ccu_timer15),\n+\tMSM_PIN_FUNCTION(ccu_timer2),\n+\tMSM_PIN_FUNCTION(ccu_timer3),\n+\tMSM_PIN_FUNCTION(ccu_timer4),\n+\tMSM_PIN_FUNCTION(ccu_timer5),\n+\tMSM_PIN_FUNCTION(ccu_timer6),\n+\tMSM_PIN_FUNCTION(ccu_timer7),\n+\tMSM_PIN_FUNCTION(ccu_timer8),\n+\tMSM_PIN_FUNCTION(ccu_timer9),\n+\tMSM_PIN_FUNCTION(clink_debug),\n+\tMSM_PIN_FUNCTION(dbg_out),\n+\tMSM_PIN_FUNCTION(dbg_out_clk),\n+\tMSM_PIN_FUNCTION(ddr_bist_complete),\n+\tMSM_PIN_FUNCTION(ddr_bist_fail),\n+\tMSM_PIN_FUNCTION(ddr_bist_start),\n+\tMSM_PIN_FUNCTION(ddr_bist_stop),\n+\tMSM_PIN_FUNCTION(ddr_pxi0),\n+\tMSM_PIN_FUNCTION(ddr_pxi1),\n+\tMSM_PIN_FUNCTION(ddr_pxi10),\n+\tMSM_PIN_FUNCTION(ddr_pxi11),\n+\tMSM_PIN_FUNCTION(ddr_pxi12),\n+\tMSM_PIN_FUNCTION(ddr_pxi13),\n+\tMSM_PIN_FUNCTION(ddr_pxi14),\n+\tMSM_PIN_FUNCTION(ddr_pxi15),\n+\tMSM_PIN_FUNCTION(ddr_pxi2),\n+\tMSM_PIN_FUNCTION(ddr_pxi3),\n+\tMSM_PIN_FUNCTION(ddr_pxi4),\n+\tMSM_PIN_FUNCTION(ddr_pxi5),\n+\tMSM_PIN_FUNCTION(ddr_pxi6),\n+\tMSM_PIN_FUNCTION(ddr_pxi7),\n+\tMSM_PIN_FUNCTION(ddr_pxi8),\n+\tMSM_PIN_FUNCTION(ddr_pxi9),\n+\tMSM_PIN_FUNCTION(dp_rx0),\n+\tMSM_PIN_FUNCTION(dp_rx00),\n+\tMSM_PIN_FUNCTION(dp_rx01),\n+\tMSM_PIN_FUNCTION(dp_rx0_mute),\n+\tMSM_PIN_FUNCTION(dp_rx1),\n+\tMSM_PIN_FUNCTION(dp_rx10),\n+\tMSM_PIN_FUNCTION(dp_rx11),\n+\tMSM_PIN_FUNCTION(dp_rx1_mute),\n+\tMSM_PIN_FUNCTION(edp0_hot),\n+\tMSM_PIN_FUNCTION(edp0_lcd),\n+\tMSM_PIN_FUNCTION(edp1_hot),\n+\tMSM_PIN_FUNCTION(edp1_lcd),\n+\tMSM_PIN_FUNCTION(edp2_hot),\n+\tMSM_PIN_FUNCTION(edp2_lcd),\n+\tMSM_PIN_FUNCTION(edp3_hot),\n+\tMSM_PIN_FUNCTION(edp3_lcd),\n+\tMSM_PIN_FUNCTION(emac0_mcg0),\n+\tMSM_PIN_FUNCTION(emac0_mcg1),\n+\tMSM_PIN_FUNCTION(emac0_mcg2),\n+\tMSM_PIN_FUNCTION(emac0_mcg3),\n+\tMSM_PIN_FUNCTION(emac0_mdc),\n+\tMSM_PIN_FUNCTION(emac0_mdio),\n+\tMSM_PIN_FUNCTION(emac0_ptp),\n+\tMSM_PIN_FUNCTION(emac1_mcg0),\n+\tMSM_PIN_FUNCTION(emac1_mcg1),\n+\tMSM_PIN_FUNCTION(emac1_mcg2),\n+\tMSM_PIN_FUNCTION(emac1_mcg3),\n+\tMSM_PIN_FUNCTION(emac1_mdc),\n+\tMSM_PIN_FUNCTION(emac1_mdio),\n+\tMSM_PIN_FUNCTION(emac1_ptp),\n+\tMSM_PIN_FUNCTION(gcc_gp1_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp2_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp3_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp4_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp5_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp6_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp7_clk),\n+\tMSM_PIN_FUNCTION(gcc_gp8_clk),\n+\tMSM_PIN_FUNCTION(jitter_bist),\n+\tMSM_PIN_FUNCTION(lbist_pass),\n+\tMSM_PIN_FUNCTION(mbist_pass),\n+\tMSM_PIN_FUNCTION(mdp0_vsync0_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync10_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync1_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync2_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync3_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync4_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync5_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync6_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync7_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync8_out),\n+\tMSM_PIN_FUNCTION(mdp0_vsync9_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync0_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync10_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync1_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync2_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync3_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync4_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync5_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync6_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync7_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync8_out),\n+\tMSM_PIN_FUNCTION(mdp1_vsync9_out),\n+\tMSM_PIN_FUNCTION(mdp_vsync_e),\n+\tMSM_PIN_FUNCTION(mdp_vsync_p),\n+\tMSM_PIN_FUNCTION(mdp_vsync_s),\n+\tMSM_PIN_FUNCTION(pcie0_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie1_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie2_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie3_clk_req_n),\n+\tMSM_PIN_FUNCTION(phase_flag0),\n+\tMSM_PIN_FUNCTION(phase_flag1),\n+\tMSM_PIN_FUNCTION(phase_flag10),\n+\tMSM_PIN_FUNCTION(phase_flag11),\n+\tMSM_PIN_FUNCTION(phase_flag12),\n+\tMSM_PIN_FUNCTION(phase_flag13),\n+\tMSM_PIN_FUNCTION(phase_flag14),\n+\tMSM_PIN_FUNCTION(phase_flag15),\n+\tMSM_PIN_FUNCTION(phase_flag16),\n+\tMSM_PIN_FUNCTION(phase_flag17),\n+\tMSM_PIN_FUNCTION(phase_flag18),\n+\tMSM_PIN_FUNCTION(phase_flag19),\n+\tMSM_PIN_FUNCTION(phase_flag2),\n+\tMSM_PIN_FUNCTION(phase_flag20),\n+\tMSM_PIN_FUNCTION(phase_flag21),\n+\tMSM_PIN_FUNCTION(phase_flag22),\n+\tMSM_PIN_FUNCTION(phase_flag23),\n+\tMSM_PIN_FUNCTION(phase_flag24),\n+\tMSM_PIN_FUNCTION(phase_flag25),\n+\tMSM_PIN_FUNCTION(phase_flag26),\n+\tMSM_PIN_FUNCTION(phase_flag27),\n+\tMSM_PIN_FUNCTION(phase_flag28),\n+\tMSM_PIN_FUNCTION(phase_flag29),\n+\tMSM_PIN_FUNCTION(phase_flag3),\n+\tMSM_PIN_FUNCTION(phase_flag30),\n+\tMSM_PIN_FUNCTION(phase_flag31),\n+\tMSM_PIN_FUNCTION(phase_flag4),\n+\tMSM_PIN_FUNCTION(phase_flag5),\n+\tMSM_PIN_FUNCTION(phase_flag6),\n+\tMSM_PIN_FUNCTION(phase_flag7),\n+\tMSM_PIN_FUNCTION(phase_flag8),\n+\tMSM_PIN_FUNCTION(phase_flag9),\n+\tMSM_PIN_FUNCTION(pll_bist_sync),\n+\tMSM_PIN_FUNCTION(pll_clk_aux),\n+\tMSM_PIN_FUNCTION(prng_rosc0),\n+\tMSM_PIN_FUNCTION(prng_rosc1),\n+\tMSM_PIN_FUNCTION(pwrbrk_i_n),\n+\tMSM_PIN_FUNCTION(qdss_cti),\n+\tMSM_PIN_FUNCTION(qdss_gpio),\n+\tMSM_PIN_FUNCTION(qdss_gpio0),\n+\tMSM_PIN_FUNCTION(qdss_gpio1),\n+\tMSM_PIN_FUNCTION(qdss_gpio10),\n+\tMSM_PIN_FUNCTION(qdss_gpio11),\n+\tMSM_PIN_FUNCTION(qdss_gpio12),\n+\tMSM_PIN_FUNCTION(qdss_gpio13),\n+\tMSM_PIN_FUNCTION(qdss_gpio14),\n+\tMSM_PIN_FUNCTION(qdss_gpio15),\n+\tMSM_PIN_FUNCTION(qdss_gpio2),\n+\tMSM_PIN_FUNCTION(qdss_gpio3),\n+\tMSM_PIN_FUNCTION(qdss_gpio4),\n+\tMSM_PIN_FUNCTION(qdss_gpio5),\n+\tMSM_PIN_FUNCTION(qdss_gpio6),\n+\tMSM_PIN_FUNCTION(qdss_gpio7),\n+\tMSM_PIN_FUNCTION(qdss_gpio8),\n+\tMSM_PIN_FUNCTION(qdss_gpio9),\n+\tMSM_PIN_FUNCTION(qspi0),\n+\tMSM_PIN_FUNCTION(qspi1),\n+\tMSM_PIN_FUNCTION(qspi2),\n+\tMSM_PIN_FUNCTION(qspi3),\n+\tMSM_PIN_FUNCTION(qspi_clk),\n+\tMSM_PIN_FUNCTION(qspi_cs0_n),\n+\tMSM_PIN_FUNCTION(qspi_cs1_n),\n+\tMSM_PIN_FUNCTION(qup0_se0_l0),\n+\tMSM_PIN_FUNCTION(qup0_se0_l1),\n+\tMSM_PIN_FUNCTION(qup0_se0_l2),\n+\tMSM_PIN_FUNCTION(qup0_se0_l3),\n+\tMSM_PIN_FUNCTION(qup0_se1_l0),\n+\tMSM_PIN_FUNCTION(qup0_se1_l1),\n+\tMSM_PIN_FUNCTION(qup0_se1_l2),\n+\tMSM_PIN_FUNCTION(qup0_se1_l3),\n+\tMSM_PIN_FUNCTION(qup0_se2_l0),\n+\tMSM_PIN_FUNCTION(qup0_se2_l1),\n+\tMSM_PIN_FUNCTION(qup0_se2_l2),\n+\tMSM_PIN_FUNCTION(qup0_se2_l3),\n+\tMSM_PIN_FUNCTION(qup0_se3_l0),\n+\tMSM_PIN_FUNCTION(qup0_se3_l1),\n+\tMSM_PIN_FUNCTION(qup0_se3_l2),\n+\tMSM_PIN_FUNCTION(qup0_se3_l3),\n+\tMSM_PIN_FUNCTION(qup0_se4_l0),\n+\tMSM_PIN_FUNCTION(qup0_se4_l1),\n+\tMSM_PIN_FUNCTION(qup0_se4_l2),\n+\tMSM_PIN_FUNCTION(qup0_se4_l3),\n+\tMSM_PIN_FUNCTION(qup0_se5_l0),\n+\tMSM_PIN_FUNCTION(qup0_se5_l1),\n+\tMSM_PIN_FUNCTION(qup0_se5_l2),\n+\tMSM_PIN_FUNCTION(qup0_se5_l3),\n+\tMSM_PIN_FUNCTION(qup1_se0_l0),\n+\tMSM_PIN_FUNCTION(qup1_se0_l1),\n+\tMSM_PIN_FUNCTION(qup1_se0_l2),\n+\tMSM_PIN_FUNCTION(qup1_se0_l3),\n+\tMSM_PIN_FUNCTION(qup1_se1_l0),\n+\tMSM_PIN_FUNCTION(qup1_se1_l1),\n+\tMSM_PIN_FUNCTION(qup1_se1_l2),\n+\tMSM_PIN_FUNCTION(qup1_se1_l3),\n+\tMSM_PIN_FUNCTION(qup1_se2_l0),\n+\tMSM_PIN_FUNCTION(qup1_se2_l1),\n+\tMSM_PIN_FUNCTION(qup1_se2_l2),\n+\tMSM_PIN_FUNCTION(qup1_se2_l3),\n+\tMSM_PIN_FUNCTION(qup1_se3_l0),\n+\tMSM_PIN_FUNCTION(qup1_se3_l1),\n+\tMSM_PIN_FUNCTION(qup1_se3_l2),\n+\tMSM_PIN_FUNCTION(qup1_se3_l3),\n+\tMSM_PIN_FUNCTION(qup1_se4_l0),\n+\tMSM_PIN_FUNCTION(qup1_se4_l1),\n+\tMSM_PIN_FUNCTION(qup1_se4_l2),\n+\tMSM_PIN_FUNCTION(qup1_se4_l3),\n+\tMSM_PIN_FUNCTION(qup1_se5_l0),\n+\tMSM_PIN_FUNCTION(qup1_se5_l1),\n+\tMSM_PIN_FUNCTION(qup1_se5_l2),\n+\tMSM_PIN_FUNCTION(qup1_se5_l3),\n+\tMSM_PIN_FUNCTION(qup1_se6_l0),\n+\tMSM_PIN_FUNCTION(qup1_se6_l1),\n+\tMSM_PIN_FUNCTION(qup1_se6_l2),\n+\tMSM_PIN_FUNCTION(qup1_se6_l3),\n+\tMSM_PIN_FUNCTION(qup2_se0_l0),\n+\tMSM_PIN_FUNCTION(qup2_se0_l1),\n+\tMSM_PIN_FUNCTION(qup2_se0_l2),\n+\tMSM_PIN_FUNCTION(qup2_se0_l3),\n+\tMSM_PIN_FUNCTION(qup2_se1_l0),\n+\tMSM_PIN_FUNCTION(qup2_se1_l1),\n+\tMSM_PIN_FUNCTION(qup2_se1_l2),\n+\tMSM_PIN_FUNCTION(qup2_se1_l3),\n+\tMSM_PIN_FUNCTION(qup2_se2_l0),\n+\tMSM_PIN_FUNCTION(qup2_se2_l1),\n+\tMSM_PIN_FUNCTION(qup2_se2_l2),\n+\tMSM_PIN_FUNCTION(qup2_se2_l3),\n+\tMSM_PIN_FUNCTION(qup2_se2_l4),\n+\tMSM_PIN_FUNCTION(qup2_se3_l0),\n+\tMSM_PIN_FUNCTION(qup2_se3_l1),\n+\tMSM_PIN_FUNCTION(qup2_se3_l2),\n+\tMSM_PIN_FUNCTION(qup2_se3_l3),\n+\tMSM_PIN_FUNCTION(qup2_se4_l0),\n+\tMSM_PIN_FUNCTION(qup2_se4_l1),\n+\tMSM_PIN_FUNCTION(qup2_se4_l2),\n+\tMSM_PIN_FUNCTION(qup2_se4_l3),\n+\tMSM_PIN_FUNCTION(qup2_se4_l4),\n+\tMSM_PIN_FUNCTION(qup2_se4_l5),\n+\tMSM_PIN_FUNCTION(qup2_se4_l6),\n+\tMSM_PIN_FUNCTION(qup2_se5_l0),\n+\tMSM_PIN_FUNCTION(qup2_se5_l1),\n+\tMSM_PIN_FUNCTION(qup2_se5_l2),\n+\tMSM_PIN_FUNCTION(qup2_se5_l3),\n+\tMSM_PIN_FUNCTION(qup2_se6_l0),\n+\tMSM_PIN_FUNCTION(qup2_se6_l1),\n+\tMSM_PIN_FUNCTION(qup2_se6_l2),\n+\tMSM_PIN_FUNCTION(qup2_se6_l3),\n+\tMSM_PIN_FUNCTION(qup3_se0_l0_mira),\n+\tMSM_PIN_FUNCTION(qup3_se0_l0_mirb),\n+\tMSM_PIN_FUNCTION(qup3_se0_l1_mira),\n+\tMSM_PIN_FUNCTION(qup3_se0_l1_mirb),\n+\tMSM_PIN_FUNCTION(qup3_se0_l2),\n+\tMSM_PIN_FUNCTION(qup3_se0_l3),\n+\tMSM_PIN_FUNCTION(qup3_se0_l4),\n+\tMSM_PIN_FUNCTION(qup3_se0_l5),\n+\tMSM_PIN_FUNCTION(qup3_se0_l6),\n+\tMSM_PIN_FUNCTION(sailss_ospi),\n+\tMSM_PIN_FUNCTION(sdc4_clk),\n+\tMSM_PIN_FUNCTION(sdc4_cmd),\n+\tMSM_PIN_FUNCTION(sdc4_data),\n+\tMSM_PIN_FUNCTION(smb_alert),\n+\tMSM_PIN_FUNCTION(smb_alert_n),\n+\tMSM_PIN_FUNCTION(smb_clk),\n+\tMSM_PIN_FUNCTION(smb_dat),\n+\tMSM_PIN_FUNCTION(tb_trig_sdc4),\n+\tMSM_PIN_FUNCTION(tmess_prng0),\n+\tMSM_PIN_FUNCTION(tmess_prng1),\n+\tMSM_PIN_FUNCTION(tsc_timer0),\n+\tMSM_PIN_FUNCTION(tsc_timer1),\n+\tMSM_PIN_FUNCTION(tsc_timer2),\n+\tMSM_PIN_FUNCTION(tsc_timer3),\n+\tMSM_PIN_FUNCTION(tsc_timer4),\n+\tMSM_PIN_FUNCTION(tsc_timer5),\n+\tMSM_PIN_FUNCTION(tsc_timer6),\n+\tMSM_PIN_FUNCTION(tsc_timer7),\n+\tMSM_PIN_FUNCTION(tsc_timer8),\n+\tMSM_PIN_FUNCTION(tsc_timer9),\n+\tMSM_PIN_FUNCTION(tsense_pwm1),\n+\tMSM_PIN_FUNCTION(tsense_pwm2),\n+\tMSM_PIN_FUNCTION(tsense_pwm3),\n+\tMSM_PIN_FUNCTION(tsense_pwm4),\n+\tMSM_PIN_FUNCTION(tsense_pwm5),\n+\tMSM_PIN_FUNCTION(tsense_pwm6),\n+\tMSM_PIN_FUNCTION(tsense_pwm7),\n+\tMSM_PIN_FUNCTION(tsense_pwm8),\n+\tMSM_PIN_FUNCTION(usb0_hs),\n+\tMSM_PIN_FUNCTION(usb0_phy_ps),\n+\tMSM_PIN_FUNCTION(usb1_hs),\n+\tMSM_PIN_FUNCTION(usb1_phy_ps),\n+\tMSM_PIN_FUNCTION(usb2_hs),\n+\tMSM_PIN_FUNCTION(usxgmii0_phy),\n+\tMSM_PIN_FUNCTION(usxgmii1_phy),\n+\tMSM_PIN_FUNCTION(vsense_trigger_mirnat),\n+\tMSM_PIN_FUNCTION(wcn_sw),\n+\tMSM_PIN_FUNCTION(wcn_sw_ctrl),\n+};\n+\n+/* Every pin is maintained as a single group, and missing or non-existing pin\n+ * would be maintained as dummy group to synchronize pin group index with\n+ * pin descriptor registered with pinctrl core.\n+ * Clients would not be able to request these dummy pin groups.\n+ */\n+static const struct msm_pingroup nord_groups[] = {\n+\t[0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _),\n+\t[1] = PINGROUP(1, pcie0_clk_req_n, _, _, _, _, _, _, _, _, _, _),\n+\t[2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _),\n+\t[3] = PINGROUP(3, _, _, _, _, _, _, _, _, _, _, _),\n+\t[4] = PINGROUP(4, pcie1_clk_req_n, _, _, _, _, _, _, _, _, _, _),\n+\t[5] = PINGROUP(5, _, _, _, _, _, _, _, _, _, _, _),\n+\t[6] = PINGROUP(6, _, _, _, _, _, _, _, _, _, _, _),\n+\t[7] = PINGROUP(7, pcie2_clk_req_n, _, _, _, _, _, _, _, _, _, _),\n+\t[8] = PINGROUP(8, _, _, _, _, _, _, _, _, _, _, _),\n+\t[9] = PINGROUP(9, _, _, _, _, _, _, _, _, _, _, _),\n+\t[10] = PINGROUP(10, pcie3_clk_req_n, _, _, _, _, _, _, _, _, _, _),\n+\t[11] = PINGROUP(11, _, _, _, _, _, _, _, _, _, _, _),\n+\t[12] = PINGROUP(12, usb0_hs, clink_debug, _, _, _, _, _, _, _, _, _),\n+\t[13] = PINGROUP(13, usb1_hs, clink_debug, gcc_gp7_clk, _, _, _, _, _, _, _, _),\n+\t[14] = PINGROUP(14, usb2_hs, clink_debug, gcc_gp8_clk, _, _, _, _, _, _, _, _),\n+\t[15] = PINGROUP(15, ccu_i2c_sda0, _, _, _, _, _, _, _, _, _, _),\n+\t[16] = PINGROUP(16, ccu_i2c_scl0, emac0_mcg0, _, _, _, _, _, _, _, _, _),\n+\t[17] = PINGROUP(17, ccu_i2c_sda1, emac0_mcg1, _, _, _, _, _, _, _, _, _),\n+\t[18] = PINGROUP(18, ccu_i2c_scl1, emac0_mcg2, _, _, _, _, _, _, _, _, _),\n+\t[19] = PINGROUP(19, ccu_i2c_sda2, emac0_mcg3, _, _, _, _, _, _, _, _, _),\n+\t[20] = PINGROUP(20, ccu_i2c_scl2, emac1_mcg0, _, _, _, _, _, _, _, _, _),\n+\t[21] = PINGROUP(21, ccu_i2c_sda3, emac1_mcg1, _, _, _, _, _, _, _, _, _),\n+\t[22] = PINGROUP(22, ccu_i2c_scl3, emac1_mcg2, _, _, _, _, _, _, _, _, _),\n+\t[23] = PINGROUP(23, ccu_i2c_sda4, emac1_mcg3, _, _, _, _, _, _, _, _, _),\n+\t[24] = PINGROUP(24, ccu_i2c_scl4, _, _, _, _, _, _, _, _, _, _),\n+\t[25] = PINGROUP(25, ccu_timer0, tsc_timer0, _, _, _, _, _, _, _, _, _),\n+\t[26] = PINGROUP(26, ccu_timer1, tsc_timer1, _, _, _, _, _, _, _, _, _),\n+\t[27] = PINGROUP(27, ccu_timer2, tsc_timer2, _, _, _, _, _, _, _, _, _),\n+\t[28] = PINGROUP(28, ccu_timer3, tsc_timer3, _, _, _, _, _, _, _, _, _),\n+\t[29] = PINGROUP(29, ccu_timer4, tsc_timer4, _, _, _, _, _, _, _, _, _),\n+\t[30] = PINGROUP(30, ccu_timer5, tsc_timer5, _, _, _, _, _, _, _, _, _),\n+\t[31] = PINGROUP(31, ccu_timer6, tsc_timer6, _, _, _, _, _, _, _, _, _),\n+\t[32] = PINGROUP(32, ccu_timer7, tsc_timer7, _, _, _, _, _, _, _, _, _),\n+\t[33] = PINGROUP(33, ccu_timer8, tsc_timer8, _, _, _, _, _, _, _, _, _),\n+\t[34] = PINGROUP(34, ccu_timer9, tsc_timer9, _, _, _, _, _, _, _, _, _),\n+\t[35] = PINGROUP(35, dp_rx0_mute, _, _, _, _, _, _, _, _, _, _),\n+\t[36] = PINGROUP(36, dp_rx1_mute, ddr_bist_start, _, _, _, _, _, _, _, _, _),\n+\t[37] = PINGROUP(37, emac1_ptp, ddr_bist_complete, _, _, _, _, _, _, _, _, _),\n+\t[38] = PINGROUP(38, emac1_ptp, ddr_bist_stop, _, _, _, _, _, _, _, _, _),\n+\t[39] = PINGROUP(39, emac1_ptp, ddr_bist_fail, _, _, _, _, _, _, _, _, _),\n+\t[40] = PINGROUP(40, emac1_ptp, _, _, _, _, _, _, _, _, _, _),\n+\t[41] = PINGROUP(41, emac1_ptp, qdss_cti, _, _, _, _, _, _, _, _, _),\n+\t[42] = PINGROUP(42, emac1_ptp, qdss_cti, gcc_gp3_clk, _, _, _, _, _, _, _, _),\n+\t[43] = PINGROUP(43, emac1_ptp, gcc_gp4_clk, tsense_pwm1, _, _, _, _, _, _, _, _),\n+\t[44] = PINGROUP(44, emac1_ptp, tsense_pwm2, _, _, _, _, _, _, _, _, _),\n+\t[45] = PINGROUP(45, usxgmii0_phy, ccu_async_in5, tsense_pwm3, _, _, _, _, _, _, _, _),\n+\t[46] = PINGROUP(46, usxgmii1_phy, tsense_pwm4, _, _, _, _, _, _, _, _, _),\n+\t[47] = PINGROUP(47, emac0_mdc, edp0_lcd, tsense_pwm5, _, _, _, _, _, _, _, _),\n+\t[48] = PINGROUP(48, emac0_mdio, edp1_lcd, tsense_pwm6, _, _, _, _, _, _, _, _),\n+\t[49] = PINGROUP(49, emac1_mdc, edp2_lcd, tsense_pwm7, _, _, _, _, _, _, _, _),\n+\t[50] = PINGROUP(50, emac1_mdio, edp3_lcd, tsense_pwm8, _, _, _, _, _, _, _, _),\n+\t[51] = PINGROUP(51, edp0_hot, clink_debug, gcc_gp1_clk, _, _, _, _, _, _, _, _),\n+\t[52] = PINGROUP(52, edp1_hot, clink_debug, gcc_gp2_clk, _, _, _, _, _, _, _, _),\n+\t[53] = PINGROUP(53, edp2_hot, clink_debug, _, _, _, _, _, _, _, _, _),\n+\t[54] = PINGROUP(54, edp3_hot, clink_debug, _, _, _, _, _, _, _, _, _),\n+\t[55] = PINGROUP(55, dp_rx0, clink_debug, _, _, _, _, _, _, _, _, _),\n+\t[56] = PINGROUP(56, dp_rx1, _, _, _, _, _, _, _, _, _, _),\n+\t[57] = PINGROUP(57, aud_intfc0_clk, _, _, _, _, _, _, _, _, _, _),\n+\t[58] = PINGROUP(58, aud_intfc0_ws, _, _, _, _, _, _, _, _, _, _),\n+\t[59] = PINGROUP(59, aud_intfc0_data0, _, _, _, _, _, _, _, _, _, _),\n+\t[60] = PINGROUP(60, aud_intfc0_data1, _, _, _, _, _, _, _, _, _, _),\n+\t[61] = PINGROUP(61, aud_intfc0_data2, aud_intfc10_clk, _, _, _, _, _, _, _, _, _),\n+\t[62] = PINGROUP(62, aud_intfc0_data3, aud_intfc10_ws, _, _, _, _, _, _, _, _, _),\n+\t[63] = PINGROUP(63, aud_intfc0_data4, aud_intfc7_clk, _, _, _, _, _, _, _, _, _),\n+\t[64] = PINGROUP(64, aud_intfc0_data5, aud_intfc7_ws, _, _, _, _, _, _, _, _, _),\n+\t[65] = PINGROUP(65, aud_intfc0_data6, aud_intfc7_data0, _, _, _, _, _, _, _, _, _),\n+\t[66] = PINGROUP(66, aud_intfc0_data7, aud_intfc7_data1, _, _, _, _, _, _, _, _, _),\n+\t[67] = PINGROUP(67, aud_intfc1_clk, phase_flag18, _, qdss_gpio0, _, _, _, _, _, _, _),\n+\t[68] = PINGROUP(68, aud_intfc1_ws, phase_flag19, _, qdss_gpio1, _, _, _, _, _, _, _),\n+\t[69] = PINGROUP(69, aud_intfc1_data0, phase_flag20, _, qdss_gpio2, _, _, _, _, _, _, _),\n+\t[70] = PINGROUP(70, aud_intfc1_data1, aud_intfc9_clk, phase_flag21, _, qdss_gpio3,\n+\t\t\t_, _, _, _, _, _),\n+\t[71] = PINGROUP(71, aud_intfc1_data2, aud_intfc9_ws, phase_flag22, _, qdss_gpio4, _, _,\n+\t\t\t_, _, _, _),\n+\t[72] = PINGROUP(72, aud_intfc1_data3, aud_intfc9_data0, phase_flag23, _, qdss_gpio5, _,\n+\t\t\t_, _, _, _, _),\n+\t[73] = PINGROUP(73, aud_intfc1_data4, aud_intfc8_clk, phase_flag24, _, qdss_gpio6, _,\n+\t\t\t_, _, _, _, _),\n+\t[74] = PINGROUP(74, aud_intfc1_data5, aud_intfc8_ws, phase_flag25, _, qdss_gpio7, _,\n+\t\t\t_, _, _, _, _),\n+\t[75] = PINGROUP(75, aud_intfc1_data6, aud_intfc8_data0, phase_flag26, _, qdss_gpio,\n+\t\t\t_, _, _, _, _, _),\n+\t[76] = PINGROUP(76, aud_intfc1_data7, aud_intfc8_data1, phase_flag27, _, qdss_gpio,\n+\t\t\t_, _, _, _, _, _),\n+\t[77] = PINGROUP(77, aud_intfc2_clk, phase_flag6, _, qdss_gpio8, _, _, _, _, _, _, _),\n+\t[78] = PINGROUP(78, aud_intfc2_ws, phase_flag5, _, qdss_gpio9, _, _, _, _, _, _, _),\n+\t[79] = PINGROUP(79, aud_intfc2_data0, phase_flag4, _, qdss_gpio10, _, _, _, _, _, _, _),\n+\t[80] = PINGROUP(80, aud_intfc2_data1, phase_flag3, _, _, qdss_gpio11, _, _, _, _, _, _),\n+\t[81] = PINGROUP(81, aud_intfc2_data2, aud_intfc10_data0, phase_flag2, _, _, qdss_gpio12,\n+\t\t\t_, _, _, _, _),\n+\t[82] = PINGROUP(82, aud_intfc2_data3, aud_intfc10_data1, phase_flag1, _, qdss_gpio13,\n+\t\t\t_, _, _, _, _, _),\n+\t[83] = PINGROUP(83, aud_intfc3_clk, dp_rx0, aoss_cti, phase_flag28, _, qdss_gpio14,\n+\t\t\t_, _, _, _, _),\n+\t[84] = PINGROUP(84, aud_intfc3_ws, dp_rx0, aoss_cti, phase_flag29, _, qdss_gpio15,\n+\t\t\t_, _, _, _, _),\n+\t[85] = PINGROUP(85, aud_intfc3_data0, dp_rx0, aoss_cti, phase_flag30, _, qdss_gpio0,\n+\t\t\t_, _, _, _, _),\n+\t[86] = PINGROUP(86, aud_intfc3_data1, aud_mclk0_mirb, dp_rx0, aoss_cti, phase_flag31,\n+\t\t\t_, qdss_gpio1, _, _, _, _),\n+\t[87] = PINGROUP(87, aud_intfc4_clk, phase_flag7, _, qdss_gpio2, _, _, _, _, _, _, _),\n+\t[88] = PINGROUP(88, aud_intfc4_ws, dp_rx0, phase_flag8, _, qdss_gpio3, _, _, _, _, _, _),\n+\t[89] = PINGROUP(89, aud_intfc4_data0, dp_rx0, phase_flag9, _, qdss_gpio4,\n+\t\t\t_, _, _, _, _, _),\n+\t[90] = PINGROUP(90, aud_intfc4_data1, aud_mclk1_mirb, phase_flag10, _, qdss_gpio5,\n+\t\t\t_, _, _, _, _, _),\n+\t[91] = PINGROUP(91, aud_intfc5_clk, phase_flag11, _, qdss_gpio6, _, _, _, _, _, _, _),\n+\t[92] = PINGROUP(92, aud_intfc5_ws, dp_rx1, phase_flag12, _, qdss_gpio7, _, _, _, _, _, _),\n+\t[93] = PINGROUP(93, aud_intfc5_data0, dp_rx1, phase_flag13, _, qdss_gpio,\n+\t\t\t_, _, _, _, _, _),\n+\t[94] = PINGROUP(94, aud_intfc5_data1, aud_mclk2_mirb, phase_flag14, tmess_prng0, _,\n+\t\t\tqdss_gpio8, _, _, _, _, _),\n+\t[95] = PINGROUP(95, aud_intfc6_clk, dp_rx1, phase_flag15, tmess_prng1, _, qdss_gpio9,\n+\t\t\t_, _, _, _, _),\n+\t[96] = PINGROUP(96, aud_intfc6_ws, dp_rx1, phase_flag16, _, qdss_gpio10, _, _, _, _, _, _),\n+\t[97] = PINGROUP(97, aud_intfc6_data0, dp_rx1, qdss_gpio11, _, _, _, _, _, _, _, _),\n+\t[98] = PINGROUP(98, aud_intfc6_data1, dp_rx1, phase_flag0, _, qdss_gpio12,\n+\t\t\t_, _, _, _, _, _),\n+\t[99] = PINGROUP(99, aud_mclk0_mira, qdss_gpio13, dp_rx00, ddr_pxi0, _, _, _, _, _, _, _),\n+\t[100] = PINGROUP(100, aud_mclk1_mira, aud_refclk0, pll_clk_aux, qdss_gpio14, dp_rx01,\n+\t\t\t ddr_pxi0, _, _, _, _, _),\n+\t[101] = PINGROUP(101, aud_mclk2_mira, aud_refclk1, phase_flag17, _, qdss_gpio15,\n+\t\t\t _, _, _, _, _, _),\n+\t[102] = PINGROUP(102, qspi0, qup3_se0_l0_mira, qup3_se0_l1_mirb, _, _, _, _, _, _, _, _),\n+\t[103] = PINGROUP(103, qspi1, qup3_se0_l1_mira, qup3_se0_l0_mirb, _, _, _, _, _, _, _, _),\n+\t[104] = PINGROUP(104, qspi_clk, qup3_se0_l2, _, _, _, _, _, _, _, _, _),\n+\t[105] = PINGROUP(105, qspi_cs0_n, qup3_se0_l3, gcc_gp5_clk, _, _, _, _, _, _, _, _),\n+\t[106] = PINGROUP(106, qspi2, qup3_se0_l4, gcc_gp6_clk, _, _, _, _, _, _, _, _),\n+\t[107] = PINGROUP(107, qspi3, qup3_se0_l5, _, _, _, _, _, _, _, _, _),\n+\t[108] = PINGROUP(108, qspi_cs1_n, qup3_se0_l6, qdss_gpio, _, _, _, _, _, _, _, _),\n+\t[109] = PINGROUP(109, qup0_se0_l2, qup0_se1_l2, qup0_se5_l2, mdp_vsync_e, smb_alert_n,\n+\t\t\t _, ddr_pxi1, _, _, _, _),\n+\t[110] = PINGROUP(110, qup0_se0_l3, qup0_se1_l3, qup0_se5_l3, qdss_cti, mdp_vsync_p,\n+\t\t\t smb_alert, _, ddr_pxi1, _, _, _),\n+\t[111] = PINGROUP(111, qup0_se1_l0, qup0_se0_l0, smb_dat, _, _, _, _, _, _, _, _),\n+\t[112] = PINGROUP(112, qup0_se1_l1, qup0_se0_l1, smb_clk, _, _, _, _, _, _, _, _),\n+\t[113] = PINGROUP(113, qup0_se2_l0, qup0_se3_l2, ccu_i2c_sda5, mdp0_vsync0_out,\n+\t\t\t dbg_out, ddr_pxi2, _, _, _, _, _),\n+\t[114] = PINGROUP(114, qup0_se2_l1, qup0_se3_l3, ccu_i2c_scl5, mdp0_vsync1_out,\n+\t\t\t _, ddr_pxi2, _, _, _, _, _),\n+\t[115] = PINGROUP(115, qup0_se3_l0, qup0_se2_l2, ccu_i2c_sda6, mdp0_vsync2_out,\n+\t\t\t _, ddr_pxi3, _, _, _, _, _),\n+\t[116] = PINGROUP(116, qup0_se3_l1, qup0_se2_l3, ccu_i2c_scl6, mdp0_vsync3_out, _,\n+\t\t\t ddr_pxi3, _, _, _, _, _),\n+\t[117] = PINGROUP(117, qup0_se4_l0, prng_rosc0, _, ddr_pxi4, _, _, _, _, _, _, _),\n+\t[118] = PINGROUP(118, qup0_se4_l1, prng_rosc1, _, ddr_pxi4, _, _, _, _, _, _, _),\n+\t[119] = PINGROUP(119, qup0_se4_l2, _, ddr_pxi6, _, _, _, _, _, _, _, _),\n+\t[120] = PINGROUP(120, qup0_se4_l3, _, ddr_pxi6, _, _, _, _, _, _, _, _),\n+\t[121] = PINGROUP(121, qup0_se5_l0, lbist_pass, mdp0_vsync4_out, _, dp_rx10, ddr_pxi7,\n+\t\t\t _, _, _, _, _),\n+\t[122] = PINGROUP(122, qup0_se5_l1, mbist_pass, mdp0_vsync5_out, _, dp_rx11, ddr_pxi7,\n+\t\t\t _, _, _, _, _),\n+\t[123] = PINGROUP(123, qup1_se0_l0, qup1_se1_l2, mdp1_vsync0_out, jitter_bist,\n+\t\t\t _, _, _, _, _, _, _),\n+\t[124] = PINGROUP(124, qup1_se0_l1, qup1_se1_l3, mdp1_vsync1_out, _, _, _, _, _, _, _, _),\n+\t[125] = PINGROUP(125, qup1_se1_l0, qup1_se0_l2, ccu_i2c_sda7, mdp1_vsync2_out,\n+\t\t\t _, _, _, _, _, _, _),\n+\t[126] = PINGROUP(126, qup1_se1_l1, qup1_se0_l3, ccu_i2c_scl7, mdp1_vsync3_out, _,\n+\t\t\t atest_usb20, ddr_pxi8, _, _, _, _),\n+\t[127] = PINGROUP(127, qup1_se2_l2, qup1_se2_l0, _, atest_usb21, ddr_pxi8,\n+\t\t\t _, _, _, _, _, _),\n+\t[128] = PINGROUP(128, qup1_se2_l3, qup1_se2_l1, _, atest_usb20, ddr_pxi9,\n+\t\t\t _, _, _, _, _, _),\n+\t[129] = PINGROUP(129, qup1_se3_l2, qup1_se3_l0, ccu_i2c_sda8, mdp1_vsync4_out, _,\n+\t\t\t atest_usb21, ddr_pxi9, _, _, _, _),\n+\t[130] = PINGROUP(130, qup1_se3_l3, qup1_se3_l1, ccu_i2c_scl8, mdp1_vsync5_out, _,\n+\t\t\t atest_usb20, ddr_pxi10, _, _, _, _),\n+\t[131] = PINGROUP(131, qup1_se4_l0, qup1_se6_l2, ccu_i2c_sda9, mdp1_vsync6_out, _,\n+\t\t\t atest_usb21, ddr_pxi10, _, _, _, _),\n+\t[132] = PINGROUP(132, qup1_se4_l1, qup1_se6_l3, ccu_i2c_scl9, mdp1_vsync7_out, _,\n+\t\t\t vsense_trigger_mirnat, ddr_pxi11, _, _, _, _),\n+\t[133] = PINGROUP(133, qup1_se5_l0, emac0_ptp, mdp1_vsync8_out, _, ddr_pxi11,\n+\t\t\t _, _, _, _, _, _),\n+\t[134] = PINGROUP(134, qup1_se5_l1, emac0_ptp, mdp1_vsync9_out, _, ddr_pxi12,\n+\t\t\t _, _, _, _, _, _),\n+\t[135] = PINGROUP(135, qup1_se5_l2, emac0_ptp, mdp1_vsync10_out, _, ddr_pxi12,\n+\t\t\t _, _, _, _, _, _),\n+\t[136] = PINGROUP(136, qup1_se5_l3, emac0_ptp, _, ddr_pxi13, _, _, _, _, _, _, _),\n+\t[137] = PINGROUP(137, qup1_se6_l0, qup1_se4_l2, dp_rx0, _, ddr_pxi13, _, _, _, _, _, _),\n+\t[138] = PINGROUP(138, qup1_se6_l1, qup1_se4_l3, dp_rx0, qdss_cti, jitter_bist,\n+\t\t\t ddr_pxi14, _, _, _, _, _),\n+\t[139] = PINGROUP(139, qup2_se0_l0, emac0_ptp, mdp0_vsync6_out, ddr_pxi14,\n+\t\t\t _, _, _, _, _, _, _),\n+\t[140] = PINGROUP(140, qup2_se0_l1, emac0_ptp, mdp0_vsync7_out, _, _, _, _, _, _, _, _),\n+\t[141] = PINGROUP(141, qup2_se0_l2, emac0_ptp, mdp0_vsync8_out, _, _, _, _, _, _, _, _),\n+\t[142] = PINGROUP(142, qup2_se0_l3, emac0_ptp, qdss_cti, mdp0_vsync9_out,\n+\t\t\t _, _, _, _, _, _, _),\n+\t[143] = PINGROUP(143, qup2_se1_l2, qup2_se4_l2, ccu_timer10, mdp0_vsync10_out,\n+\t\t\t _, _, _, _, _, _, _),\n+\t[144] = PINGROUP(144, qup2_se1_l3, qup2_se4_l3, ccu_timer11, qdss_cti, mdp_vsync_s,\n+\t\t\t _, _, _, _, _, _),\n+\t[145] = PINGROUP(145, qup2_se2_l0, _, _, _, _, _, _, _, _, _, _),\n+\t[146] = PINGROUP(146, qup2_se2_l1, _, _, _, _, _, _, _, _, _, _),\n+\t[147] = PINGROUP(147, qup2_se2_l2, _, _, _, _, _, _, _, _, _, _),\n+\t[148] = PINGROUP(148, qup2_se2_l3, _, _, _, _, _, _, _, _, _, _),\n+\t[149] = PINGROUP(149, qup2_se2_l4, _, _, _, _, _, _, _, _, _, _),\n+\t[150] = PINGROUP(150, qup2_se3_l0, qup2_se4_l4, ccu_timer12, _, _, _, _, _, _, _, _),\n+\t[151] = PINGROUP(151, qup2_se3_l1, qup2_se4_l5, ccu_timer13, _, _, _, _, _, _, _, _),\n+\t[152] = PINGROUP(152, qup2_se3_l2, qup2_se4_l6, ccu_timer14, _, _, _, _, _, _, _, _),\n+\t[153] = PINGROUP(153, qup2_se3_l3, ccu_timer15, _, _, _, _, _, _, _, _, _),\n+\t[154] = PINGROUP(154, qup2_se4_l0, qup2_se1_l0, _, _, _, _, _, _, _, _, _),\n+\t[155] = PINGROUP(155, qup2_se4_l1, qup2_se1_l1, _, _, _, _, _, _, _, _, _),\n+\t[156] = PINGROUP(156, qup2_se5_l0, qup2_se6_l2, _, _, _, _, _, _, _, _, _),\n+\t[157] = PINGROUP(157, qup2_se5_l1, qup2_se6_l3, _, _, _, _, _, _, _, _, _),\n+\t[158] = PINGROUP(158, qup2_se6_l0, qup2_se5_l2, dp_rx1, _, _, _, _, _, _, _, _),\n+\t[159] = PINGROUP(159, qup2_se6_l1, qup2_se5_l3, dp_rx1, _, _, _, _, _, _, _, _),\n+\t[160] = PINGROUP(160, wcn_sw_ctrl, _, _, _, _, _, _, _, _, _, _),\n+\t[161] = PINGROUP(161, wcn_sw, _, _, _, _, _, _, _, _, _, _),\n+\t[162] = PINGROUP(162, qdss_cti, _, ddr_pxi15, _, _, _, _, _, _, _, _),\n+\t[163] = PINGROUP(163, qdss_cti, _, ddr_pxi15, _, _, _, _, _, _, _, _),\n+\t[164] = PINGROUP(164, usb0_phy_ps, _, sailss_ospi, ddr_pxi5, _, _, _, _, _, _, _),\n+\t[165] = PINGROUP(165, usb1_phy_ps, dbg_out_clk, sailss_ospi, ddr_pxi5,\n+\t\t\t _, _, _, _, _, _, _),\n+\t[166] = PINGROUP(166, _, _, _, _, _, _, _, _, _, _, _),\n+\t[167] = PINGROUP(167, pwrbrk_i_n, _, _, _, _, _, _, _, _, _, _),\n+\t[168] = PINGROUP(168, bist_done, _, _, _, _, _, _, _, _, _, _),\n+\t[169] = PINGROUP(169, tb_trig_sdc4, _, _, _, _, _, _, _, _, _, _),\n+\t[170] = PINGROUP(170, sdc4_data, _, _, _, _, _, _, _, _, _, _),\n+\t[171] = PINGROUP(171, sdc4_data, _, _, _, _, _, _, _, _, _, _),\n+\t[172] = PINGROUP(172, sdc4_data, _, _, _, _, _, _, _, _, _, _),\n+\t[173] = PINGROUP(173, sdc4_data, _, _, _, _, _, _, _, _, _, _),\n+\t[174] = PINGROUP(174, sdc4_cmd, _, _, _, _, _, _, _, _, _, _),\n+\t[175] = PINGROUP(175, sdc4_clk, _, _, _, _, _, _, _, _, _, _),\n+\t[176] = PINGROUP(176, ccu_async_in0, pll_bist_sync, atest_char_start,\n+\t\t\t _, _, _, _, _, _, _, _),\n+\t[177] = PINGROUP(177, ccu_async_in1, atest_char0, _, _, _, _, _, _, _, _, _),\n+\t[178] = PINGROUP(178, ccu_async_in2, atest_char1, _, _, _, _, _, _, _, _, _),\n+\t[179] = PINGROUP(179, ccu_async_in3, atest_char2, _, _, _, _, _, _, _, _, _),\n+\t[180] = PINGROUP(180, ccu_async_in4, atest_char3, _, _, _, _, _, _, _, _, _),\n+\t[181] = UFS_RESET(ufs_reset, 0xBD004),\n+};\n+\n+static const struct msm_gpio_wakeirq_map nord_pdc_map[] = {\n+\t{ 0, 67 },    { 1, 68 },    { 2, 82 },\t  { 3, 69 },\t{ 4, 70 },\n+\t{ 5, 83 },    { 6, 71 },    { 7, 72 },\t  { 8, 84 },\t{ 9, 73 },\n+\t{ 10, 119 },  { 11, 85 },   { 45, 107 },  { 46, 98 },\t{ 102, 77 },\n+\t{ 108, 78 },  { 110, 120 }, { 114, 80 },  { 116, 81 },\t{ 120, 117 },\n+\t{ 124, 108 }, { 126, 99 },  { 128, 100 }, { 132, 101 }, { 138, 87 },\n+\t{ 142, 88 },  { 144, 89 },  { 153, 90 },  { 157, 91 },\t{ 159, 118 },\n+\t{ 160, 110 }, { 161, 79 },  { 166, 109 }, { 168, 111 },\n+};\n+\n+static const struct msm_pinctrl_soc_data nord_tlmm = {\n+\t.pins = nord_pins,\n+\t.npins = ARRAY_SIZE(nord_pins),\n+\t.functions = nord_functions,\n+\t.nfunctions = ARRAY_SIZE(nord_functions),\n+\t.groups = nord_groups,\n+\t.ngroups = ARRAY_SIZE(nord_groups),\n+\t.ngpios = 182,\n+\t.wakeirq_map = nord_pdc_map,\n+\t.nwakeirq_map = ARRAY_SIZE(nord_pdc_map),\n+\t.egpio_func = 11,\n+};\n+\n+static const struct of_device_id nord_tlmm_of_match[] = {\n+\t{ .compatible = \"qcom,nord-tlmm\", .data = &nord_tlmm },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, nord_tlmm_of_match);\n+\n+static int nord_tlmm_probe(struct platform_device *pdev)\n+{\n+\tconst struct msm_pinctrl_soc_data *pinctrl_data;\n+\tstruct device *dev = &pdev->dev;\n+\n+\tpinctrl_data = device_get_match_data(dev);\n+\tif (!pinctrl_data)\n+\t\treturn -EINVAL;\n+\n+\treturn msm_pinctrl_probe(pdev, &nord_tlmm);\n+}\n+\n+static struct platform_driver nord_tlmm_driver = {\n+\t.driver = {\n+\t\t.name = \"nord-tlmm\",\n+\t\t.of_match_table = nord_tlmm_of_match,\n+\t},\n+\t.probe = nord_tlmm_probe,\n+};\n+\n+static int __init nord_tlmm_init(void)\n+{\n+\treturn platform_driver_register(&nord_tlmm_driver);\n+}\n+arch_initcall(nord_tlmm_init);\n+\n+static void __exit nord_tlmm_exit(void)\n+{\n+\tplatform_driver_unregister(&nord_tlmm_driver);\n+}\n+module_exit(nord_tlmm_exit);\n+\n+MODULE_DESCRIPTION(\"Qualcomm Technologies Inc. Nord TLMM driver\");\n+MODULE_LICENSE(\"GPL\");\n",
    "prefixes": [
        "2/3"
    ]
}