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GET /api/patches/2219561/?format=api
{ "id": 2219561, "url": "http://patchwork.ozlabs.org/api/patches/2219561/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOqehAHY1DjMoco_vDqoPSY4-o=q=Ty6Yro9uDHOy+2CBg@mail.gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<CAMe9rOqehAHY1DjMoco_vDqoPSY4-o=q=Ty6Yro9uDHOy+2CBg@mail.gmail.com>", "list_archive_url": null, "date": "2026-04-03T12:24:25", "name": "Correct x86: Call ix86_access_stack_p only for larger alignment", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2d65cf41d4c1de33a73c73f2b5d6780e4706f43d", "submitter": { "id": 4387, "url": "http://patchwork.ozlabs.org/api/people/4387/?format=api", "name": "H.J. Lu", "email": "hjl.tools@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOqehAHY1DjMoco_vDqoPSY4-o=q=Ty6Yro9uDHOy+2CBg@mail.gmail.com/mbox/", "series": [ { "id": 498623, "url": "http://patchwork.ozlabs.org/api/series/498623/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=498623", "date": "2026-04-03T12:24:25", "name": "Correct x86: Call ix86_access_stack_p only for larger alignment", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498623/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219561/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=NPsKtFxo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Fri, 03 Apr 2026\n 05:25:02 -0700 (PDT)", "MIME-Version": "1.0", "From": "\"H.J. Lu\" <hjl.tools@gmail.com>", "Date": "Fri, 3 Apr 2026 20:24:25 +0800", "X-Gm-Features": "AQROBzDi0_WPazzNSR_-tjivJfhAiDyXFeAu7yjqZOsdtDMbKc8zxZDB3KJv25g", "Message-ID": "\n <CAMe9rOqehAHY1DjMoco_vDqoPSY4-o=q=Ty6Yro9uDHOy+2CBg@mail.gmail.com>", "Subject": "[PATCH] Correct x86: Call ix86_access_stack_p only for larger\n alignment", "To": "GCC Patches <gcc-patches@gcc.gnu.org>, Richard Biener <rguenther@suse.de>,\n Uros Bizjak <ubizjak@gmail.com>, Hongtao Liu <hongtao.liu@intel.com>", "Content-Type": "multipart/mixed; boundary=\"00000000000000800e064e8d684b\"", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "commit f511bf93f947199a9f9099fee87b7052e5515fb9\nAuthor: H.J. Lu <hjl.tools@gmail.com>\nDate: Sun Mar 29 14:30:28 2026 -0700\n\n x86: Call ix86_access_stack_p only for larger alignment\n\nhas 2 issues:\n\n1. It is incorrect to use GET_MODE_ALIGNMENT as memory alignment since\nmemory alignment can be different from mode alignment as in\n\n(set (reg:OI 20 xmm0 [orig:112 s ] [112])\n (mem/c:OI (plus:DI (reg/f:DI 7 sp)\n (const_int -32 [0xffffffffffffffe0])) [3 s+0 S32 A128]))\n\nMEM_ALIGN should be used instead.\n\n2. It replaced:\n\n HARD_REG_SET hard_stack_slot_access = stack_slot_access;\n ...\n bool symbolic_const_load_p = false;\n\n if (!TEST_HARD_REG_BIT (hard_stack_slot_access, regno))\n...\n symbolic_const_load_p = true;\n ...\n\n if (!symbolic_const_load_p\n || ix86_access_stack_p...)\ncall ix86_update_stack_alignment.\n\nwith\n\n if (ix86_need_alignment_p...\n && ix86_access_stack_p...)\ncall ix86_update_stack_alignment.\n\nSince ix86_access_stack_p excludes registers on hard_stack_slot_access,\nstack alignment isn't updated for registers on hard_stack_slot_access.\nInstead, we should do\n\n if (ix86_need_alignment_p...\n && (TEST_HARD_REG_BIT (hard_stack_slot_access, regno)\n || ix86_access_stack_p...))\ncall ix86_update_stack_alignment.\n\ngcc/\n\nPR target/124759\n* config/i386/i386.cc (ix86_need_alignment_p_1): Replace\nGET_MODE_ALIGNMENT with MEM_ALIGN.\n(ix86_find_max_used_stack_alignment): Restore\nhard_stack_slot_access handling.\n\ngcc/testsuite/\n\nPR target/124759\n* gcc.target/i386/pr124759.c: New test.", "diff": "From b0ddf3f222e0109ba9c97c36cfd800c54bb435c9 Mon Sep 17 00:00:00 2001\nFrom: \"H.J. Lu\" <hjl.tools@gmail.com>\nDate: Fri, 3 Apr 2026 15:55:17 +0800\nSubject: [PATCH] Correct x86: Call ix86_access_stack_p only for larger\n alignment\n\ncommit f511bf93f947199a9f9099fee87b7052e5515fb9\nAuthor: H.J. Lu <hjl.tools@gmail.com>\nDate: Sun Mar 29 14:30:28 2026 -0700\n\n x86: Call ix86_access_stack_p only for larger alignment\n\nhas 2 issues:\n\n1. It is incorrect to use GET_MODE_ALIGNMENT as memory alignment since\nmemory alignment can be different from mode alignment as in\n\n(set (reg:OI 20 xmm0 [orig:112 s ] [112])\n (mem/c:OI (plus:DI (reg/f:DI 7 sp)\n (const_int -32 [0xffffffffffffffe0])) [3 s+0 S32 A128]))\n\nMEM_ALIGN should be used instead.\n\n2. It replaced:\n\n HARD_REG_SET hard_stack_slot_access = stack_slot_access;\n ...\n bool symbolic_const_load_p = false;\n\n if (!TEST_HARD_REG_BIT (hard_stack_slot_access, regno))\n\t...\n symbolic_const_load_p = true;\n ...\n\n if (!symbolic_const_load_p\n || ix86_access_stack_p...)\n\tcall ix86_update_stack_alignment.\n\nwith\n\n if (ix86_need_alignment_p...\n && ix86_access_stack_p...)\n\tcall ix86_update_stack_alignment.\n\nSince ix86_access_stack_p excludes registers on hard_stack_slot_access,\nstack alignment isn't updated for registers on hard_stack_slot_access.\nInstead, we should do\n\n if (ix86_need_alignment_p...\n && (TEST_HARD_REG_BIT (hard_stack_slot_access, regno)\n\t || ix86_access_stack_p...))\n\tcall ix86_update_stack_alignment.\n\ngcc/\n\n\tPR target/124759\n\t* config/i386/i386.cc (ix86_need_alignment_p_1): Replace\n\tGET_MODE_ALIGNMENT with MEM_ALIGN.\n\t(ix86_find_max_used_stack_alignment): Restore\n\thard_stack_slot_access handling.\n\ngcc/testsuite/\n\n\tPR target/124759\n\t* gcc.target/i386/pr124759.c: New test.\n\nSigned-off-by: H.J. Lu <hjl.tools@gmail.com>\n---\n gcc/config/i386/i386.cc | 17 +++++++++-----\n gcc/testsuite/gcc.target/i386/pr124759.c | 29 ++++++++++++++++++++++++\n 2 files changed, 40 insertions(+), 6 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/i386/pr124759.c\n\ndiff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc\nindex 39136ce5042..146b83f6d1e 100644\n--- a/gcc/config/i386/i386.cc\n+++ b/gcc/config/i386/i386.cc\n@@ -8789,7 +8789,7 @@ ix86_need_alignment_p_1 (rtx set, unsigned int alignment)\n rtx dest = SET_DEST (set);\n \n if (MEM_P (dest))\n- return GET_MODE_ALIGNMENT (GET_MODE (dest)) > alignment;\n+ return MEM_ALIGN (dest) > alignment;\n \n const_rtx src = SET_SRC (set);\n \n@@ -8799,7 +8799,7 @@ ix86_need_alignment_p_1 (rtx set, unsigned int alignment)\n auto op = *iter;\n \n if (MEM_P (op))\n-\treturn GET_MODE_ALIGNMENT (GET_MODE (op)) > alignment;\n+\treturn MEM_ALIGN (op) > alignment;\n }\n \n return false;\n@@ -8890,6 +8890,9 @@ ix86_find_max_used_stack_alignment (unsigned int &stack_alignment,\n bitmap_set_bit (worklist, HARD_FRAME_POINTER_REGNUM);\n }\n \n+ /* Registers on HARD_STACK_SLOT_ACCESS always access stack. */\n+ HARD_REG_SET hard_stack_slot_access = stack_slot_access;\n+\n calculate_dominance_info (CDI_DOMINATORS);\n \n unsigned int regno;\n@@ -8926,10 +8929,12 @@ ix86_find_max_used_stack_alignment (unsigned int &stack_alignment,\n \t /* Call ix86_access_stack_p only if INSN needs alignment >\n \t STACK_ALIGNMENT. */\n \t if (ix86_need_alignment_p (insn, stack_alignment)\n-\t && ix86_access_stack_p (regno, BLOCK_FOR_INSN (insn),\n-\t\t\t\t set_up_by_prologue, prologue_used,\n-\t\t\t\t reg_dominate_bbs_known,\n-\t\t\t\t reg_dominate_bbs))\n+\t && (TEST_HARD_REG_BIT (hard_stack_slot_access, regno)\n+\t\t || ix86_access_stack_p (regno, BLOCK_FOR_INSN (insn),\n+\t\t\t\t\t set_up_by_prologue,\n+\t\t\t\t\t prologue_used,\n+\t\t\t\t\t reg_dominate_bbs_known,\n+\t\t\t\t\t reg_dominate_bbs)))\n \t {\n \t /* Update stack alignment if REGNO is used for stack\n \t\t access. */\ndiff --git a/gcc/testsuite/gcc.target/i386/pr124759.c b/gcc/testsuite/gcc.target/i386/pr124759.c\nnew file mode 100644\nindex 00000000000..b5a86b7b9be\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr124759.c\n@@ -0,0 +1,29 @@\n+/* { dg-do run { target avx_runtime } } */\n+/* { dg-options \"-fhardened -O3 -mavx\" } */\n+\n+struct a {\n+ unsigned long long b;\n+ unsigned long long c;\n+ int d;\n+ char e;\n+ int f;\n+} g;\n+int h = 1, i, j;\n+long long k, l, n;\n+int m[1]={};\n+short o;\n+static inline short p(short q, short r) { return q + r; }\n+int main() {\n+ for (; h < 3; h = p(h, 1))\n+ if (h) {\n+ k |= 4;\n+ struct a s = {8, 2, 2, 4, 15};\n+ for (int n = 0; n != 54; n++)\n+ if (m[l])\n+ if (i)\n+ o = 0;\n+ g = s;\n+ j &= 4073709551610LL;\n+ }\n+ return 0;\n+}\n-- \n2.53.0\n\n", "prefixes": [] }