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GET /api/patches/2219468/?format=api
{ "id": 2219468, "url": "http://patchwork.ozlabs.org/api/patches/2219468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403035541.18355-7-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260403035541.18355-7-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-04-03T03:55:30", "name": "[v3,06/14] intel_iommu: Export some functions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e85868af388a6e4b522f1dc692af7a379b866589", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403035541.18355-7-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 498583, "url": "http://patchwork.ozlabs.org/api/series/498583/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498583", "date": "2026-04-03T03:55:36", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498583/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219468/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219468/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=dvbjZuTD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fn4gN6zpgz1yCs\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 03 Apr 2026 14:57:36 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8Vdo-0001Eb-6c; Thu, 02 Apr 2026 23:56:16 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w8Vdm-0001EC-Rw\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 23:56:14 -0400", "from mgamail.intel.com ([198.175.65.19])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w8Vdk-0004N9-WD\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 23:56:14 -0400", "from fmviesa007.fm.intel.com ([10.60.135.147])\n by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Apr 2026 20:56:12 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Apr 2026 20:56:09 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775188573; x=1806724573;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Js9NLii87RvOIODDyynTxEH0ho3Q87bgpwCKHhwNZL8=;\n b=dvbjZuTDjP6LeKC2Zop9CR15jY7yKjVvUVDFB/jFX/chhe8oSKRIB9nW\n 0nQXo6jOJBmjHpqVq0zY16F9E62QIvKDtips7+wKw0KDJVyHGXDldrfWQ\n Tc3p2ZoScLVcrnj4bXF4u4HMylC4VTADE//3xvYL1QmSiS9EczPtjYjmt\n VDqJqNQ7bt1aI3/+oxrlGcKMDcY8DbGBjtiq/kVFYZzj2aFSF6eBy74MJ\n 7UlAZ5LSsYxHl+xPNhS9pilIVfPolktfewl47//p4LkOh8SjbXbi+/1Dz\n MZjcQaBdOY6oI/A3+8zrVXXMOS4SmitUhrcdFUbM9p40baajCEUdQKorQ Q==;", "X-CSE-ConnectionGUID": [ "0lh6xCszSi2vlb4QBnnGEg==", "bwyxdQLBQG6Dxh+UeAMqWQ==" ], "X-CSE-MsgGUID": [ "Av5nk56NSvG3EuFh5M5QFA==", "f6DIFUBOSGy6NBYKZtXNMw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11747\"; a=\"76140629\"", "E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"76140629\"", "E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"223884882\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>", "Subject": "[PATCH v3 06/14] intel_iommu: Export some functions", "Date": "Thu, 2 Apr 2026 23:55:30 -0400", "Message-ID": "<20260403035541.18355-7-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260403035541.18355-1-zhenzhong.duan@intel.com>", "References": "<20260403035541.18355-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.19;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-48", "X-Spam_score": "-4.9", "X-Spam_bar": "----", "X-Spam_report": "(-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.542,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Export some functions for accel code usages. Inline functions and MACROs\nare moved to internal header files. Then accel code in following patches\ncould access them.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nReviewed-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>\nReviewed-by: Yi Liu <yi.l.liu@intel.com>\nTested-by: Xudong Hao <xudong.hao@intel.com>\n---\n hw/i386/intel_iommu_internal.h | 31 +++++++++++++++++++++++++\n hw/i386/intel_iommu.c | 42 ++++++++--------------------------\n 2 files changed, 40 insertions(+), 33 deletions(-)", "diff": "diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex db4f186a3e..c7e107fe87 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -620,6 +620,12 @@ typedef struct VTDRootEntry VTDRootEntry;\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL\n #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL\n \n+/* context entry operations */\n+#define VTD_CE_GET_PASID_DIR_TABLE(ce) \\\n+ ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)\n+#define VTD_CE_GET_PRE(ce) \\\n+ ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)\n+\n typedef struct VTDPASIDCacheInfo {\n uint8_t type;\n uint16_t did;\n@@ -746,4 +752,29 @@ static inline bool vtd_pe_pgtt_is_fst(VTDPASIDEntry *pe)\n {\n return (VTD_SM_PASID_ENTRY_PGTT(pe) == VTD_SM_PASID_ENTRY_FST);\n }\n+\n+static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)\n+{\n+ return pdire->val & 1;\n+}\n+\n+static inline bool vtd_pe_present(VTDPASIDEntry *pe)\n+{\n+ return pe->val[0] & VTD_PASID_ENTRY_P;\n+}\n+\n+static inline int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n+{\n+ return memcmp(p1, p2, sizeof(*p1));\n+}\n+\n+int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n+ VTDPASIDDirEntry *pdire);\n+int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\n+ dma_addr_t addr, VTDPASIDEntry *pe);\n+int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n+ uint8_t devfn, VTDContextEntry *ce);\n+int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n+ VTDPASIDEntry *pe, uint32_t pasid);\n+VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid);\n #endif\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex 635e7ee145..aa67c89e73 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -42,12 +42,6 @@\n #include \"migration/vmstate.h\"\n #include \"trace.h\"\n \n-/* context entry operations */\n-#define VTD_CE_GET_PASID_DIR_TABLE(ce) \\\n- ((ce)->val[0] & VTD_PASID_DIR_BASE_ADDR_MASK)\n-#define VTD_CE_GET_PRE(ce) \\\n- ((ce)->val[0] & VTD_SM_CONTEXT_ENTRY_PRE)\n-\n /*\n * Paging mode for first-stage translation (VTD spec Figure 9-6)\n * 00: 4-level paging, 01: 5-level paging\n@@ -831,18 +825,12 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *s, VTDPASIDEntry *pe)\n }\n }\n \n-static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire)\n-{\n- return pdire->val & 1;\n-}\n-\n /**\n * Caller of this function should check present bit if wants\n * to use pdir entry for further usage except for fpd bit check.\n */\n-static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,\n- uint32_t pasid,\n- VTDPASIDDirEntry *pdire)\n+int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base, uint32_t pasid,\n+ VTDPASIDDirEntry *pdire)\n {\n uint32_t index;\n dma_addr_t addr, entry_size;\n@@ -860,15 +848,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pasid_dir_base,\n return 0;\n }\n \n-static inline bool vtd_pe_present(VTDPASIDEntry *pe)\n-{\n- return pe->val[0] & VTD_PASID_ENTRY_P;\n-}\n-\n-static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,\n- uint32_t pasid,\n- dma_addr_t addr,\n- VTDPASIDEntry *pe)\n+int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s, uint32_t pasid,\n+ dma_addr_t addr, VTDPASIDEntry *pe)\n {\n uint8_t pgtt;\n uint32_t index;\n@@ -954,8 +935,8 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,\n return 0;\n }\n \n-static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n- VTDPASIDEntry *pe, uint32_t pasid)\n+int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n+ VTDPASIDEntry *pe, uint32_t pasid)\n {\n dma_addr_t pasid_dir_base;\n \n@@ -1526,8 +1507,8 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce)\n }\n \n /* Map a device to its corresponding domain (context-entry) */\n-static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n- uint8_t devfn, VTDContextEntry *ce)\n+int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n+ uint8_t devfn, VTDContextEntry *ce)\n {\n VTDRootEntry re;\n int ret_fr;\n@@ -1909,7 +1890,7 @@ static VTDAddressSpace *vtd_get_as_by_sid_and_pasid(IntelIOMMUState *s,\n vtd_find_as_by_sid_and_pasid, &key);\n }\n \n-static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)\n+VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid)\n {\n return vtd_get_as_by_sid_and_pasid(s, sid, PCI_NO_PASID);\n }\n@@ -3133,11 +3114,6 @@ static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as,\n return vtd_ce_get_pasid_entry(s, &ce, pe, vtd_as->pasid);\n }\n \n-static int vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2)\n-{\n- return memcmp(p1, p2, sizeof(*p1));\n-}\n-\n /* Update or invalidate pasid cache based on the pasid entry in guest memory. */\n static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value,\n gpointer user_data)\n", "prefixes": [ "v3", "06/14" ] }