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GET /api/patches/2219460/?format=api
{ "id": 2219460, "url": "http://patchwork.ozlabs.org/api/patches/2219460/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403035541.18355-8-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260403035541.18355-8-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-04-03T03:55:31", "name": "[v3,07/14] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dcce02c5b061868cc92ae7911173df947071fbf4", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260403035541.18355-8-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 498584, "url": "http://patchwork.ozlabs.org/api/series/498584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498584", "date": "2026-04-03T03:55:31", "name": null, "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219460/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219460/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=nBaQUD6U;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fn4g869D9z1yCs\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 03 Apr 2026 14:57:23 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8Vdq-0001FB-VV; Thu, 02 Apr 2026 23:56:19 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w8Vdq-0001Ew-4S\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 23:56:18 -0400", "from mgamail.intel.com ([198.175.65.19])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w8Vdo-0004N9-Es\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 23:56:17 -0400", "from fmviesa007.fm.intel.com ([10.60.135.147])\n by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Apr 2026 20:56:15 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 02 Apr 2026 20:56:12 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775188576; x=1806724576;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=iQaCmLmcKbdNrlzqxau5uvh3eGSoDbU2Iuqgw7ziD1M=;\n b=nBaQUD6UyH4yhBVgrkxnVxSZRUeTIBDSSKMWmdoBSBRRYay28bjodkGw\n 8Y8z+Q+S9f7i0zoESsW8uPTkeGK4sxpN8CXI3NSYRreZg/6G9TViH2Zcp\n bICviZawERHXpu1HYsZNIJbY77G/QKhAEQy2yfhjaADt0GcXyLjIBZh/l\n 3go3PevfCq3UpyhWEsczI634ucHT+ongCWmLya1bdFVjD+JIiKOwrylMD\n 0hInipMTKKdpeOLAUL5uIv8WuOvxOjoBvASqgemVxErU2nI3jtEesXR5+\n ZdjOQGPDPPFrthzDr+T0gj7XMPx/+5SjvFxmrEcH3tnPW8YAdAEa2zRdl w==;", "X-CSE-ConnectionGUID": [ "r/9A47wSTQyqd50gkcmyyg==", "6AriUrPARGeJH4hE35nvww==" ], "X-CSE-MsgGUID": [ "32EXtFCgR22Ln9blBmh7WA==", "exCLPoykTNmf0W7GENFdJQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11747\"; a=\"76140638\"", "E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"76140638\"", "E=Sophos;i=\"6.23,157,1770624000\"; d=\"scan'208\";a=\"223884888\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH v3 07/14] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0", "Date": "Thu, 2 Apr 2026 23:55:31 -0400", "Message-ID": "<20260403035541.18355-8-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260403035541.18355-1-zhenzhong.duan@intel.com>", "References": "<20260403035541.18355-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.19;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-48", "X-Spam_score": "-4.9", "X-Spam_bar": "----", "X-Spam_report": "(-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.542,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "In previous patch we introduced a global macro IOMMU_NO_PASID(0) for\nRequests-without-PASID, this makes the local macro PASID_0 redundant.\nDelete it and use IOMMU_NO_PASID instead.\n\nSuggested-by: Yi Liu <yi.l.liu@intel.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nTested-by: Xudong Hao <xudong.hao@intel.com>\n---\n hw/i386/intel_iommu_internal.h | 1 -\n hw/i386/intel_iommu.c | 18 +++++++++---------\n hw/i386/intel_iommu_accel.c | 2 +-\n 3 files changed, 10 insertions(+), 11 deletions(-)", "diff": "diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex c7e107fe87..0141316f83 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -615,7 +615,6 @@ typedef struct VTDRootEntry VTDRootEntry;\n #define VTD_CTX_ENTRY_LEGACY_SIZE 16\n #define VTD_CTX_ENTRY_SCALABLE_SIZE 32\n \n-#define PASID_0 0\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw))\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL\n #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex aa67c89e73..3b8d3a96d2 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -941,7 +941,7 @@ int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n dma_addr_t pasid_dir_base;\n \n if (pasid == PCI_NO_PASID) {\n- pasid = PASID_0;\n+ pasid = IOMMU_NO_PASID;\n }\n pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);\n return vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe);\n@@ -958,7 +958,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,\n VTDPASIDEntry pe;\n \n if (pasid == PCI_NO_PASID) {\n- pasid = PASID_0;\n+ pasid = IOMMU_NO_PASID;\n }\n pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);\n \n@@ -1501,9 +1501,9 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce)\n \n /*\n * Make sure in Scalable Mode, a present context entry\n- * has valid pasid entry setting at PASID_0.\n+ * has valid pasid entry setting at IOMMU_NO_PASID.\n */\n- return vtd_ce_get_pasid_entry(s, ce, &pe, PASID_0);\n+ return vtd_ce_get_pasid_entry(s, ce, &pe, IOMMU_NO_PASID);\n }\n \n /* Map a device to its corresponding domain (context-entry) */\n@@ -1564,7 +1564,7 @@ int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n }\n } else {\n /*\n- * Check if the programming of pasid setting of PASID_0\n+ * Check if the programming of pasid setting of IOMMU_NO_PASID\n * is valid, and thus avoids to check pasid entry fetching\n * result in future helper function calling.\n */\n@@ -2122,7 +2122,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,\n vtd_iommu_lock(s);\n \n if (pasid == PCI_NO_PASID && s->root_scalable) {\n- pasid = PASID_0;\n+ pasid = IOMMU_NO_PASID;\n }\n \n /* Try to fetch pte from IOTLB */\n@@ -2508,10 +2508,10 @@ static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,\n * In legacy mode, vtd_as->pasid == pasid is always true.\n * In scalable mode, for vtd address space backing a PCI\n * device without pasid, needs to compare pasid with\n- * PASID_0 of this device.\n+ * IOMMU_NO_PASID of this device.\n */\n if (!(vtd_as->pasid == pasid ||\n- (vtd_as->pasid == PCI_NO_PASID && pasid == PASID_0))) {\n+ (vtd_as->pasid == PCI_NO_PASID && pasid == IOMMU_NO_PASID))) {\n continue;\n }\n \n@@ -3022,7 +3022,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s,\n if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),\n vtd_as->devfn, &ce) &&\n domain_id == vtd_get_domain_id(s, &ce, vtd_as->pasid)) {\n- if ((vtd_as->pasid != PCI_NO_PASID || pasid != PASID_0) &&\n+ if ((vtd_as->pasid != PCI_NO_PASID || pasid != IOMMU_NO_PASID) &&\n vtd_as->pasid != pasid) {\n continue;\n }\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex bd1236c070..8940d240a1 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -217,7 +217,7 @@ static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value,\n \n did = VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry);\n \n- if (piotlb_info->domain_id == did && piotlb_info->pasid == PASID_0) {\n+ if (piotlb_info->domain_id == did && piotlb_info->pasid == IOMMU_NO_PASID) {\n HostIOMMUDeviceIOMMUFD *hiodi =\n HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);\n uint32_t entry_num = 1; /* Only implement one request for simplicity */\n", "prefixes": [ "v3", "07/14" ] }