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GET /api/patches/2219453/?format=api
{ "id": 2219453, "url": "http://patchwork.ozlabs.org/api/patches/2219453/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260403022513.9446-8-alif.zakuan.yuslaimi@altera.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260403022513.9446-8-alif.zakuan.yuslaimi@altera.com>", "list_archive_url": null, "date": "2026-04-03T02:25:11", "name": "[v1,7/9] clk: s10: Refactor S10 clock driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d489921c0bbe2c1158496c73f7027277be4102b7", "submitter": { "id": 90458, "url": "http://patchwork.ozlabs.org/api/people/90458/?format=api", "name": "Yuslaimi, Alif Zakuan", "email": "alif.zakuan.yuslaimi@altera.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260403022513.9446-8-alif.zakuan.yuslaimi@altera.com/mbox/", "series": [ { "id": 498580, "url": "http://patchwork.ozlabs.org/api/series/498580/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498580", "date": "2026-04-03T02:25:04", "name": "SoCFPGA: Update Boot Support for Stratix10 in U-Boot", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498580/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219453/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219453/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=kahtj+la;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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This allows several APIs such as enable/disable clock, and\nget clock rate to be supported.\n\nThis driver will be initialized during SPL to bring up the clock as early\nas possible. The clock initialization process are refactored into this new\ndriver from clock_manager_s10.c during clock driver probe.\n\nExcluding Stratix10 from legacy method of obtaining clkmgr base address in\nmach-socfpga/misc.c as the base address is already obtained during clock\ndriver probe during SPL initialization.\n\nSigned-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>\n---\n MAINTAINERS | 1 +\n arch/arm/mach-socfpga/Kconfig | 2 +\n arch/arm/mach-socfpga/clock_manager_s10.c | 449 ++-----------\n .../include/mach/clock_manager_s10.h | 176 +-----\n arch/arm/mach-socfpga/misc.c | 3 +-\n arch/arm/mach-socfpga/spl_s10.c | 7 +-\n drivers/clk/altera/Makefile | 1 +\n drivers/clk/altera/clk-s10.c | 591 ++++++++++++++++++\n drivers/clk/altera/clk-s10.h | 202 ++++++\n 9 files changed, 861 insertions(+), 571 deletions(-)\n create mode 100644 drivers/clk/altera/clk-s10.c\n create mode 100644 drivers/clk/altera/clk-s10.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex c58d8f85e33..863e0b763d8 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -159,6 +159,7 @@ F:\tarch/arm/mach-socfpga/\n F:\tboard/altera/stratix10-socdk/\n F:\tboard/intel/agilex-socdk/\n F:\tconfigs/socfpga_*\n+F:\tdrivers/clk/altera/\n F:\tdrivers/ddr/altera/\n F:\tdrivers/power/domain/altr-pmgr-agilex5.c\n F:\tdrivers/sysreset/sysreset_socfpga*\ndiff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex aec0fb7b1c8..c7ecdc4055f 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -149,8 +149,10 @@ config ARCH_SOCFPGA_STRATIX10\n \tselect ARMV8_MULTIENTRY\n \tselect ARMV8_SET_SMPEN\n \tselect BINMAN if SPL_ATF\n+\tselect CLK\n \tselect FPGA_INTEL_SDM_MAILBOX\n \tselect GICV2\n+\tselect SPL_CLK if SPL\n \tselect ARCH_SOCFPGA_SOC64\n \n choice\ndiff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c\nindex fd27470f967..df636f14f93 100644\n--- a/arch/arm/mach-socfpga/clock_manager_s10.c\n+++ b/arch/arm/mach-socfpga/clock_manager_s10.c\n@@ -1,425 +1,78 @@\n // SPDX-License-Identifier: GPL-2.0\n /*\n- * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>\n+ * Copyright (C) 2026 Altera Corporation <www.altera.com>\n *\n */\n \n-#include <compiler.h>\n-#include <dm/device.h>\n-#include <linux/errno.h>\n-#include <asm/io.h>\n+#include <clk.h>\n+#include <dm.h>\n+#include <log.h>\n+#include <malloc.h>\n #include <asm/arch/clock_manager.h>\n-#include <asm/arch/handoff_soc64.h>\n #include <asm/arch/system_manager.h>\n+#include <asm/io.h>\n+#include <dt-bindings/clock/stratix10-clock.h>\n \n-/*\n- * function to write the bypass register which requires a poll of the\n- * busy bit\n- */\n-static void cm_write_bypass_mainpll(u32 val)\n-{\n-\twritel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_BYPASS);\n-\tcm_wait_for_fsm();\n-}\n-\n-static void cm_write_bypass_perpll(u32 val)\n-{\n-\twritel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_BYPASS);\n-\tcm_wait_for_fsm();\n-}\n-\n-/* function to write the ctrl register which requires a poll of the busy bit */\n-static void cm_write_ctrl(u32 val)\n-{\n-\twritel(val, socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL);\n-\tcm_wait_for_fsm();\n-}\n-\n-/*\n- * Setup clocks while making no assumptions about previous state of the clocks.\n- */\n-void cm_basic_init(const struct cm_config * const cfg)\n-{\n-\tu32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;\n-\n-\tif (cfg == 0)\n-\t\treturn;\n-\n-\t/* Put all plls in bypass */\n-\tcm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);\n-\tcm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);\n-\n-\t/* setup main PLL dividers where calculate the vcocalib value */\n-\tmdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n-\t\tCLKMGR_FDBCK_MDIV_MASK;\n-\trefclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n-\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n-\tmscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;\n-\thscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -\n-\t\tCLKMGR_HSCNT_CONST;\n-\tvcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n-\t\t ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n-\t\t CLKMGR_VCOCALIB_MSCNT_OFFSET);\n-\n-\twritel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n-\t\t~CLKMGR_PLLGLOB_RST_MASK),\n-\t\tsocfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);\n-\twritel(cfg->main_pll_fdbck,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);\n-\twritel(vcocalib,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_VCOCALIB);\n-\twritel(cfg->main_pll_pllc0,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC0);\n-\twritel(cfg->main_pll_pllc1,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLC1);\n-\twritel(cfg->main_pll_nocdiv,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCDIV);\n-\n-\t/* setup peripheral PLL dividers */\n-\t/* calculate the vcocalib value */\n-\tmdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n-\t\tCLKMGR_FDBCK_MDIV_MASK;\n-\trefclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n-\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n-\tmscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;\n-\thscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -\n-\t\tCLKMGR_HSCNT_CONST;\n-\tvcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n-\t\t ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n-\t\t CLKMGR_VCOCALIB_MSCNT_OFFSET);\n-\n-\twritel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n-\t\t~CLKMGR_PLLGLOB_RST_MASK),\n-\t\tsocfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);\n-\twritel(cfg->per_pll_fdbck,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);\n-\twritel(vcocalib,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_VCOCALIB);\n-\twritel(cfg->per_pll_pllc0,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC0);\n-\twritel(cfg->per_pll_pllc1,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLC1);\n-\twritel(cfg->per_pll_emacctl,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EMACCTL);\n-\twritel(cfg->per_pll_gpiodiv,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_GPIODIV);\n-\n-\t/* Take both PLL out of reset and power up */\n-\tsetbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB,\n-\t\t CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n-\tsetbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB,\n-\t\t CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n-\n-#define LOCKED_MASK \\\n-\t(CLKMGR_STAT_MAINPLL_LOCKED | \\\n-\tCLKMGR_STAT_PERPLL_LOCKED)\n-\n-\tcm_wait_for_lock(LOCKED_MASK);\n-\n-\t/*\n-\t * Dividers for C2 to C9 only init after PLLs are lock. As dividers\n-\t * only take effect upon value change, we shall set a maximum value as\n-\t * default value.\n-\t */\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);\n-\twritel(0xff, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);\n-\n-\twritel(cfg->main_pll_mpuclk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_MPUCLK);\n-\twritel(cfg->main_pll_nocclk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_NOCCLK);\n-\twritel(cfg->main_pll_cntr2clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR2CLK);\n-\twritel(cfg->main_pll_cntr3clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR3CLK);\n-\twritel(cfg->main_pll_cntr4clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR4CLK);\n-\twritel(cfg->main_pll_cntr5clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR5CLK);\n-\twritel(cfg->main_pll_cntr6clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR6CLK);\n-\twritel(cfg->main_pll_cntr7clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR7CLK);\n-\twritel(cfg->main_pll_cntr8clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR8CLK);\n-\twritel(cfg->main_pll_cntr9clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_CNTR9CLK);\n-\twritel(cfg->per_pll_cntr2clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR2CLK);\n-\twritel(cfg->per_pll_cntr3clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR3CLK);\n-\twritel(cfg->per_pll_cntr4clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR4CLK);\n-\twritel(cfg->per_pll_cntr5clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR5CLK);\n-\twritel(cfg->per_pll_cntr6clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR6CLK);\n-\twritel(cfg->per_pll_cntr7clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR7CLK);\n-\twritel(cfg->per_pll_cntr8clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR8CLK);\n-\twritel(cfg->per_pll_cntr9clk,\n-\t socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_CNTR9CLK);\n-\n-\t/* Take all PLLs out of bypass */\n-\tcm_write_bypass_mainpll(0);\n-\tcm_write_bypass_perpll(0);\n-\n-\t/* clear safe mode / out of boot mode */\n-\tcm_write_ctrl(readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_CTRL) &\n-\t\t ~(CLKMGR_CTRL_SAFEMODE));\n-\n-\t/* Now ungate non-hw-managed clocks */\n-\twritel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_EN);\n-\twritel(~0, socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_EN);\n-\n-\t/* Clear the loss of lock bits (write 1 to clear) */\n-\twritel(CLKMGR_INTER_PERPLLLOST_MASK |\n-\t\t CLKMGR_INTER_MAINPLLLOST_MASK,\n-\t\t socfpga_get_clkmgr_addr() + CLKMGR_S10_INTRCLR);\n-}\n-\n-static unsigned long cm_get_main_vco_clk_hz(void)\n+static ulong cm_get_rate_dm(u32 id)\n {\n-\t unsigned long fref, refdiv, mdiv, reg, vco;\n-\n-\treg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_PLLGLOB);\n-\n-\tfref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n-\t\tCLKMGR_PLLGLOB_VCO_PSRC_MASK;\n-\tswitch (fref) {\n-\tcase CLKMGR_VCO_PSRC_EOSC1:\n-\t\tfref = cm_get_osc_clk_hz();\n-\t\tbreak;\n-\tcase CLKMGR_VCO_PSRC_INTOSC:\n-\t\tfref = cm_get_intosc_clk_hz();\n-\t\tbreak;\n-\tcase CLKMGR_VCO_PSRC_F2S:\n-\t\tfref = cm_get_fpga_clk_hz();\n-\t\tbreak;\n+\tstruct udevice *dev;\n+\tstruct clk clk;\n+\tulong rate;\n+\tint ret;\n+\n+\tret = uclass_get_device_by_driver(UCLASS_CLK,\n+\t\t\t\t\t DM_DRIVER_GET(socfpga_s10_clk),\n+\t\t\t\t\t &dev);\n+\tif (ret)\n+\t\treturn 0;\n+\n+\tclk.id = id;\n+\tret = clk_request(dev, &clk);\n+\tif (ret < 0)\n+\t\treturn 0;\n+\n+\trate = clk_get_rate(&clk);\n+\n+\tif ((rate == (unsigned long)-ENOSYS) ||\n+\t (rate == (unsigned long)-ENXIO) ||\n+\t (rate == (unsigned long)-EIO)) {\n+\t\tdebug(\"%s id %u: clk_get_rate err: %ld\\n\",\n+\t\t __func__, id, rate);\n+\t\treturn 0;\n \t}\n \n-\trefdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n-\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n-\n-\treg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_MAINPLL_FDBCK);\n-\tmdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n-\n-\tvco = fref / refdiv;\n-\tvco = vco * (CLKMGR_MDIV_CONST + mdiv);\n-\treturn vco;\n+\treturn rate;\n }\n \n-static unsigned long cm_get_per_vco_clk_hz(void)\n+static u32 cm_get_rate_dm_khz(u32 id)\n {\n-\tunsigned long fref, refdiv, mdiv, reg, vco;\n-\n-\treg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_PLLGLOB);\n-\n-\tfref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n-\t\tCLKMGR_PLLGLOB_VCO_PSRC_MASK;\n-\tswitch (fref) {\n-\tcase CLKMGR_VCO_PSRC_EOSC1:\n-\t\tfref = cm_get_osc_clk_hz();\n-\t\tbreak;\n-\tcase CLKMGR_VCO_PSRC_INTOSC:\n-\t\tfref = cm_get_intosc_clk_hz();\n-\t\tbreak;\n-\tcase CLKMGR_VCO_PSRC_F2S:\n-\t\tfref = cm_get_fpga_clk_hz();\n-\t\tbreak;\n-\t}\n-\n-\trefdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n-\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n-\n-\treg = readl(socfpga_get_clkmgr_addr() + CLKMGR_S10_PERPLL_FDBCK);\n-\tmdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n-\n-\tvco = fref / refdiv;\n-\tvco = vco * (CLKMGR_MDIV_CONST + mdiv);\n-\treturn vco;\n+\treturn cm_get_rate_dm(id) / 1000;\n }\n \n unsigned long cm_get_mpu_clk_hz(void)\n {\n-\tunsigned long clock = readl(socfpga_get_clkmgr_addr() +\n-\t\t\t\t CLKMGR_S10_MAINPLL_MPUCLK);\n-\n-\tclock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n-\n-\tswitch (clock) {\n-\tcase CLKMGR_CLKSRC_MAIN:\n-\t\tclock = cm_get_main_vco_clk_hz();\n-\t\tclock /= (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t\tCLKMGR_S10_MAINPLL_PLLC0) &\n-\t\t\t CLKMGR_PLLC0_DIV_MASK);\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_PER:\n-\t\tclock = cm_get_per_vco_clk_hz();\n-\t\tclock /= (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t\tCLKMGR_S10_PERPLL_PLLC0) &\n-\t\t\t CLKMGR_CLKCNT_MSK);\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_OSC1:\n-\t\tclock = cm_get_osc_clk_hz();\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_INTOSC:\n-\t\tclock = cm_get_intosc_clk_hz();\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_FPGA:\n-\t\tclock = cm_get_fpga_clk_hz();\n-\t\tbreak;\n-\t}\n-\n-\tclock /= 1 + (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t CLKMGR_S10_MAINPLL_MPUCLK) & CLKMGR_CLKCNT_MSK);\n-\treturn clock;\n-}\n-\n-unsigned int cm_get_l3_main_clk_hz(void)\n-{\n-\tu32 clock = readl(socfpga_get_clkmgr_addr() +\n-\t\t\t CLKMGR_S10_MAINPLL_NOCCLK);\n-\n-\tclock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n-\n-\tswitch (clock) {\n-\tcase CLKMGR_CLKSRC_MAIN:\n-\t\tclock = cm_get_main_vco_clk_hz();\n-\t\tclock /= (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t\tCLKMGR_S10_MAINPLL_PLLC1) &\n-\t\t\t CLKMGR_PLLC0_DIV_MASK);\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_PER:\n-\t\tclock = cm_get_per_vco_clk_hz();\n-\t\tclock /= (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t CLKMGR_S10_PERPLL_PLLC1) & CLKMGR_CLKCNT_MSK);\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_OSC1:\n-\t\tclock = cm_get_osc_clk_hz();\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_INTOSC:\n-\t\tclock = cm_get_intosc_clk_hz();\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_FPGA:\n-\t\tclock = cm_get_fpga_clk_hz();\n-\t\tbreak;\n-\t}\n-\n-\tclock /= 1 + (readl(socfpga_get_clkmgr_addr() +\n-\t\t CLKMGR_S10_MAINPLL_NOCCLK) & CLKMGR_CLKCNT_MSK);\n-\treturn clock;\n-}\n-\n-unsigned int cm_get_mmc_controller_clk_hz(void)\n-{\n-\tu32 clock = readl(socfpga_get_clkmgr_addr() +\n-\t\t\t CLKMGR_S10_PERPLL_CNTR6CLK);\n-\n-\tclock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n-\n-\tswitch (clock) {\n-\tcase CLKMGR_CLKSRC_MAIN:\n-\t\tclock = cm_get_l3_main_clk_hz();\n-\t\tclock /= 1 + (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t\t CLKMGR_S10_MAINPLL_CNTR6CLK) &\n-\t\t\t CLKMGR_CLKCNT_MSK);\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_PER:\n-\t\tclock = cm_get_l3_main_clk_hz();\n-\t\tclock /= 1 + (readl(socfpga_get_clkmgr_addr() +\n-\t\t\t\t CLKMGR_S10_PERPLL_CNTR6CLK) &\n-\t\t\t CLKMGR_CLKCNT_MSK);\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_OSC1:\n-\t\tclock = cm_get_osc_clk_hz();\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_INTOSC:\n-\t\tclock = cm_get_intosc_clk_hz();\n-\t\tbreak;\n-\n-\tcase CLKMGR_CLKSRC_FPGA:\n-\t\tclock = cm_get_fpga_clk_hz();\n-\t\tbreak;\n-\t}\n-\treturn clock / 4;\n-}\n-\n-unsigned int cm_get_l4_sp_clk_hz(void)\n-{\n-\tu32 clock = cm_get_l3_main_clk_hz();\n-\n-\tclock /= (1 << ((readl(socfpga_get_clkmgr_addr() +\n-\t\t\t CLKMGR_S10_MAINPLL_NOCDIV) >>\n-\t\t\t CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));\n-\treturn clock;\n-}\n-\n-unsigned int cm_get_spi_controller_clk_hz(void)\n-{\n-\tu32 clock = cm_get_l3_main_clk_hz();\n-\n-\tclock /= (1 << ((readl(socfpga_get_clkmgr_addr() +\n-\t\t\t CLKMGR_S10_MAINPLL_NOCDIV) >>\n-\t\t\t CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));\n-\treturn clock;\n+\treturn cm_get_rate_dm(STRATIX10_MPU_CLK);\n }\n \n unsigned int cm_get_l4_sys_free_clk_hz(void)\n {\n-\treturn cm_get_l3_main_clk_hz() / 4;\n-}\n-\n-/*\n- * Override weak dw_spi_get_clk implementation in designware_spi.c driver\n- */\n-\n-int dw_spi_get_clk(struct udevice *bus, ulong *rate)\n-{\n-\t*rate = cm_get_spi_controller_clk_hz();\n-\tif (!*rate) {\n-\t\tprintf(\"SPI: clock rate is zero\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treturn 0;\n+\treturn cm_get_rate_dm(STRATIX10_L4_SYS_FREE_CLK);\n }\n \n void cm_print_clock_quick_summary(void)\n {\n-\tprintf(\"MPU %d kHz\\n\", (u32)(cm_get_mpu_clk_hz() / 1000));\n-\tprintf(\"L3 main %d kHz\\n\", cm_get_l3_main_clk_hz() / 1000);\n-\tprintf(\"Main VCO %d kHz\\n\", (u32)(cm_get_main_vco_clk_hz() / 1000));\n-\tprintf(\"Per VCO %d kHz\\n\", (u32)(cm_get_per_vco_clk_hz() / 1000));\n-\tprintf(\"EOSC1 %d kHz\\n\", cm_get_osc_clk_hz() / 1000);\n-\tprintf(\"HPS MMC %d kHz\\n\", cm_get_mmc_controller_clk_hz() / 1000);\n-\tprintf(\"UART %d kHz\\n\", cm_get_l4_sp_clk_hz() / 1000);\n+\tprintf(\"MPU %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_MPU_CLK));\n+\tprintf(\"L3 main %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_NOC_CLK));\n+\tprintf(\"Main VCO %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_MAIN_PLL_CLK));\n+\tprintf(\"Per VCO %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_PERIPH_PLL_CLK));\n+\tprintf(\"EOSC1 %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_OSC1));\n+\tprintf(\"HPS MMC %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_SDMMC_CLK));\n+\tprintf(\"UART %d kHz\\n\",\n+\t cm_get_rate_dm_khz(STRATIX10_L4_SP_CLK));\n }\ndiff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\nindex 5dcbda9473e..e5ff0648b86 100644\n--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h\n@@ -1,177 +1,13 @@\n-/* SPDX-License-Identifier: GPL-2.0\n- *\n- * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2026 Altera Corporation <www.altera.com>\n *\n */\n \n-#ifndef\t_CLOCK_MANAGER_S10_\n-#define\t_CLOCK_MANAGER_S10_\n+#ifndef _CLOCK_MANAGER_S10_\n+#define _CLOCK_MANAGER_S10_\n \n #include <asm/arch/clock_manager_soc64.h>\n-#include <linux/bitops.h>\n-\n-/* Clock speed accessors */\n-unsigned long cm_get_sdram_clk_hz(void);\n-unsigned int cm_get_l4_sp_clk_hz(void);\n-unsigned int cm_get_mmc_controller_clk_hz(void);\n-unsigned int cm_get_spi_controller_clk_hz(void);\n-\n-struct cm_config {\n-\t/* main group */\n-\tu32 main_pll_mpuclk;\n-\tu32 main_pll_nocclk;\n-\tu32 main_pll_cntr2clk;\n-\tu32 main_pll_cntr3clk;\n-\tu32 main_pll_cntr4clk;\n-\tu32 main_pll_cntr5clk;\n-\tu32 main_pll_cntr6clk;\n-\tu32 main_pll_cntr7clk;\n-\tu32 main_pll_cntr8clk;\n-\tu32 main_pll_cntr9clk;\n-\tu32 main_pll_nocdiv;\n-\tu32 main_pll_pllglob;\n-\tu32 main_pll_fdbck;\n-\tu32 main_pll_pllc0;\n-\tu32 main_pll_pllc1;\n-\tu32 spare;\n-\n-\t/* peripheral group */\n-\tu32 per_pll_cntr2clk;\n-\tu32 per_pll_cntr3clk;\n-\tu32 per_pll_cntr4clk;\n-\tu32 per_pll_cntr5clk;\n-\tu32 per_pll_cntr6clk;\n-\tu32 per_pll_cntr7clk;\n-\tu32 per_pll_cntr8clk;\n-\tu32 per_pll_cntr9clk;\n-\tu32 per_pll_emacctl;\n-\tu32 per_pll_gpiodiv;\n-\tu32 per_pll_pllglob;\n-\tu32 per_pll_fdbck;\n-\tu32 per_pll_pllc0;\n-\tu32 per_pll_pllc1;\n-\n-\t/* incoming clock */\n-\tu32 hps_osc_clk_hz;\n-\tu32 fpga_clk_hz;\n-};\n-\n-void cm_basic_init(const struct cm_config * const cfg);\n-\n-/* Control status */\n-#define CLKMGR_S10_CTRL\t\t\t\t\t0x00\n-#define CLKMGR_S10_STAT\t\t\t\t\t0x04\n-#define CLKMGR_S10_INTRCLR\t\t\t\t0x14\n-/* Mainpll group */\n-#define CLKMGR_S10_MAINPLL_EN\t\t\t\t0x30\n-#define CLKMGR_S10_MAINPLL_BYPASS\t\t\t0x3c\n-#define CLKMGR_S10_MAINPLL_MPUCLK\t\t\t0x48\n-#define CLKMGR_S10_MAINPLL_NOCCLK\t\t\t0x4c\n-#define CLKMGR_S10_MAINPLL_CNTR2CLK\t\t\t0x50\n-#define CLKMGR_S10_MAINPLL_CNTR3CLK\t\t\t0x54\n-#define CLKMGR_S10_MAINPLL_CNTR4CLK\t\t\t0x58\n-#define CLKMGR_S10_MAINPLL_CNTR5CLK\t\t\t0x5c\n-#define CLKMGR_S10_MAINPLL_CNTR6CLK\t\t\t0x60\n-#define CLKMGR_S10_MAINPLL_CNTR7CLK\t\t\t0x64\n-#define CLKMGR_S10_MAINPLL_CNTR8CLK\t\t\t0x68\n-#define CLKMGR_S10_MAINPLL_CNTR9CLK\t\t\t0x6c\n-#define CLKMGR_S10_MAINPLL_NOCDIV\t\t\t0x70\n-#define CLKMGR_S10_MAINPLL_PLLGLOB\t\t\t0x74\n-#define CLKMGR_S10_MAINPLL_FDBCK\t\t\t0x78\n-#define CLKMGR_S10_MAINPLL_MEMSTAT\t\t\t0x80\n-#define CLKMGR_S10_MAINPLL_PLLC0\t\t\t0x84\n-#define CLKMGR_S10_MAINPLL_PLLC1\t\t\t0x88\n-#define CLKMGR_S10_MAINPLL_VCOCALIB\t\t\t0x8c\n-/* Periphpll group */\n-#define CLKMGR_S10_PERPLL_EN\t\t\t\t0xa4\n-#define CLKMGR_S10_PERPLL_BYPASS\t\t\t0xb0\n-#define CLKMGR_S10_PERPLL_CNTR2CLK\t\t\t0xbc\n-#define CLKMGR_S10_PERPLL_CNTR3CLK\t\t\t0xc0\n-#define CLKMGR_S10_PERPLL_CNTR4CLK\t\t\t0xc4\n-#define CLKMGR_S10_PERPLL_CNTR5CLK\t\t\t0xc8\n-#define CLKMGR_S10_PERPLL_CNTR6CLK\t\t\t0xcc\n-#define CLKMGR_S10_PERPLL_CNTR7CLK\t\t\t0xd0\n-#define CLKMGR_S10_PERPLL_CNTR8CLK\t\t\t0xd4\n-#define CLKMGR_S10_PERPLL_CNTR9CLK\t\t\t0xd8\n-#define CLKMGR_S10_PERPLL_EMACCTL\t\t\t0xdc\n-#define CLKMGR_S10_PERPLL_GPIODIV\t\t\t0xe0\n-#define CLKMGR_S10_PERPLL_PLLGLOB\t\t\t0xe4\n-#define CLKMGR_S10_PERPLL_FDBCK\t\t\t\t0xe8\n-#define CLKMGR_S10_PERPLL_MEMSTAT\t\t\t0xf0\n-#define CLKMGR_S10_PERPLL_PLLC0\t\t\t\t0xf4\n-#define CLKMGR_S10_PERPLL_PLLC1\t\t\t\t0xf8\n-#define CLKMGR_S10_PERPLL_VCOCALIB\t\t\t0xfc\n-\n-#define CLKMGR_STAT\t\t\t\t\tCLKMGR_S10_STAT\n-#define CLKMGR_INTER\t\t\t\t\tCLKMGR_S10_INTER\n-#define CLKMGR_PERPLL_EN\t\t\t\tCLKMGR_S10_PERPLL_EN\n-\n-#define CLKMGR_CTRL_SAFEMODE\t\t\t\tBIT(0)\n-#define CLKMGR_BYPASS_MAINPLL_ALL\t\t\t0x00000007\n-#define CLKMGR_BYPASS_PERPLL_ALL\t\t\t0x0000007f\n-\n-#define CLKMGR_INTER_MAINPLLLOCKED_MASK\t\t\t0x00000001\n-#define CLKMGR_INTER_PERPLLLOCKED_MASK\t\t\t0x00000002\n-#define CLKMGR_INTER_MAINPLLLOST_MASK\t\t\t0x00000004\n-#define CLKMGR_INTER_PERPLLLOST_MASK\t\t\t0x00000008\n-#define CLKMGR_STAT_BUSY\t\t\t\tBIT(0)\n-#define CLKMGR_STAT_MAINPLL_LOCKED\t\t\tBIT(8)\n-#define CLKMGR_STAT_PERPLL_LOCKED\t\t\tBIT(9)\n-\n-#define CLKMGR_PLLGLOB_PD_MASK\t\t\t\t0x00000001\n-#define CLKMGR_PLLGLOB_RST_MASK\t\t\t\t0x00000002\n-#define CLKMGR_PLLGLOB_VCO_PSRC_MASK\t\t\t0x3\n-#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET\t\t\t16\n-#define CLKMGR_VCO_PSRC_EOSC1\t\t\t\t0\n-#define CLKMGR_VCO_PSRC_INTOSC\t\t\t\t1\n-#define CLKMGR_VCO_PSRC_F2S\t\t\t\t2\n-#define CLKMGR_PLLGLOB_REFCLKDIV_MASK\t\t\t0x3f\n-#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET\t\t\t8\n-\n-#define CLKMGR_CLKSRC_MASK\t\t\t\t0x7\n-#define CLKMGR_CLKSRC_OFFSET\t\t\t\t16\n-#define CLKMGR_CLKSRC_MAIN\t\t\t\t0\n-#define CLKMGR_CLKSRC_PER\t\t\t\t1\n-#define CLKMGR_CLKSRC_OSC1\t\t\t\t2\n-#define CLKMGR_CLKSRC_INTOSC\t\t\t\t3\n-#define CLKMGR_CLKSRC_FPGA\t\t\t\t4\n-#define CLKMGR_CLKCNT_MSK\t\t\t\t0x7ff\n-\n-#define CLKMGR_FDBCK_MDIV_MASK\t\t\t\t0xff\n-#define CLKMGR_FDBCK_MDIV_OFFSET\t\t\t24\n-\n-#define CLKMGR_PLLC0_DIV_MASK\t\t\t\t0xff\n-#define CLKMGR_PLLC1_DIV_MASK\t\t\t\t0xff\n-#define CLKMGR_PLLC0_EN_OFFSET\t\t\t\t27\n-#define CLKMGR_PLLC1_EN_OFFSET\t\t\t\t24\n-\n-#define CLKMGR_NOCDIV_L4MAIN_OFFSET\t\t\t0\n-#define CLKMGR_NOCDIV_L4MPCLK_OFFSET\t\t\t8\n-#define CLKMGR_NOCDIV_L4SPCLK_OFFSET\t\t\t16\n-#define CLKMGR_NOCDIV_CSATCLK_OFFSET\t\t\t24\n-#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET\t\t\t26\n-#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET\t\t\t28\n-\n-#define CLKMGR_NOCDIV_L4SPCLK_MASK\t\t\t0x3\n-#define CLKMGR_NOCDIV_DIV1\t\t\t\t0\n-#define CLKMGR_NOCDIV_DIV2\t\t\t\t1\n-#define CLKMGR_NOCDIV_DIV4\t\t\t\t2\n-#define CLKMGR_NOCDIV_DIV8\t\t\t\t3\n-#define CLKMGR_CSPDBGCLK_DIV1\t\t\t\t0\n-#define CLKMGR_CSPDBGCLK_DIV4\t\t\t\t1\n-\n-#define CLKMGR_MSCNT_CONST\t\t\t\t200\n-#define CLKMGR_MDIV_CONST\t\t\t\t6\n-#define CLKMGR_HSCNT_CONST\t\t\t\t9\n-\n-#define CLKMGR_VCOCALIB_MSCNT_MASK\t\t\t0xff\n-#define CLKMGR_VCOCALIB_MSCNT_OFFSET\t\t\t9\n-#define CLKMGR_VCOCALIB_HSCNT_MASK\t\t\t0xff\n-\n-#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET\t\t\t26\n-#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET\t\t\t27\n-#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET\t\t\t28\n-\n-#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK\t\t0x00000020\n+#include \"../../../../../drivers/clk/altera/clk-s10.h\"\n \n #endif /* _CLOCK_MANAGER_S10_ */\ndiff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c\nindex 418d7dfb572..6d7128c77be 100644\n--- a/arch/arm/mach-socfpga/misc.c\n+++ b/arch/arm/mach-socfpga/misc.c\n@@ -276,7 +276,8 @@ void socfpga_get_managers_addr(void)\n \t\t\t\t\t &socfpga_clkmgr_base);\n \telse if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) &&\n \t\t !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) &&\n-\t\t !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5))\n+\t\t !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) &&\n+\t\t !IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10))\n \t\tret = socfpga_get_base_addr(\"altr,clk-mgr\",\n \t\t\t\t\t &socfpga_clkmgr_base);\n \ndiff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c\nindex b05bec2cbc1..ace029557f3 100644\n--- a/arch/arm/mach-socfpga/spl_s10.c\n+++ b/arch/arm/mach-socfpga/spl_s10.c\n@@ -37,7 +37,6 @@ u32 reset_flag(void)\n \n void board_init_f(ulong dummy)\n {\n-\tconst struct cm_config *cm_default_cfg = cm_get_default_config();\n \tint ret;\n \tstruct udevice *dev;\n \n@@ -75,7 +74,11 @@ void board_init_f(ulong dummy)\n \tsysmgr_pinmux_init();\n \n \t/* configuring the HPS clocks */\n-\tcm_basic_init(cm_default_cfg);\n+\tret = uclass_get_device(UCLASS_CLK, 0, &dev);\n+\tif (ret) {\n+\t\tdebug(\"Clock init failed: %d\\n\", ret);\n+\t\thang();\n+\t}\n \n #ifdef CONFIG_DEBUG_UART\n \tsocfpga_per_reset(SOCFPGA_RESET(UART0), 0);\ndiff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile\nindex 693446b3d89..e961d059820 100644\n--- a/drivers/clk/altera/Makefile\n+++ b/drivers/clk/altera/Makefile\n@@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o\n obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o\n obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o\n obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o\n+obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += clk-s10.o\ndiff --git a/drivers/clk/altera/clk-s10.c b/drivers/clk/altera/clk-s10.c\nnew file mode 100644\nindex 00000000000..73c9b3556a0\n--- /dev/null\n+++ b/drivers/clk/altera/clk-s10.c\n@@ -0,0 +1,591 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2026 Altera Corporation <www.altera.com>\n+ *\n+ */\n+\n+#include <log.h>\n+#include <wait_bit.h>\n+#include <asm/io.h>\n+#include <asm/system.h>\n+#include <clk-uclass.h>\n+#include <dm.h>\n+#include <dm/lists.h>\n+#include <dm/util.h>\n+#include <dt-bindings/clock/stratix10-clock.h>\n+#include <linux/bitfield.h>\n+#include <linux/bitops.h>\n+#include <asm/arch/clock_manager.h>\n+\n+struct socfpga_clk_plat {\n+\tvoid __iomem *regs;\n+\tint pllgrp;\n+\tint bitmask;\n+};\n+\n+/*\n+ * function to write the bypass register which requires a poll of the\n+ * busy bit\n+ */\n+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)\n+{\n+\tvoid __iomem *base = plat->regs;\n+\n+\tCM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);\n+\n+\twait_for_bit_le32(base + CLKMGR_STAT,\n+\t\t\t CLKMGR_STAT_BUSY, false, 20000, false);\n+}\n+\n+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)\n+{\n+\tvoid __iomem *base = plat->regs;\n+\n+\tCM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);\n+\n+\twait_for_bit_le32(base + CLKMGR_STAT,\n+\t\t\t CLKMGR_STAT_BUSY, false, 20000, false);\n+}\n+\n+/* function to write the ctrl register which requires a poll of the busy bit */\n+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)\n+{\n+\tvoid __iomem *base = plat->regs;\n+\n+\tCM_REG_WRITEL(plat, val, CLKMGR_CTRL);\n+\n+\twait_for_bit_le32(base + CLKMGR_STAT,\n+\t\t\t CLKMGR_STAT_BUSY, false, 20000, false);\n+}\n+\n+/*\n+ * Setup clocks while making no assumptions about previous state of the clocks.\n+ */\n+static void clk_basic_init(struct udevice *dev,\n+\t\t\t const struct cm_config * const cfg)\n+{\n+\tstruct socfpga_clk_plat *plat = dev_get_plat(dev);\n+\tu32 mdiv, refclkdiv, mscnt, hscnt, vcocalib;\n+\tuintptr_t base_addr = (uintptr_t)plat->regs;\n+\n+\tif (!cfg)\n+\t\treturn;\n+\n+\t/* Put all plls in bypass */\n+\tclk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);\n+\tclk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);\n+\n+\t/* setup main PLL dividers where calculate the vcocalib value */\n+\tmdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n+\t\tCLKMGR_FDBCK_MDIV_MASK;\n+\trefclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\tmscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;\n+\thscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -\n+\t\tCLKMGR_HSCNT_CONST;\n+\tvcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n+\t\t ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n+\t\t CLKMGR_VCOCALIB_MSCNT_OFFSET);\n+\n+\twritel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n+\t\t~CLKMGR_PLLGLOB_RST_MASK),\n+\t\tbase_addr + CLKMGR_MAINPLL_PLLGLOB);\n+\twritel(cfg->main_pll_fdbck,\n+\t base_addr + CLKMGR_MAINPLL_FDBCK);\n+\twritel(vcocalib,\n+\t base_addr + CLKMGR_MAINPLL_VCOCALIB);\n+\twritel(cfg->main_pll_pllc0,\n+\t base_addr + CLKMGR_MAINPLL_PLLC0);\n+\twritel(cfg->main_pll_pllc1,\n+\t base_addr + CLKMGR_MAINPLL_PLLC1);\n+\twritel(cfg->main_pll_nocdiv,\n+\t base_addr + CLKMGR_MAINPLL_NOCDIV);\n+\n+\t/* setup peripheral PLL dividers */\n+\t/* calculate the vcocalib value */\n+\tmdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) &\n+\t\tCLKMGR_FDBCK_MDIV_MASK;\n+\trefclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\tmscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv;\n+\thscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv -\n+\t\tCLKMGR_HSCNT_CONST;\n+\tvcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |\n+\t\t ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<\n+\t\t CLKMGR_VCOCALIB_MSCNT_OFFSET);\n+\n+\twritel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &\n+\t\t~CLKMGR_PLLGLOB_RST_MASK),\n+\t\tbase_addr + CLKMGR_PERPLL_PLLGLOB);\n+\twritel(cfg->per_pll_fdbck,\n+\t base_addr + CLKMGR_PERPLL_FDBCK);\n+\twritel(vcocalib,\n+\t base_addr + CLKMGR_PERPLL_VCOCALIB);\n+\twritel(cfg->per_pll_pllc0,\n+\t base_addr + CLKMGR_PERPLL_PLLC0);\n+\twritel(cfg->per_pll_pllc1,\n+\t base_addr + CLKMGR_PERPLL_PLLC1);\n+\twritel(cfg->per_pll_emacctl,\n+\t base_addr + CLKMGR_PERPLL_EMACCTL);\n+\twritel(cfg->per_pll_gpiodiv,\n+\t base_addr + CLKMGR_PERPLL_GPIODIV);\n+\n+\t/* Take both PLL out of reset and power up */\n+\tsetbits_le32(base_addr + CLKMGR_MAINPLL_PLLGLOB,\n+\t\t CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n+\tsetbits_le32(base_addr + CLKMGR_PERPLL_PLLGLOB,\n+\t\t CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);\n+\n+\twait_for_bit_le32((const void *)(base_addr + CLKMGR_STAT),\n+\t\t\t CLKMGR_STAT_ALLPLL_LOCKED_MASK, true, 20000, false);\n+\n+\t/*\n+\t * Dividers for C2 to C9 only init after PLLs are lock. As dividers\n+\t * only take effect upon value change, we shall set a maximum value as\n+\t * default value.\n+\t */\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_MPUCLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_NOCCLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR2CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR3CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR4CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR5CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR6CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR7CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR8CLK);\n+\twritel(0xff, base_addr + CLKMGR_MAINPLL_CNTR9CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR2CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR3CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR4CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR5CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR6CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR7CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR8CLK);\n+\twritel(0xff, base_addr + CLKMGR_PERPLL_CNTR9CLK);\n+\n+\twritel(cfg->main_pll_mpuclk,\n+\t base_addr + CLKMGR_MAINPLL_MPUCLK);\n+\twritel(cfg->main_pll_nocclk,\n+\t base_addr + CLKMGR_MAINPLL_NOCCLK);\n+\twritel(cfg->main_pll_cntr2clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR2CLK);\n+\twritel(cfg->main_pll_cntr3clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR3CLK);\n+\twritel(cfg->main_pll_cntr4clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR4CLK);\n+\twritel(cfg->main_pll_cntr5clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR5CLK);\n+\twritel(cfg->main_pll_cntr6clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR6CLK);\n+\twritel(cfg->main_pll_cntr7clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR7CLK);\n+\twritel(cfg->main_pll_cntr8clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR8CLK);\n+\twritel(cfg->main_pll_cntr9clk,\n+\t base_addr + CLKMGR_MAINPLL_CNTR9CLK);\n+\twritel(cfg->per_pll_cntr2clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR2CLK);\n+\twritel(cfg->per_pll_cntr3clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR3CLK);\n+\twritel(cfg->per_pll_cntr4clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR4CLK);\n+\twritel(cfg->per_pll_cntr5clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR5CLK);\n+\twritel(cfg->per_pll_cntr6clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR6CLK);\n+\twritel(cfg->per_pll_cntr7clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR7CLK);\n+\twritel(cfg->per_pll_cntr8clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR8CLK);\n+\twritel(cfg->per_pll_cntr9clk,\n+\t base_addr + CLKMGR_PERPLL_CNTR9CLK);\n+\n+\t/* Take all PLLs out of bypass */\n+\tclk_write_bypass_mainpll(plat, 0);\n+\tclk_write_bypass_perpll(plat, 0);\n+\n+\t/* clear safe mode / out of boot mode */\n+\tclk_write_ctrl(plat, readl(base_addr + CLKMGR_CTRL) &\n+\t\t ~(CLKMGR_CTRL_SAFEMODE));\n+\n+\t/* Now ungate non-hw-managed clocks */\n+\twritel(~0, base_addr + CLKMGR_MAINPLL_EN);\n+\twritel(~0, base_addr + CLKMGR_PERPLL_EN);\n+\n+\t/* Clear the loss of lock bits (write 1 to clear) */\n+\twritel(CLKMGR_INTER_PERPLLLOST_MASK |\n+\t\t CLKMGR_INTER_MAINPLLLOST_MASK,\n+\t\t base_addr + CLKMGR_INTRCLR);\n+}\n+\n+static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat,\n+\t\t\t u32 pllglob_reg, u32 fdbck_reg)\n+{\n+\t u64 fref, refdiv, mdiv, reg, vco;\n+\n+\treg = CM_REG_READL(plat, pllglob_reg);\n+\n+\tfref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &\n+\t\tCLKMGR_PLLGLOB_VCO_PSRC_MASK;\n+\n+\tswitch (fref) {\n+\tcase CLKMGR_VCO_PSRC_EOSC1:\n+\t\tfref = cm_get_osc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_VCO_PSRC_INTOSC:\n+\t\tfref = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_VCO_PSRC_F2S:\n+\t\tfref = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\t}\n+\n+\trefdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &\n+\t\t CLKMGR_PLLGLOB_REFCLKDIV_MASK;\n+\n+\treg = CM_REG_READL(plat, fdbck_reg);\n+\tmdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;\n+\n+\tvco = fref / refdiv;\n+\tvco = vco * (CLKMGR_MDIV_CONST + mdiv);\n+\n+\treturn vco;\n+}\n+\n+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\treturn clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,\n+\t\t\t\t CLKMGR_MAINPLL_FDBCK);\n+}\n+\n+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\treturn clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,\n+\t\t\t\t CLKMGR_PERPLL_FDBCK);\n+}\n+\n+static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg)\n+{\n+\tu32 clksrc = CM_REG_READL(plat, reg);\n+\n+\treturn (clksrc >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;\n+}\n+\n+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\tu64 clock;\n+\tu32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_MPUCLK);\n+\n+\tswitch (clklsrc) {\n+\tcase CLKMGR_CLKSRC_MAIN:\n+\t\tclock = clk_get_main_vco_clk_hz(plat);\n+\t\tclock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC0) &\n+\t\t\t CLKMGR_PLLC0_DIV_MASK);\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_PER:\n+\t\tclock = clk_get_per_vco_clk_hz(plat);\n+\t\tclock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC0) &\n+\t\t\t CLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_OSC1:\n+\t\tclock = cm_get_osc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_INTOSC:\n+\t\tclock = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_FPGA:\n+\t\tclock = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\tclock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &\n+\t\t CLKMGR_CLKCNT_MSK);\n+\n+\treturn clock;\n+}\n+\n+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\tu64 clock;\n+\tu32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_MAINPLL_NOCCLK);\n+\n+\tswitch (clklsrc) {\n+\tcase CLKMGR_CLKSRC_MAIN:\n+\t\tclock = clk_get_main_vco_clk_hz(plat);\n+\t\tclock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC1) &\n+\t\t\t CLKMGR_PLLC0_DIV_MASK);\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_PER:\n+\t\tclock = clk_get_per_vco_clk_hz(plat);\n+\t\tclock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC1) &\n+\t\t\t CLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_OSC1:\n+\t\tclock = cm_get_osc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_INTOSC:\n+\t\tclock = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_FPGA:\n+\t\tclock = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\tclock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_NOCCLK) &\n+\t\t CLKMGR_CLKCNT_MSK);\n+\n+\treturn clock;\n+}\n+\n+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\tu32 clock;\n+\tu32 clklsrc = clk_get_5_1_clk_src(plat, CLKMGR_PERPLL_CNTR6CLK);\n+\n+\tswitch (clklsrc) {\n+\tcase CLKMGR_CLKSRC_MAIN:\n+\t\tclock = clk_get_l3_main_clk_hz(plat);\n+\t\tclock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_CNTR6CLK) & CLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_PER:\n+\t\tclock = clk_get_l3_main_clk_hz(plat);\n+\t\tclock /= 1 + (CM_REG_READL(plat, CLKMGR_PERPLL_CNTR6CLK) & CLKMGR_CLKCNT_MSK);\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_OSC1:\n+\t\tclock = cm_get_osc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_INTOSC:\n+\t\tclock = cm_get_intosc_clk_hz();\n+\t\tbreak;\n+\tcase CLKMGR_CLKSRC_FPGA:\n+\t\tclock = cm_get_fpga_clk_hz();\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\treturn clock / 4;\n+}\n+\n+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\tu64 clock = clk_get_l3_main_clk_hz(plat);\n+\n+\tclock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>\n+\t\t CLKMGR_NOCDIV_L4SPCLK_OFFSET) &\n+\t\t CLKMGR_CLKCNT_MSK);\n+\n+\treturn clock;\n+}\n+\n+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)\n+{\n+\tif (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)\n+\t\treturn clk_get_l3_main_clk_hz(plat) / 2;\n+\n+\treturn clk_get_l3_main_clk_hz(plat) / 4;\n+}\n+\n+static ulong socfpga_clk_get_rate(struct clk *clk)\n+{\n+\tstruct socfpga_clk_plat *plat = dev_get_plat(clk->dev);\n+\n+\tswitch (clk->id) {\n+\tcase STRATIX10_MPU_CLK:\n+\t\treturn clk_get_mpu_clk_hz(plat);\n+\tcase STRATIX10_NOC_CLK:\n+\t\treturn clk_get_l3_main_clk_hz(plat);\n+\tcase STRATIX10_MAIN_PLL_CLK:\n+\t\treturn clk_get_main_vco_clk_hz(plat);\n+\tcase STRATIX10_PERIPH_PLL_CLK:\n+\t\treturn clk_get_per_vco_clk_hz(plat);\n+\tcase STRATIX10_OSC1:\n+\t\treturn cm_get_osc_clk_hz();\n+\tcase STRATIX10_SDMMC_CLK:\n+\t\treturn clk_get_sdmmc_clk_hz(plat);\n+\tcase STRATIX10_L4_SP_CLK:\n+\t\treturn clk_get_l4_sp_clk_hz(plat);\n+\tcase STRATIX10_L4_SYS_FREE_CLK:\n+\t\treturn clk_get_l4_sys_free_clk_hz(plat);\n+\tdefault:\n+\t\treturn -ENXIO;\n+\t}\n+}\n+\n+static int bitmask_from_clk_id(struct clk *clk)\n+{\n+\tstruct socfpga_clk_plat *plat = dev_get_plat(clk->dev);\n+\n+\tswitch (clk->id) {\n+\tcase STRATIX10_MPU_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_L4_MAIN_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_L4_MP_CLK:\n+\tcase STRATIX10_NAND_X_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_L4_SP_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_CS_AT_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_CS_TRACE_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_CS_PDBG_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_CSCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_CS_TIMER_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_S2F_USER0_CLK:\n+\t\tplat->pllgrp = CLKMGR_MAINPLL_EN;\n+\t\tplat->bitmask = CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_EMAC0_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_EMAC1_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_EMAC2_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_EMAC_PTP_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_GPIO_DB_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_SDMMC_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_S2F_USER1_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_PSI_REF_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_USB_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_USBCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_SPI_M_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_NAND_CLK:\n+\t\tplat->pllgrp = CLKMGR_PERPLL_EN;\n+\t\tplat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;\n+\t\tbreak;\n+\tcase STRATIX10_L4_SYS_FREE_CLK:\n+\t\treturn -EOPNOTSUPP;\n+\tdefault:\n+\t\treturn -ENXIO;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int socfpga_clk_enable(struct clk *clk)\n+{\n+\tstruct socfpga_clk_plat *plat = dev_get_plat(clk->dev);\n+\tuintptr_t base_addr = (uintptr_t)plat->regs;\n+\tint ret;\n+\n+\tret = bitmask_from_clk_id(clk);\n+\tif (ret == -EOPNOTSUPP)\n+\t\treturn 0;\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tsetbits_le32(base_addr + plat->pllgrp, plat->bitmask);\n+\n+\treturn 0;\n+}\n+\n+static int socfpga_clk_disable(struct clk *clk)\n+{\n+\tstruct socfpga_clk_plat *plat = dev_get_plat(clk->dev);\n+\tuintptr_t base_addr = (uintptr_t)plat->regs;\n+\tint ret;\n+\n+\tret = bitmask_from_clk_id(clk);\n+\tif (ret == -EOPNOTSUPP)\n+\t\treturn 0;\n+\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tclrbits_le32(base_addr + plat->pllgrp, plat->bitmask);\n+\n+\treturn 0;\n+}\n+\n+static int socfpga_clk_probe(struct udevice *dev)\n+{\n+\tconst struct cm_config *cm_default_cfg = cm_get_default_config();\n+\n+\tclk_basic_init(dev, cm_default_cfg);\n+\n+\treturn 0;\n+}\n+\n+static int socfpga_clk_of_to_plat(struct udevice *dev)\n+{\n+\tstruct socfpga_clk_plat *plat = dev_get_plat(dev);\n+\tfdt_addr_t addr;\n+\n+\taddr = dev_read_addr(dev);\n+\tif (addr == FDT_ADDR_T_NONE)\n+\t\treturn -EINVAL;\n+\tplat->regs = (void __iomem *)addr;\n+\n+\treturn 0;\n+}\n+\n+static struct clk_ops socfpga_clk_ops = {\n+\t.enable\t\t= socfpga_clk_enable,\n+\t.disable\t= socfpga_clk_disable,\n+\t.get_rate\t= socfpga_clk_get_rate,\n+};\n+\n+static const struct udevice_id socfpga_clk_match[] = {\n+\t{ .compatible = \"intel,stratix10-clkmgr\" },\n+\t{}\n+};\n+\n+U_BOOT_DRIVER(socfpga_s10_clk) = {\n+\t.name\t\t= \"clk-s10\",\n+\t.id\t\t= UCLASS_CLK,\n+\t.of_match\t= socfpga_clk_match,\n+\t.ops\t\t= &socfpga_clk_ops,\n+\t.probe\t\t= socfpga_clk_probe,\n+\t.of_to_plat = socfpga_clk_of_to_plat,\n+\t.plat_auto\t= sizeof(struct socfpga_clk_plat),\n+};\ndiff --git a/drivers/clk/altera/clk-s10.h b/drivers/clk/altera/clk-s10.h\nnew file mode 100644\nindex 00000000000..f5be1e68500\n--- /dev/null\n+++ b/drivers/clk/altera/clk-s10.h\n@@ -0,0 +1,202 @@\n+/* SPDX-License-Identifier: GPL-2.0\n+ *\n+ * Copyright (C) 2026 Altera Corporation <www.altera.com>\n+ *\n+ */\n+\n+#ifndef\t_CLK_S10_\n+#define\t_CLK_S10_\n+\n+#ifndef __ASSEMBLY__\n+#include <linux/bitops.h>\n+#endif\n+\n+#define COUNTER_FREQUENCY_REAL\t400000000\n+\n+#define CM_REG_READL(plat, reg)\t\t\t\t\\\n+\treadl((plat)->regs + (reg))\n+\n+#define CM_REG_WRITEL(plat, data, reg)\t\t\t\\\n+\twritel(data, (plat)->regs + (reg))\n+\n+#define CM_REG_CLRBITS(plat, reg, clear)\t\t\\\n+\tclrbits_le32((plat)->regs + (reg), (clear))\n+\n+#define CM_REG_SETBITS(plat, reg, set)\t\t\t\\\n+\tsetbits_le32((plat)->regs + (reg), (set))\n+\n+struct cm_config {\n+\t/* main group */\n+\tu32 main_pll_mpuclk;\n+\tu32 main_pll_nocclk;\n+\tu32 main_pll_cntr2clk;\n+\tu32 main_pll_cntr3clk;\n+\tu32 main_pll_cntr4clk;\n+\tu32 main_pll_cntr5clk;\n+\tu32 main_pll_cntr6clk;\n+\tu32 main_pll_cntr7clk;\n+\tu32 main_pll_cntr8clk;\n+\tu32 main_pll_cntr9clk;\n+\tu32 main_pll_nocdiv;\n+\tu32 main_pll_pllglob;\n+\tu32 main_pll_fdbck;\n+\tu32 main_pll_pllc0;\n+\tu32 main_pll_pllc1;\n+\tu32 spare;\n+\n+\t/* peripheral group */\n+\tu32 per_pll_cntr2clk;\n+\tu32 per_pll_cntr3clk;\n+\tu32 per_pll_cntr4clk;\n+\tu32 per_pll_cntr5clk;\n+\tu32 per_pll_cntr6clk;\n+\tu32 per_pll_cntr7clk;\n+\tu32 per_pll_cntr8clk;\n+\tu32 per_pll_cntr9clk;\n+\tu32 per_pll_emacctl;\n+\tu32 per_pll_gpiodiv;\n+\tu32 per_pll_pllglob;\n+\tu32 per_pll_fdbck;\n+\tu32 per_pll_pllc0;\n+\tu32 per_pll_pllc1;\n+\n+\t/* incoming clock */\n+\tu32 hps_osc_clk_hz;\n+\tu32 fpga_clk_hz;\n+};\n+\n+/* Control status */\n+#define CLKMGR_CTRL\t\t\t\t\t0x00\n+#define CLKMGR_STAT\t\t\t\t\t0x04\n+#define CLKMGR_INTRCLR\t\t\t\t0x14\n+/* Mainpll group */\n+#define CLKMGR_MAINPLL_EN\t\t\t\t0x30\n+#define CLKMGR_MAINPLL_BYPASS\t\t\t0x3c\n+#define CLKMGR_MAINPLL_MPUCLK\t\t\t0x48\n+#define CLKMGR_MAINPLL_NOCCLK\t\t\t0x4c\n+#define CLKMGR_MAINPLL_CNTR2CLK\t\t\t0x50\n+#define CLKMGR_MAINPLL_CNTR3CLK\t\t\t0x54\n+#define CLKMGR_MAINPLL_CNTR4CLK\t\t\t0x58\n+#define CLKMGR_MAINPLL_CNTR5CLK\t\t\t0x5c\n+#define CLKMGR_MAINPLL_CNTR6CLK\t\t\t0x60\n+#define CLKMGR_MAINPLL_CNTR7CLK\t\t\t0x64\n+#define CLKMGR_MAINPLL_CNTR8CLK\t\t\t0x68\n+#define CLKMGR_MAINPLL_CNTR9CLK\t\t\t0x6c\n+#define CLKMGR_MAINPLL_NOCDIV\t\t\t0x70\n+#define CLKMGR_MAINPLL_PLLGLOB\t\t\t0x74\n+#define CLKMGR_MAINPLL_FDBCK\t\t\t0x78\n+#define CLKMGR_MAINPLL_MEMSTAT\t\t\t0x80\n+#define CLKMGR_MAINPLL_PLLC0\t\t\t0x84\n+#define CLKMGR_MAINPLL_PLLC1\t\t\t0x88\n+#define CLKMGR_MAINPLL_VCOCALIB\t\t\t0x8c\n+/* Periphpll group */\n+#define CLKMGR_PERPLL_EN\t\t\t\t0xa4\n+#define CLKMGR_PERPLL_BYPASS\t\t\t0xb0\n+#define CLKMGR_PERPLL_CNTR2CLK\t\t\t0xbc\n+#define CLKMGR_PERPLL_CNTR3CLK\t\t\t0xc0\n+#define CLKMGR_PERPLL_CNTR4CLK\t\t\t0xc4\n+#define CLKMGR_PERPLL_CNTR5CLK\t\t\t0xc8\n+#define CLKMGR_PERPLL_CNTR6CLK\t\t\t0xcc\n+#define CLKMGR_PERPLL_CNTR7CLK\t\t\t0xd0\n+#define CLKMGR_PERPLL_CNTR8CLK\t\t\t0xd4\n+#define CLKMGR_PERPLL_CNTR9CLK\t\t\t0xd8\n+#define CLKMGR_PERPLL_EMACCTL\t\t\t0xdc\n+#define CLKMGR_PERPLL_GPIODIV\t\t\t0xe0\n+#define CLKMGR_PERPLL_PLLGLOB\t\t\t0xe4\n+#define CLKMGR_PERPLL_FDBCK\t\t\t\t0xe8\n+#define CLKMGR_PERPLL_MEMSTAT\t\t\t0xf0\n+#define CLKMGR_PERPLL_PLLC0\t\t\t\t0xf4\n+#define CLKMGR_PERPLL_PLLC1\t\t\t\t0xf8\n+#define CLKMGR_PERPLL_VCOCALIB\t\t\t0xfc\n+\n+#define CLKMGR_CTRL_SAFEMODE\t\t\t\tBIT(0)\n+#define CLKMGR_BYPASS_MAINPLL_ALL\t\t\t0x00000007\n+#define CLKMGR_BYPASS_PERPLL_ALL\t\t\t0x0000007f\n+\n+#define CLKMGR_INTER_MAINPLLLOCKED_MASK\t\t\t0x00000001\n+#define CLKMGR_INTER_PERPLLLOCKED_MASK\t\t\t0x00000002\n+#define CLKMGR_INTER_MAINPLLLOST_MASK\t\t\t0x00000004\n+#define CLKMGR_INTER_PERPLLLOST_MASK\t\t\t0x00000008\n+#define CLKMGR_STAT_BUSY\t\t\t\tBIT(0)\n+#define CLKMGR_STAT_MAINPLL_LOCKED\t\t\tBIT(8)\n+#define CLKMGR_STAT_PERPLL_LOCKED\t\t\tBIT(9)\n+#define CLKMGR_STAT_BOOTMODE\t\t\tBIT(16)\n+\n+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK\t\t\\\n+\t(CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)\n+\n+#define CLKMGR_PLLGLOB_PD_MASK\t\t\t\t0x00000001\n+#define CLKMGR_PLLGLOB_RST_MASK\t\t\t\t0x00000002\n+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK\t\t\t0x3\n+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET\t\t\t16\n+#define CLKMGR_VCO_PSRC_EOSC1\t\t\t\t0\n+#define CLKMGR_VCO_PSRC_INTOSC\t\t\t\t1\n+#define CLKMGR_VCO_PSRC_F2S\t\t\t\t2\n+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK\t\t\t0x3f\n+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET\t\t\t8\n+\n+#define CLKMGR_CLKSRC_MASK\t\t\t\t0x7\n+#define CLKMGR_CLKSRC_OFFSET\t\t\t\t16\n+#define CLKMGR_CLKSRC_MAIN\t\t\t\t0\n+#define CLKMGR_CLKSRC_PER\t\t\t\t1\n+#define CLKMGR_CLKSRC_OSC1\t\t\t\t2\n+#define CLKMGR_CLKSRC_INTOSC\t\t\t\t3\n+#define CLKMGR_CLKSRC_FPGA\t\t\t\t4\n+#define CLKMGR_CLKCNT_MSK\t\t\t\t0x7ff\n+\n+#define CLKMGR_FDBCK_MDIV_MASK\t\t\t\t0xff\n+#define CLKMGR_FDBCK_MDIV_OFFSET\t\t\t24\n+\n+#define CLKMGR_PLLC0_DIV_MASK\t\t\t\t0xff\n+#define CLKMGR_PLLC1_DIV_MASK\t\t\t\t0xff\n+#define CLKMGR_PLLC0_EN_OFFSET\t\t\t\t27\n+#define CLKMGR_PLLC1_EN_OFFSET\t\t\t\t24\n+\n+#define CLKMGR_NOCDIV_L4MAIN_OFFSET\t\t\t0\n+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET\t\t\t8\n+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET\t\t\t16\n+#define CLKMGR_NOCDIV_CSATCLK_OFFSET\t\t\t24\n+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET\t\t\t26\n+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET\t\t\t28\n+\n+#define CLKMGR_NOCDIV_L4SPCLK_MASK\t\t\t0x3\n+#define CLKMGR_NOCDIV_DIV1\t\t\t\t0\n+#define CLKMGR_NOCDIV_DIV2\t\t\t\t1\n+#define CLKMGR_NOCDIV_DIV4\t\t\t\t2\n+#define CLKMGR_NOCDIV_DIV8\t\t\t\t3\n+#define CLKMGR_CSPDBGCLK_DIV1\t\t\t\t0\n+#define CLKMGR_CSPDBGCLK_DIV4\t\t\t\t1\n+\n+#define CLKMGR_MSCNT_CONST\t\t\t\t200\n+#define CLKMGR_MDIV_CONST\t\t\t\t6\n+#define CLKMGR_HSCNT_CONST\t\t\t\t9\n+\n+#define CLKMGR_VCOCALIB_MSCNT_MASK\t\t\t0xff\n+#define CLKMGR_VCOCALIB_MSCNT_OFFSET\t\t\t9\n+#define CLKMGR_VCOCALIB_HSCNT_MASK\t\t\t0xff\n+\n+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET\t\t\t26\n+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET\t\t\t27\n+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET\t\t\t28\n+\n+#define CLKMGR_MAINPLLGRP_EN_MPUCLK_MASK\t\tBIT(0)\n+#define CLKMGR_MAINPLLGRP_EN_L4MAINCLK_MASK\t\tBIT(1)\n+#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK\t\tBIT(2)\n+#define CLKMGR_MAINPLLGRP_EN_L4SPCLK_MASK\t\tBIT(3)\n+#define CLKMGR_MAINPLLGRP_EN_CSCLK_MASK\t\tBIT(4)\n+#define CLKMGR_MAINPLLGRP_EN_CSTIMERCLK_MASK\t\tBIT(5)\n+#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK\t\tBIT(6)\n+\n+#define CLKMGR_PERPLLGRP_EN_EMAC0CLK_MASK\t\tBIT(0)\n+#define CLKMGR_PERPLLGRP_EN_EMAC1CLK_MASK\t\tBIT(1)\n+#define CLKMGR_PERPLLGRP_EN_EMAC2CLK_MASK\t\tBIT(2)\n+#define CLKMGR_PERPLLGRP_EN_EMACPTPCLK_MASK\t\tBIT(3)\n+#define CLKMGR_PERPLLGRP_EN_GPIODBCLK_MASK\t\tBIT(4)\n+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK\t\tBIT(5)\n+#define CLKMGR_PERPLLGRP_EN_S2FUSER1CLK_MASK\t\tBIT(6)\n+#define CLKMGR_PERPLLGRP_EN_PSIREFCLK_MASK\t\tBIT(7)\n+#define CLKMGR_PERPLLGRP_EN_USBCLK_MASK\t\tBIT(8)\n+#define CLKMGR_PERPLLGRP_EN_SPIMCLK_MASK\t\tBIT(9)\n+#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK\t\tBIT(10)\n+\n+#endif /* _CLK_S10_ */\n", "prefixes": [ "v1", "7/9" ] }