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GET /api/patches/2219283/?format=api
{ "id": 2219283, "url": "http://patchwork.ozlabs.org/api/patches/2219283/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260402173258.24387-3-kevinstefanov15@gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260402173258.24387-3-kevinstefanov15@gmail.com>", "list_archive_url": null, "date": "2026-04-02T17:33:00", "name": "Refactor loops with TEST_HARD_REG_BIT to use EXECUTE_IF_SET_IN_HARD_REG_SET", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "43941aa100ea54107ca25250bb29530f4fc6f2a2", "submitter": { "id": 92714, "url": "http://patchwork.ozlabs.org/api/people/92714/?format=api", "name": "Kevin Stefanov", "email": "kevinstefanov15@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260402173258.24387-3-kevinstefanov15@gmail.com/mbox/", "series": [ { "id": 498535, "url": "http://patchwork.ozlabs.org/api/series/498535/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=498535", "date": "2026-04-02T17:33:00", "name": "Refactor loops with TEST_HARD_REG_BIT to use EXECUTE_IF_SET_IN_HARD_REG_SET", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498535/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219283/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219283/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=GbrbcLFG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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<i> < FIRST_PSEUDO_REGISTER; <i>++)\n if (TEST_HARD_REG_BIT (<set>, <i>))\n <body that doesn't change i or set>\n\nand carries out the necessary refactoring to rewrite them as:\n\n hard_reg_set_iterator hrsi; [...]\n EXECUTE_IF_SET_IN_HARD_REG_SET (<set>, 0, <i>, hrsi)\n <body that doesn't change i or set>\n\nin loops where expressing <set> does not involve <i>.\n\ngcc/\n\t* config/m32c/m32c.cc (m32c_class_max_nregs): Improved 1 loop.\n\t* config/m68k/m68k.cc (m68k_conditional_register_usage): Improved 1 loop.\n\t(m68k_zero_call_used_regs): Improved 1 loop.\n\t* config/pdp11/pdp11.cc (pdp11_conditional_register_usage): Improved 1 loop.\n\t* ira-int.h (ira_hard_reg_set_intersection_p): Improved 1 loop.\n\t* ira-lives.cc (process_bb_node_lives): Improved 1 loop.\n\t* ira.cc (setup_class_hard_regs): Improved 1 loop.\n\t(update_equiv_regs_prescan): Improved 1 loop.\n\t(build_insn_chain): Improved 1 loop.\n\t* lra_eliminations.cc (spill_pseudos): Improved 1 loop.\n\t* optabs.cc (expand_asm_reg_clobber_mem_blockage): Improved 2 loops.\n\t* postreload.cc (reload_combine): Improved 3 loops.\n\t* reginfo.cc (init_reg_sets_1): Improved 1 loop.\n\t* regrename.cc (init_rename_info): Improved 1 loop.\n\t* reload1.cc (maybe_fix_stack_asms): Improved 1 loop.\n\t(update_eliminables): Improved 1 loop.\n\t* rtl-ssa/insns.cc (function_info::record_call_clobbers): Improved 1 loop.\n\t* sched-deps.cc (sched_analyze_insn): Fix indentation.\n\t* sel-sched-dump.cc (dump_insn_vector): Improved 1 loop.\n\nSigned-off-by: Kevin Stefanov <kevinstefanov15@gmail.com>\n---\nI have gone over each occurence under gcc/ returned by:\ngrep -r -C 5 \"TEST_HARD_REG_BIT\" | grep --color=always -E \"for|$\"\nto get all hits for TEST_HARD_REG_BIT, with any occurences of \"for\"\nin the surrounding context lines being highlighted in red, so I can\nskip any occurences that are not part of a for-loop to begin with.\nThese are all the for loops I found that matched the pattern required\nfor this refactoring. I had sent a first small patch with a single\nloop refactored a month ago on the file we talked about on bugzilla.\n(sched-deps.cc) and I never received any feedback on that so, just a\nlight reminder for that too. I do not have write access yet so when\ncode review passes and we're good to go, I'd appreciate if someone could\ndo that part for me. Let me know if I have miscellaneous things like\nindentation or changelog style to fix. One last thing, I forgot to\nadd a [1/X] numbering marker on my first commit from a month ago,\nso what is the recommended way for me to fix that, given that this\ncommit here is technically [2/X] now?\nHere is my output from comparing the test results of this change and\nthat of a pristine GCC build:\nTests that now work, but didn't before (6 tests):\ng++: g++.dg/gomp/deprecate-1.C -std=c++20 expected multiline pattern lines 119-121\ng++: g++.dg/gomp/deprecate-1.C -std=c++20 (test for excess errors)\ng++: g++.dg/gomp/deprecate-1.C -std=c++26 expected multiline pattern lines 119-121\ng++: g++.dg/gomp/deprecate-1.C -std=c++26 (test for excess errors)\ng++: g++.dg/gomp/deprecate-1.C -std=c++98 expected multiline pattern lines 119-121\ng++: g++.dg/gomp/deprecate-1.C -std=c++98 (test for excess errors)\nNew tests that PASS (1 tests):\ng++: g++.dg/modules/compile-std1.C module-cmi <bits/stdc++.h> (gcm.cache/home/hypervisor123/tmp/repos/gcc/objdir-contrib/x86_64-pc-linux-gnu/libstdc++-v3/include/x86_64-pc-linux-gnu/bits/stdc++.h.gcm)\nOld tests that passed, that have disappeared (1 tests): (Eeek!)\ng++: g++.dg/modules/compile-std1.C module-cmi <bits/stdc++.h> (gcm.cache/home/hypervisor123/tmp/repos/gcc/objdir/x86_64-pc-linux-gnu/libstdc++-v3/include/x86_64-pc-linux-gnu/bits/stdc++.h.gcm)\n## Differences found\n# 1 differences in 16 common sum files found\n\n gcc/config/m32c/m32c.cc | 15 +++++++------\n gcc/config/m68k/m68k.cc | 10 ++++-----\n gcc/config/pdp11/pdp11.cc | 4 ++--\n gcc/ira-int.h | 10 ++++-----\n gcc/ira-lives.cc | 9 ++++----\n gcc/ira.cc | 24 +++++++++++++-------\n gcc/lra-eliminations.cc | 8 ++++---\n gcc/optabs.cc | 21 +++++++++--------\n gcc/postreload.cc | 33 ++++++++++++++-------------\n gcc/reginfo.cc | 14 ++++++------\n gcc/regrename.cc | 20 ++++++++---------\n gcc/reload1.cc | 47 ++++++++++++++++++++-------------------\n gcc/rtl-ssa/insns.cc | 7 ++++--\n gcc/sched-deps.cc | 25 +++++++++++----------\n gcc/sel-sched-dump.cc | 12 +++++-----\n 15 files changed, 141 insertions(+), 118 deletions(-)", "diff": "diff --git a/gcc/config/m32c/m32c.cc b/gcc/config/m32c/m32c.cc\nindex b18246df05e..b0709dcca57 100644\n--- a/gcc/config/m32c/m32c.cc\n+++ b/gcc/config/m32c/m32c.cc\n@@ -793,13 +793,14 @@ m32c_class_max_nregs (reg_class_t regclass, machine_mode mode)\n int rn;\n unsigned char max = 0;\n \n- for (rn = 0; rn < FIRST_PSEUDO_REGISTER; rn++)\n- if (TEST_HARD_REG_BIT (reg_class_contents[(int) regclass], rn))\n- {\n-\tunsigned char n = m32c_hard_regno_nregs (rn, mode);\n-\tif (max < n)\n-\t max = n;\n- }\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET\n+ (reg_class_contents[(int) regclass], 0, rn, hrsi)\n+ {\n+ unsigned char n = m32c_hard_regno_nregs (rn, mode);\n+ if (max < n)\n+\tmax = n;\n+ }\n return max;\n }\n \ndiff --git a/gcc/config/m68k/m68k.cc b/gcc/config/m68k/m68k.cc\nindex 18fc2cacf43..8652ff56273 100644\n--- a/gcc/config/m68k/m68k.cc\n+++ b/gcc/config/m68k/m68k.cc\n@@ -7118,9 +7118,9 @@ m68k_conditional_register_usage (void)\n if (!TARGET_HARD_FLOAT)\n {\n x = reg_class_contents[FP_REGS];\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n- if (TEST_HARD_REG_BIT (x, i))\n-\t fixed_regs[i] = call_used_regs[i] = 1;\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (x, 0, i, hrsi)\n+\tfixed_regs[i] = call_used_regs[i] = 1;\n }\n if (flag_pic)\n fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;\n@@ -7211,8 +7211,8 @@ m68k_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)\n {\n rtx zero_fpreg = NULL_RTX;\n \n- for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)\n- if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (need_zeroed_hardregs, 0, regno, hrsi)\n {\n \trtx reg, zero;\n \ndiff --git a/gcc/config/pdp11/pdp11.cc b/gcc/config/pdp11/pdp11.cc\nindex 07800faecf8..77c5d2ccb01 100644\n--- a/gcc/config/pdp11/pdp11.cc\n+++ b/gcc/config/pdp11/pdp11.cc\n@@ -2214,8 +2214,8 @@ pdp11_conditional_register_usage (void)\n if (!TARGET_FPU)\n {\n x = reg_class_contents[FPU_REGS];\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ )\n- if (TEST_HARD_REG_BIT (x, i))\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (x, 0, i, hrsi)\n \tfixed_regs[i] = call_used_regs[i] = 1;\n }\n \ndiff --git a/gcc/ira-int.h b/gcc/ira-int.h\nindex 6726a0f4cad..3c0db7e6220 100644\n--- a/gcc/ira-int.h\n+++ b/gcc/ira-int.h\n@@ -1441,11 +1441,11 @@ ira_hard_reg_set_intersection_p (int hard_regno, machine_mode mode,\n inline int\n hard_reg_set_size (HARD_REG_SET set)\n {\n- int i, size;\n-\n- for (size = i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n- if (TEST_HARD_REG_BIT (set, i))\n- size++;\n+ int size = 0;\n+ unsigned int i;\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (set, 0, i, hrsi)\n+ size++;\n return size;\n }\n \ndiff --git a/gcc/ira-lives.cc b/gcc/ira-lives.cc\nindex 04e586343c8..1caa175f5cb 100644\n--- a/gcc/ira-lives.cc\n+++ b/gcc/ira-lives.cc\n@@ -1309,7 +1309,7 @@ static void\n process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)\n {\n int i, freq;\n- unsigned int j;\n+ unsigned int j, k;\n basic_block bb;\n rtx_insn *insn;\n bitmap_iterator bi;\n@@ -1330,12 +1330,13 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)\n sparseset_clear (objects_live);\n REG_SET_TO_HARD_REG_SET (hard_regs_live, reg_live_out);\n hard_regs_live &= ~(eliminable_regset | ira_no_alloc_regs);\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n-\tif (TEST_HARD_REG_BIT (hard_regs_live, i))\n+ hard_reg_set_iterator hrsi;\n+ k = 0;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (hard_regs_live, 0, k, hrsi)\n \t {\n \t enum reg_class aclass, pclass, cl;\n \n-\t aclass = ira_allocno_class_translate[REGNO_REG_CLASS (i)];\n+\t aclass = ira_allocno_class_translate[REGNO_REG_CLASS (k)];\n \t pclass = ira_pressure_class_translate[aclass];\n \t for (j = 0;\n \t\t (cl = ira_reg_class_super_classes[pclass][j])\ndiff --git a/gcc/ira.cc b/gcc/ira.cc\nindex d65e1b97ed8..8d08ad87474 100644\n--- a/gcc/ira.cc\n+++ b/gcc/ira.cc\n@@ -466,6 +466,7 @@ static void\n setup_class_hard_regs (void)\n {\n int cl, i, hard_regno, n;\n+ unsigned int j;\n HARD_REG_SET processed_hard_reg_set;\n \n ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);\n@@ -497,9 +498,12 @@ setup_class_hard_regs (void)\n \t }\n \t}\n ira_class_hard_regs_num[cl] = n;\n- for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n-\tif (TEST_HARD_REG_BIT (temp_hard_regset, i))\n-\t ira_non_ordered_class_hard_regs[cl][n++] = i;\n+ n = 0;\n+ j = 0;\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (temp_hard_regset, 0, j ,hrsi)\n+\tira_non_ordered_class_hard_regs[cl][n++] = j;\n+\n ira_assert (ira_class_hard_regs_num[cl] == n);\n }\n }\n@@ -3610,10 +3614,14 @@ update_equiv_regs_prescan (void)\n \t}\n \n HARD_REG_SET extra_caller_saves = callee_abis.caller_save_regs (*crtl->abi);\n+\n+ hard_reg_set_iterator hrsi;\n+ unsigned int regno = 0;\n if (!hard_reg_set_empty_p (extra_caller_saves))\n- for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)\n- if (TEST_HARD_REG_BIT (extra_caller_saves, regno))\n+ {\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (extra_caller_saves, 0, regno, hrsi)\n \tdf_set_regs_ever_live (regno, true);\n+ }\n }\n \n /* Find registers that are equivalent to a single value throughout the\n@@ -4387,9 +4395,9 @@ build_insn_chain (void)\n sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno);\n auto_bitmap live_subregs_used;\n \n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n- if (TEST_HARD_REG_BIT (eliminable_regset, i))\n- bitmap_set_bit (elim_regset, i);\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (eliminable_regset, 0, i, hrsi)\n+ bitmap_set_bit (elim_regset, i);\n FOR_EACH_BB_REVERSE_FN (bb, cfun)\n {\n bitmap_iterator bi;\ndiff --git a/gcc/lra-eliminations.cc b/gcc/lra-eliminations.cc\nindex 8e68cb70dcf..9276714687a 100644\n--- a/gcc/lra-eliminations.cc\n+++ b/gcc/lra-eliminations.cc\n@@ -1132,6 +1132,7 @@ static int\n spill_pseudos (HARD_REG_SET set, int *spilled_pseudos)\n {\n int i, n;\n+ unsigned int j;\n bitmap_head to_process;\n rtx_insn *insn;\n \n@@ -1140,9 +1141,10 @@ spill_pseudos (HARD_REG_SET set, int *spilled_pseudos)\n if (lra_dump_file != NULL)\n {\n fprintf (lra_dump_file, \"\t Spilling non-eliminable hard regs:\");\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n-\tif (TEST_HARD_REG_BIT (set, i))\n-\t fprintf (lra_dump_file, \" %d\", i);\n+ j = 0;\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (set, 0, j, hrsi)\n+\tfprintf (lra_dump_file, \" %d\", j);\n fprintf (lra_dump_file, \"\\n\");\n }\n bitmap_initialize (&to_process, ®_obstack);\ndiff --git a/gcc/optabs.cc b/gcc/optabs.cc\nindex e813cf9b215..2e1f1f9bc9c 100644\n--- a/gcc/optabs.cc\n+++ b/gcc/optabs.cc\n@@ -7508,9 +7508,11 @@ expand_asm_reg_clobber_mem_blockage (HARD_REG_SET regs)\n rtx asm_op, clob_mem;\n \n unsigned int num_of_regs = 0;\n- for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n- if (TEST_HARD_REG_BIT (regs, i))\n- num_of_regs++;\n+ unsigned int i;\n+ hard_reg_set_iterator hrsi1;\n+ i = 0;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (regs, 0, i, hrsi1)\n+ num_of_regs++;\n \n asm_op = gen_rtx_ASM_OPERANDS (VOIDmode, \"\", \"\", 0,\n \t\t\t\t rtvec_alloc (0), rtvec_alloc (0),\n@@ -7529,12 +7531,13 @@ expand_asm_reg_clobber_mem_blockage (HARD_REG_SET regs)\n if (num_of_regs > 0)\n {\n unsigned int j = 2;\n- for (unsigned int i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n-\tif (TEST_HARD_REG_BIT (regs, i))\n-\t {\n-\t RTVEC_ELT (v, j) = gen_rtx_CLOBBER (VOIDmode, regno_reg_rtx[i]);\n- \t j++;\n-\t }\n+ hard_reg_set_iterator hrsi2;\n+ i = 0;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (regs, 0, i, hrsi2)\n+\t{\n+\t RTVEC_ELT (v, j) = gen_rtx_CLOBBER (VOIDmode, regno_reg_rtx[i]);\n+\t j++;\n+\t}\n gcc_assert (j == (num_of_regs + 2));\n }\n \ndiff --git a/gcc/postreload.cc b/gcc/postreload.cc\nindex 80a65796efb..9d798880ea6 100644\n--- a/gcc/postreload.cc\n+++ b/gcc/postreload.cc\n@@ -1338,14 +1338,15 @@ reload_combine (void)\n last_index_reg = -1;\n else if (first_index_reg == -1 && last_index_reg == 0)\n {\n- for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)\n-\tif (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))\n-\t {\n-\t if (first_index_reg == -1)\n-\t first_index_reg = r;\n+ hard_reg_set_iterator hrsi1;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET\n+\t(reg_class_contents[INDEX_REG_CLASS], 0, r, hrsi1)\n+\t{\n+\t if (first_index_reg == -1)\n+\t first_index_reg = r;\n \n-\t last_index_reg = r;\n-\t }\n+\t last_index_reg = r;\n+\t}\n \n /* If no index register is available, we can quit now. Set LAST_INDEX_REG\n \t to -1 so we'll know to quit early the next time we get here. */\n@@ -1440,12 +1441,12 @@ reload_combine (void)\n \t rtx link;\n \t HARD_REG_SET used_regs = insn_callee_abi (insn).full_reg_clobbers ();\n \n-\t for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)\n-\t if (TEST_HARD_REG_BIT (used_regs, r))\n-\t {\n-\t\treg_state[r].use_index = RELOAD_COMBINE_MAX_USES;\n-\t\treg_state[r].store_ruid = reload_combine_ruid;\n-\t }\n+\t hard_reg_set_iterator hrsi2;\n+\t EXECUTE_IF_SET_IN_HARD_REG_SET (used_regs, 0, r, hrsi2)\n+\t {\n+\t reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;\n+\t reg_state[r].store_ruid = reload_combine_ruid;\n+\t }\n \n \t for (link = CALL_INSN_FUNCTION_USAGE (insn); link;\n \t link = XEXP (link, 1))\n@@ -1480,9 +1481,11 @@ reload_combine (void)\n \t live = &ever_live_at_start;\n \n \t if (live)\n-\t for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)\n-\t if (TEST_HARD_REG_BIT (*live, r))\n+\t {\n+\t hard_reg_set_iterator hrsi3;\n+\t EXECUTE_IF_SET_IN_HARD_REG_SET (*live, 0, r, hrsi3)\n \t\treg_state[r].use_index = -1;\n+\t }\n \t}\n \n reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid,\ndiff --git a/gcc/reginfo.cc b/gcc/reginfo.cc\nindex 9b515870d55..c06ab4dea72 100644\n--- a/gcc/reginfo.cc\n+++ b/gcc/reginfo.cc\n@@ -269,13 +269,13 @@ init_reg_sets_1 (void)\n for (i = 0; i < N_REG_CLASSES; i++)\n {\n bool any_nonfixed = false;\n- for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)\n-\tif (TEST_HARD_REG_BIT (reg_class_contents[i], j))\n-\t {\n-\t reg_class_size[i]++;\n-\t if (!fixed_regs[j])\n-\t any_nonfixed = true;\n-\t }\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (reg_class_contents[i], 0, j, hrsi)\n+\t{\n+\t reg_class_size[i]++;\n+\t if (!fixed_regs[j])\n+\t any_nonfixed = true;\n+\t}\n class_only_fixed_regs[i] = !any_nonfixed;\n }\n \ndiff --git a/gcc/regrename.cc b/gcc/regrename.cc\nindex b0021019c69..5b625cd27df 100644\n--- a/gcc/regrename.cc\n+++ b/gcc/regrename.cc\n@@ -630,17 +630,17 @@ init_rename_info (class bb_rename_info *p, basic_block bb)\n \t remove_range_from_hard_reg_set (&live_hard_regs, i, iri->nregs);\n \t}\n }\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n+ struct incoming_reg_info *iri;\n+ unsigned int j = 0;\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (start_chains_set, 0, j, hrsi)\n {\n- struct incoming_reg_info *iri = p->incoming + i;\n- if (TEST_HARD_REG_BIT (start_chains_set, i))\n-\t{\n-\t du_head_p chain;\n-\t if (dump_file)\n-\t fprintf (dump_file, \"opening incoming chain\\n\");\n-\t chain = create_new_chain (i, iri->nregs, NULL, NULL, NO_REGS);\n-\t bitmap_set_bit (&p->incoming_open_chains_set, chain->id);\n-\t}\n+ du_head_p chain;\n+ if (dump_file)\n+\tfprintf (dump_file, \"opening incoming chain\\n\");\n+ iri = p->incoming + j;\n+ chain = create_new_chain (j, iri->nregs, NULL, NULL, NO_REGS);\n+ bitmap_set_bit (&p->incoming_open_chains_set, chain->id);\n }\n }\n \ndiff --git a/gcc/reload1.cc b/gcc/reload1.cc\nindex 8cac4011c46..c4562a4eb3c 100644\n--- a/gcc/reload1.cc\n+++ b/gcc/reload1.cc\n@@ -1403,12 +1403,13 @@ maybe_fix_stack_asms (void)\n \t constraints, must be usable as reload registers. So clear them\n \t out of the life information. */\n allowed &= clobbered;\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n-\tif (TEST_HARD_REG_BIT (allowed, i))\n-\t {\n-\t CLEAR_REGNO_REG_SET (&chain->live_throughout, i);\n-\t CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);\n-\t }\n+ hard_reg_set_iterator hrsi;\n+ unsigned int j = 0;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (allowed, 0, j, hrsi)\n+\t{\n+\t CLEAR_REGNO_REG_SET (&chain->live_throughout, j);\n+\t CLEAR_REGNO_REG_SET (&chain->dead_or_set, j);\n+\t}\n }\n \n #endif\n@@ -3919,29 +3920,29 @@ update_eliminables (HARD_REG_SET *pset)\n static bool\n update_eliminables_and_spill (void)\n {\n- int i;\n+ unsigned int i;\n bool did_spill = false;\n HARD_REG_SET to_spill;\n CLEAR_HARD_REG_SET (to_spill);\n update_eliminables (&to_spill);\n used_spill_regs &= ~to_spill;\n \n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n- if (TEST_HARD_REG_BIT (to_spill, i))\n- {\n-\tspill_hard_reg (i, 1);\n-\tdid_spill = true;\n-\n-\t/* Regardless of the state of spills, if we previously had\n-\t a register that we thought we could eliminate, but now\n-\t cannot eliminate, we must run another pass.\n-\n-\t Consider pseudos which have an entry in reg_equiv_* which\n-\t reference an eliminable register. We must make another pass\n-\t to update reg_equiv_* so that we do not substitute in the\n-\t old value from when we thought the elimination could be\n-\t performed. */\n- }\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (to_spill, 0, i, hrsi)\n+ {\n+ spill_hard_reg (i, 1);\n+ did_spill = true;\n+\n+ /* Regardless of the state of spills, if we previously had\n+\t a register that we thought we could eliminate, but now\n+\t cannot eliminate, we must run another pass.\n+\n+\t Consider pseudos which have an entry in reg_equiv_* which\n+\t reference an eliminable register. We must make another pass\n+\t to update reg_equiv_* so that we do not substitute in the\n+\t old value from when we thought the elimination could be\n+\t performed. */\n+ }\n return did_spill;\n }\n \ndiff --git a/gcc/rtl-ssa/insns.cc b/gcc/rtl-ssa/insns.cc\nindex 317a5809b18..5097752e1ac 100644\n--- a/gcc/rtl-ssa/insns.cc\n+++ b/gcc/rtl-ssa/insns.cc\n@@ -632,8 +632,10 @@ function_info::record_call_clobbers (build_info &bi, insn_info *insn,\n m_clobbered_by_calls |= abi.full_and_partial_reg_clobbers ();\n }\n else\n- for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)\n- if (TEST_HARD_REG_BIT (abi.full_reg_clobbers (), regno))\n+ {\n+ hard_reg_set_iterator hrsi;\n+ unsigned int regno = 0;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (abi.full_reg_clobbers (), 0, regno, hrsi)\n \t{\n \t def_info *def = m_defs[regno + 1];\n \t if (!def || def->last_def ()->insn () != insn)\n@@ -645,6 +647,7 @@ function_info::record_call_clobbers (build_info &bi, insn_info *insn,\n \t bi.record_reg_def (def);\n \t }\n \t}\n+ }\n }\n \n // Called while building SSA form using BI. Record that INSN contains\ndiff --git a/gcc/sched-deps.cc b/gcc/sched-deps.cc\nindex ef4728d753b..c24c6ae99e4 100644\n--- a/gcc/sched-deps.cc\n+++ b/gcc/sched-deps.cc\n@@ -3149,21 +3149,22 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)\n \t }\n \t}\n \n- hard_reg_set_iterator hrsi;\n+\thard_reg_set_iterator hrsi;\n \tEXECUTE_IF_SET_IN_HARD_REG_SET(implicit_reg_pending_uses, 0, i , hrsi)\n-\t{\n-\t struct deps_reg *reg_last = &deps->reg_last[i];\n-\t add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false);\n-\t add_dependence_list (insn, reg_last->implicit_sets, 0, REG_DEP_ANTI,\n-\t\t\t\t\t\t false);\n-\t add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE, false);\n-\n-\t if (!deps->readonly)\n \t {\n-\t reg_last->uses = alloc_INSN_LIST (insn, reg_last->uses);\n- \t reg_last->uses_length++;\n+\t struct deps_reg *reg_last = &deps->reg_last[i];\n+\t add_dependence_list (insn, reg_last->sets, 0, REG_DEP_TRUE, false);\n+\t add_dependence_list (insn, reg_last->implicit_sets, 0, REG_DEP_ANTI,\n+\t\t\t\t false);\n+\t add_dependence_list (insn, reg_last->clobbers, 0, REG_DEP_TRUE,\n+\t\t\t\t false);\n+\n+\t if (!deps->readonly)\n+\t {\n+\t\treg_last->uses = alloc_INSN_LIST (insn, reg_last->uses);\n+\t\treg_last->uses_length++;\n+\t }\n \t }\n-\t}\n \n if (targetm.sched.exposed_pipeline)\n \t{\ndiff --git a/gcc/sel-sched-dump.cc b/gcc/sel-sched-dump.cc\nindex 146e819bc6b..e0f20801fa6 100644\n--- a/gcc/sel-sched-dump.cc\n+++ b/gcc/sel-sched-dump.cc\n@@ -539,14 +539,14 @@ dump_insn_vector (rtx_vec_t succs)\n static void\n print_hard_reg_set (FILE *file, const char *prefix, HARD_REG_SET set)\n {\n- int i;\n+ unsigned int i;\n \n fprintf (file, \"%s{ \", prefix);\n- for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)\n- {\n- if (TEST_HARD_REG_BIT (set, i))\n-\tfprintf (file, \"%d \", i);\n- }\n+\n+ hard_reg_set_iterator hrsi;\n+ EXECUTE_IF_SET_IN_HARD_REG_SET (set, 0, i, hrsi)\n+ fprintf (file, \"%d \", i);\n+\n fprintf (file, \"}\\n\");\n }\n \n", "prefixes": [] }