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GET /api/patches/2219147/?format=api
{ "id": 2219147, "url": "http://patchwork.ozlabs.org/api/patches/2219147/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-13-754895c15e9e@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260402-mshv_accel_arm64_supp-v2-13-754895c15e9e@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-02T12:52:40", "name": "[v2,13/14] hw/intc,target/arm/mshv: add MSHV vGICv3 implementation", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "efd8f4653a3604f1101a5bf524353e93e2d801f0", "submitter": { "id": 92925, "url": "http://patchwork.ozlabs.org/api/people/92925/?format=api", "name": "Aastha Rawat", "email": "aastharawat@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-13-754895c15e9e@linux.microsoft.com/mbox/", "series": [ { "id": 498484, "url": "http://patchwork.ozlabs.org/api/series/498484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498484", "date": "2026-04-02T12:52:39", "name": "Add ARM64 support for MSHV accelerator", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498484/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219147/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219147/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=Qh9k7nU9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmjsW2PDTz1yCs\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 03 Apr 2026 00:50:07 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8IKx-0007Sr-JC; Thu, 02 Apr 2026 09:43:55 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <aastharawat@linux.microsoft.com>)\n id 1w8IKt-0005fW-LG; Thu, 02 Apr 2026 09:43:51 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <aastharawat@linux.microsoft.com>)\n id 1w8HYD-0008TT-GJ; Thu, 02 Apr 2026 08:53:36 -0400", "from localhost (unknown [131.107.147.136])\n by linux.microsoft.com (Postfix) with ESMTPSA id 5E62F20B6F0C;\n Thu, 2 Apr 2026 05:53:07 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 5E62F20B6F0C", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1775134387;\n bh=Iqbi7u5tYNh4i8ZrZfBBa2K6wUBHH2xKi1VgQMHkTtw=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n b=Qh9k7nU9Yd6lQb5X9q+RmWPY/V2/GbXxb4ZF+WrPpCZ3Qpm56SQROKfvEAS8tCpl0\n QT5KetLgAid2DCBM/aM3gZGn2YLwyyMQaJknFxs+8JrjoEDa1EnuPPHCEkqjvhwK51\n fv+EukJThsWzrl3+rwvKLTdfjT+6aaXTd32DOAgk=", "From": "Aastha Rawat <aastharawat@linux.microsoft.com>", "Date": "Thu, 02 Apr 2026 12:52:40 +0000", "Subject": "[PATCH v2 13/14] hw/intc,target/arm/mshv: add MSHV vGICv3\n implementation", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260402-mshv_accel_arm64_supp-v2-13-754895c15e9e@linux.microsoft.com>", "References": "\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>", "In-Reply-To": "\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Wei Liu <wei.liu@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>, =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Anirudh Rayabharam <anirudh@anirudhrb.com>,\n Aastha Rawat <aastharawat@linux.microsoft.com>,\n Magnus Kulke <magnus.kulke@linux.microsoft.com>, qemu-arm@nongnu.org,\n Alexander Graf <agraf@csgraf.de>, Pedro Barbuda <pbarbuda@microsoft.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>", "X-Mailer": "b4 0.15.1", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: \"Anirudh Rayabharam (Microsoft)\" <anirudh@anirudhrb.com>\n\nAdd in-kernel GICv3 support for the MSHV accelerator, following the\nsame approach as the KVM and WHPX vGIC backends. The implementation\nhandles IRQ injection via the HVCALL_ASSERT_VIRTUAL_INTERRUPT hypercall.\n\nIntroduce mshv_arch_pre_init_vm(), an arch-specific hook called after\nVM creation but before VM initialization, used on arm64 to configure\nGIC partition properties (GICD base, ITS translater base, timer and PMU\nPPI numbers). The x86 side provides a no-op stub.\n\nUpdate the virt machine to treat MSHV like WHPX for GIC version\nselection (GICv3 only) and MSI controller finalization (no ITS support).\n\nSigned-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>\n---\n accel/mshv/mshv-all.c | 5 +\n hw/arm/virt.c | 8 +-\n hw/intc/arm_gicv3_common.c | 3 +\n hw/intc/arm_gicv3_mshv.c | 181 +++++++++++++++++++++++++++++++++++++\n hw/intc/meson.build | 1 +\n include/hw/hyperv/hvgdk_mini.h | 2 +\n include/hw/hyperv/hvhdk_mini.h | 6 ++\n include/hw/intc/arm_gicv3_common.h | 1 +\n include/system/mshv_int.h | 1 +\n target/arm/mshv/mshv-all.c | 62 +++++++++++++\n target/i386/mshv/mshv-all.c | 5 +\n 11 files changed, 271 insertions(+), 4 deletions(-)", "diff": "diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\nindex 6c0ddbf3ca..628cd0ad17 100644\n--- a/accel/mshv/mshv-all.c\n+++ b/accel/mshv/mshv-all.c\n@@ -200,6 +200,11 @@ static int create_vm(int mshv_fd, int *vm_fd)\n return -1;\n }\n \n+ ret = mshv_arch_pre_init_vm(*vm_fd);\n+ if (ret < 0) {\n+ return -1;\n+ }\n+\n ret = initialize_vm(*vm_fd);\n if (ret < 0) {\n return -1;\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex 34eb5248a9..5f922ece9c 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -2117,7 +2117,7 @@ static void finalize_gic_version(VirtMachineState *vms)\n /* KVM w/o kernel irqchip can only deal with GICv2 */\n gics_supported |= VIRT_GIC_VERSION_2_MASK;\n accel_name = \"KVM with kernel-irqchip=off\";\n- } else if (whpx_enabled()) {\n+ } else if (whpx_enabled() || mshv_enabled()) {\n gics_supported |= VIRT_GIC_VERSION_3_MASK;\n } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {\n gics_supported |= VIRT_GIC_VERSION_2_MASK;\n@@ -2159,7 +2159,7 @@ static void finalize_msi_controller(VirtMachineState *vms)\n if (vms->msi_controller == VIRT_MSI_CTRL_AUTO) {\n if (vms->gic_version == VIRT_GIC_VERSION_2) {\n vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n- } else if (whpx_enabled()) {\n+ } else if (whpx_enabled() || mshv_enabled()) {\n vms->msi_controller = VIRT_MSI_CTRL_GICV2M;\n } else {\n vms->msi_controller = VIRT_MSI_CTRL_ITS;\n@@ -2176,8 +2176,8 @@ static void finalize_msi_controller(VirtMachineState *vms)\n error_report(\"GICv2 + ITS is an invalid configuration.\");\n exit(1);\n }\n- if (whpx_enabled()) {\n- error_report(\"ITS not supported on WHPX.\");\n+ if (whpx_enabled() || mshv_enabled()) {\n+ error_report(\"ITS not supported on WHPX and MSHV.\");\n exit(1);\n }\n }\ndiff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c\nindex 9200671c7a..239c645ab9 100644\n--- a/hw/intc/arm_gicv3_common.c\n+++ b/hw/intc/arm_gicv3_common.c\n@@ -33,6 +33,7 @@\n #include \"hw/arm/linux-boot-if.h\"\n #include \"system/kvm.h\"\n #include \"system/whpx.h\"\n+#include \"system/mshv.h\"\n \n \n static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)\n@@ -658,6 +659,8 @@ const char *gicv3_class_name(void)\n return \"kvm-arm-gicv3\";\n } else if (whpx_enabled()) {\n return TYPE_WHPX_GICV3;\n+ } else if (mshv_enabled()) {\n+ return TYPE_MSHV_GICV3;\n } else {\n if (kvm_enabled()) {\n error_report(\"Userspace GICv3 is not supported with KVM\");\ndiff --git a/hw/intc/arm_gicv3_mshv.c b/hw/intc/arm_gicv3_mshv.c\nnew file mode 100644\nindex 0000000000..a87819a5ba\n--- /dev/null\n+++ b/hw/intc/arm_gicv3_mshv.c\n@@ -0,0 +1,181 @@\n+/*\n+ * ARM Generic Interrupt Controller using MSHV in-kernel support\n+ *\n+ * Copyright Microsoft, Corp. 2026\n+ * Based on vGICv3 KVM code by Pavel Fedin\n+ *\n+ * Authors:\n+ * Aastha Rawat <aastharawat@microsoft.com>\n+ * Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qapi/error.h\"\n+#include \"qemu/error-report.h\"\n+#include \"hw/intc/arm_gicv3_common.h\"\n+#include \"migration/blocker.h\"\n+#include \"target/arm/cpregs.h\"\n+#include \"hw/hyperv/hvgdk_mini.h\"\n+#include \"system/mshv.h\"\n+#include \"system/mshv_int.h\"\n+\n+struct MSHVARMGICv3Class {\n+ ARMGICv3CommonClass parent_class;\n+ DeviceRealize parent_realize;\n+ ResettablePhases parent_phases;\n+};\n+\n+OBJECT_DECLARE_TYPE(GICv3State, MSHVARMGICv3Class, MSHV_GICV3)\n+\n+static void mshv_gicv3_get(GICv3State *s)\n+{\n+}\n+\n+static void mshv_gicv3_put(GICv3State *s)\n+{\n+}\n+\n+static void mshv_gicv3_reset_hold(Object *obj, ResetType type)\n+{\n+ GICv3State *s = ARM_GICV3_COMMON(obj);\n+ MSHVARMGICv3Class *mgc = MSHV_GICV3_GET_CLASS(s);\n+\n+ if (mgc->parent_phases.hold) {\n+ mgc->parent_phases.hold(obj, type);\n+ }\n+\n+ mshv_gicv3_put(s);\n+}\n+\n+static void mshv_gicv3_set_irq(void *opaque, int irq, int level)\n+{\n+ int ret;\n+ GICv3State *s = (GICv3State *)opaque;\n+ int vm_fd = mshv_state->vm;\n+ struct hv_input_assert_virtual_interrupt arg = {0};\n+ struct mshv_root_hvcall args = {0};\n+ union hv_interrupt_control control = {\n+ .interrupt_type = HV_ARM64_INTERRUPT_TYPE_FIXED,\n+ .rsvd1 = 0,\n+ .asserted = level,\n+ .rsvd2 = 0\n+ };\n+\n+ if (irq >= s->num_irq) {\n+ return;\n+ }\n+\n+ arg.control = control;\n+ arg.vector = GIC_INTERNAL + irq;\n+\n+ args.code = HVCALL_ASSERT_VIRTUAL_INTERRUPT;\n+ args.in_sz = sizeof(arg);\n+ args.in_ptr = (uint64_t)&arg;\n+\n+ ret = mshv_hvcall(vm_fd, &args);\n+ if (ret < 0) {\n+ error_report(\"Failed to set GICv3 IRQ %d to level %d\", irq, level);\n+ }\n+}\n+\n+static void mshv_gicv3_realize(DeviceState *dev, Error **errp)\n+{\n+ ERRP_GUARD();\n+ GICv3State *s = MSHV_GICV3(dev);\n+ MSHVARMGICv3Class *mgc = MSHV_GICV3_GET_CLASS(s);\n+ int i, ret;\n+\n+ mgc->parent_realize(dev, errp);\n+ if (*errp) {\n+ return;\n+ }\n+\n+ if (s->revision != 3) {\n+ error_setg(errp, \"unsupported GIC revision %d for platform GIC\",\n+ s->revision);\n+ return;\n+ }\n+\n+ if (s->security_extn) {\n+ error_setg(errp, \"the platform vGICv3 does not implement the \"\n+ \"security extensions\");\n+ return;\n+ }\n+\n+ if (s->nmi_support) {\n+ error_setg(errp, \"NMI is not supported with the platform GIC\");\n+ return;\n+ }\n+\n+ if (s->nb_redist_regions > 1) {\n+ error_setg(errp, \"Multiple VGICv3 redistributor regions are not \"\n+ \"supported by MSHV\");\n+ error_append_hint(errp, \"A maximum of %d VCPUs can be used\",\n+ s->redist_region_count[0]);\n+ return;\n+ }\n+\n+ gicv3_init_irqs_and_mmio(s, mshv_gicv3_set_irq, NULL);\n+\n+ for (i = 0; i < s->num_cpu; i++) {\n+ CPUState *cpu_state = qemu_get_cpu(i);\n+\n+ hv_register_assoc gicr_base = {\n+ .name = HV_ARM64_REGISTER_GICR_BASE_GPA,\n+ .value = {\n+ .reg64 = 0x080A0000 + (GICV3_REDIST_SIZE * i)\n+ }\n+ };\n+\n+ ret = mshv_set_generic_regs(cpu_state, &gicr_base, 1);\n+ if (ret < 0) {\n+ error_setg(errp, \"Failed to set GICR base for CPU %d\", i);\n+ return;\n+ }\n+ }\n+\n+ if (s->maint_irq) {\n+ error_setg(errp,\n+ \"Nested virtualisation not currently supported by MSHV\");\n+ return;\n+ }\n+\n+ error_setg(&s->migration_blocker,\n+ \"Live migration disabled because GIC state save/restore not supported on MSHV\");\n+ if (migrate_add_blocker(&s->migration_blocker, errp) < 0) {\n+ error_report_err(*errp);\n+ }\n+}\n+\n+static void mshv_gicv3_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n+ ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);\n+ MSHVARMGICv3Class *mgc = MSHV_GICV3_CLASS(klass);\n+\n+ agcc->pre_save = mshv_gicv3_get;\n+ agcc->post_load = mshv_gicv3_put;\n+\n+ device_class_set_parent_realize(dc, mshv_gicv3_realize,\n+ &mgc->parent_realize);\n+ resettable_class_set_parent_phases(rc, NULL, mshv_gicv3_reset_hold, NULL,\n+ &mgc->parent_phases);\n+}\n+\n+static const TypeInfo mshv_arm_gicv3_info = {\n+ .name = TYPE_MSHV_GICV3,\n+ .parent = TYPE_ARM_GICV3_COMMON,\n+ .instance_size = sizeof(GICv3State),\n+ .class_init = mshv_gicv3_class_init,\n+ .class_size = sizeof(MSHVARMGICv3Class),\n+};\n+\n+static void mshv_gicv3_register_types(void)\n+{\n+ type_register_static(&mshv_arm_gicv3_info);\n+}\n+\n+type_init(mshv_gicv3_register_types)\ndiff --git a/hw/intc/meson.build b/hw/intc/meson.build\nindex 96742df090..9d824db582 100644\n--- a/hw/intc/meson.build\n+++ b/hw/intc/meson.build\n@@ -43,6 +43,7 @@ arm_common_ss.add(when: 'CONFIG_ARM_GICV3', if_true: files('arm_gicv3_cpuif.c'))\n specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))\n specific_ss.add(when: ['CONFIG_WHPX', 'TARGET_AARCH64'], if_true: files('arm_gicv3_whpx.c'))\n specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))\n+specific_ss.add(when: ['CONFIG_MSHV', 'TARGET_AARCH64'], if_true: files('arm_gicv3_mshv.c'))\n arm_common_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))\n specific_ss.add(when: 'CONFIG_GRLIB', if_true: files('grlib_irqmp.c'))\n specific_ss.add(when: 'CONFIG_IOAPIC', if_true: files('ioapic.c'))\ndiff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h\nindex eb766734d6..b50a65a0d4 100644\n--- a/include/hw/hyperv/hvgdk_mini.h\n+++ b/include/hw/hyperv/hvgdk_mini.h\n@@ -66,6 +66,8 @@ typedef enum hv_register_name {\n HV_ARM64_REGISTER_MIDR_EL1 = 0x00040051,\n HV_ARM64_REGISTER_MPIDR_EL1 = 0x00040001,\n \n+ HV_ARM64_REGISTER_GICR_BASE_GPA = 0x00063000,\n+\n #elif defined(__x86_64__)\n /* X64 User-Mode Registers */\n HV_X64_REGISTER_RAX = 0x00020000,\ndiff --git a/include/hw/hyperv/hvhdk_mini.h b/include/hw/hyperv/hvhdk_mini.h\nindex 9c2f3cf5ae..4d78fa0677 100644\n--- a/include/hw/hyperv/hvhdk_mini.h\n+++ b/include/hw/hyperv/hvhdk_mini.h\n@@ -62,6 +62,12 @@ enum hv_partition_property_code {\n HV_PARTITION_PROPERTY_ISOLATION_POLICY = 0x00050014,\n HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION = 0x00050017,\n HV_PARTITION_PROPERTY_SEV_VMGEXIT_OFFLOADS = 0x00050022,\n+ HV_PARTITION_PROPERTY_GICD_BASE_ADDRESS = 0x00050028,\n+ HV_PARTITION_PROPERTY_GITS_TRANSLATER_BASE_ADDRESS = 0x00050029,\n+ HV_PARTITION_PROPERTY_GIC_LPI_INT_ID_BITS = 0x0005002A,\n+ HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTV = 0x0005002B,\n+ HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTP = 0x0005002C,\n+ HV_PARTITION_PROPERTY_GIC_PPI_PERFORMANCE_MONITORS_INTERRUPT = 0x0005002D,\n \n /* Compatibility properties */\n HV_PARTITION_PROPERTY_PROCESSOR_VENDOR = 0x00060000,\ndiff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3_common.h\nindex c55cf18120..3baac1a35c 100644\n--- a/include/hw/intc/arm_gicv3_common.h\n+++ b/include/hw/intc/arm_gicv3_common.h\n@@ -315,6 +315,7 @@ DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass,\n \n /* Types for GICv3 kernel-irqchip */\n #define TYPE_WHPX_GICV3 \"whpx-arm-gicv3\"\n+#define TYPE_MSHV_GICV3 \"mshv-arm-gicv3\"\n \n struct ARMGICv3CommonClass {\n /*< private >*/\ndiff --git a/include/system/mshv_int.h b/include/system/mshv_int.h\nindex c72c91cd23..0ef98abedf 100644\n--- a/include/system/mshv_int.h\n+++ b/include/system/mshv_int.h\n@@ -97,6 +97,7 @@ void mshv_arch_destroy_vcpu(CPUState *cpu);\n void mshv_arch_amend_proc_features(\n union hv_partition_synthetic_processor_features *features);\n int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd);\n+int mshv_arch_pre_init_vm(int vm_fd);\n int mshv_arch_post_init_vm(int vm_fd);\n void mshv_setup_hvcall_args(AccelCPUState *state);\n \ndiff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c\nindex c1c0291461..5a07d45f33 100644\n--- a/target/arm/mshv/mshv-all.c\n+++ b/target/arm/mshv/mshv-all.c\n@@ -290,6 +290,68 @@ void mshv_arch_amend_proc_features(\n \n }\n \n+static int set_partition_prop(int vm_fd, uint32_t prop_code,\n+ uint64_t prop_value)\n+{\n+ int ret;\n+ struct hv_input_set_partition_property in = {0};\n+ in.property_code = prop_code;\n+ in.property_value = prop_value;\n+\n+ struct mshv_root_hvcall args = {0};\n+ args.code = HVCALL_SET_PARTITION_PROPERTY;\n+ args.in_sz = sizeof(in);\n+ args.in_ptr = (uint64_t)∈\n+\n+ ret = mshv_hvcall(vm_fd, &args);\n+ if (ret < 0) {\n+ error_report(\"Failed to set partition property code %u\", prop_code);\n+ return -1;\n+ }\n+\n+ return 0;\n+}\n+\n+int mshv_arch_pre_init_vm(int vm_fd)\n+{\n+ int ret;\n+ VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());\n+\n+ ret = set_partition_prop(vm_fd,\n+ HV_PARTITION_PROPERTY_GICD_BASE_ADDRESS,\n+ vms->memmap[VIRT_GIC_DIST].base);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n+ ret = set_partition_prop(vm_fd,\n+ HV_PARTITION_PROPERTY_GITS_TRANSLATER_BASE_ADDRESS,\n+ vms->memmap[VIRT_GIC_ITS].base);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n+ ret = set_partition_prop(vm_fd,\n+ HV_PARTITION_PROPERTY_GIC_LPI_INT_ID_BITS,\n+ 0);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n+ ret = set_partition_prop(vm_fd,\n+ HV_PARTITION_PROPERTY_GIC_PPI_OVERFLOW_INTERRUPT_FROM_CNTV,\n+ ARCH_TIMER_VIRT_IRQ);\n+ if (ret < 0) {\n+ return ret;\n+ }\n+\n+ ret = set_partition_prop(vm_fd,\n+ HV_PARTITION_PROPERTY_GIC_PPI_PERFORMANCE_MONITORS_INTERRUPT,\n+ VIRTUAL_PMU_IRQ);\n+\n+ return ret;\n+}\n+\n int mshv_arch_post_init_vm(int vm_fd)\n {\n return 0;\ndiff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c\nindex f0b43aa86f..ce8b426ea4 100644\n--- a/target/i386/mshv/mshv-all.c\n+++ b/target/i386/mshv/mshv-all.c\n@@ -39,6 +39,11 @@ int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)\n return 0;\n }\n \n+int mshv_arch_pre_init_vm(int vm_fd)\n+{\n+ return 0;\n+}\n+\n /*\n * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a\n * fault to the guest if it tries to access it. It is possible to override\n", "prefixes": [ "v2", "13/14" ] }