Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2219146/?format=api
{ "id": 2219146, "url": "http://patchwork.ozlabs.org/api/patches/2219146/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-10-754895c15e9e@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260402-mshv_accel_arm64_supp-v2-10-754895c15e9e@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-02T12:52:37", "name": "[v2,10/14] target/arm: extract MMIO emulation logic for HVF & WHPX", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "eac0ff9fae7a6b57d737d5f8af16123d26aecc71", "submitter": { "id": 92925, "url": "http://patchwork.ozlabs.org/api/people/92925/?format=api", "name": "Aastha Rawat", "email": "aastharawat@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-10-754895c15e9e@linux.microsoft.com/mbox/", "series": [ { "id": 498484, "url": "http://patchwork.ozlabs.org/api/series/498484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498484", "date": "2026-04-02T12:52:39", "name": "Add ARM64 support for MSHV accelerator", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498484/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219146/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219146/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=GJVi4GKs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmjsH4wgNz1yGH\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 03 Apr 2026 00:49:55 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8ILG-0008Lb-71; Thu, 02 Apr 2026 09:44:14 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <aastharawat@linux.microsoft.com>)\n id 1w8IKt-0006PC-LM; Thu, 02 Apr 2026 09:43:51 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <aastharawat@linux.microsoft.com>)\n id 1w8HYD-0008T4-GI; Thu, 02 Apr 2026 08:53:36 -0400", "from localhost (unknown [131.107.147.136])\n by linux.microsoft.com (Postfix) with ESMTPSA id 6EAFE20B703B;\n Thu, 2 Apr 2026 05:53:05 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 6EAFE20B703B", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1775134385;\n bh=gPpAZwOHC73qULp/xwV5Y6sj58uM2Ujhph39FL6vbIY=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n b=GJVi4GKsF7ZRsEZxXG0o0f8J1FFKqovxzg+/9/7OuepNfw4AFA8SLlvC3wkem9jMk\n +GheysUG8BdDpp1hCCtbTYf1uXud9YfYfeTY+2aQEcsPxcWzNTTGFUjATBmIezmLnu\n 3KkVAG7xJ/0eCQzsNvJHWCK7pyfcGVMD2YD0ATKE=", "From": "Aastha Rawat <aastharawat@linux.microsoft.com>", "Date": "Thu, 02 Apr 2026 12:52:37 +0000", "Subject": "[PATCH v2 10/14] target/arm: extract MMIO emulation logic for HVF\n & WHPX", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260402-mshv_accel_arm64_supp-v2-10-754895c15e9e@linux.microsoft.com>", "References": "\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>", "In-Reply-To": "\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Wei Liu <wei.liu@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>, =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Anirudh Rayabharam <anirudh@anirudhrb.com>,\n Aastha Rawat <aastharawat@linux.microsoft.com>,\n Magnus Kulke <magnus.kulke@linux.microsoft.com>, qemu-arm@nongnu.org,\n Alexander Graf <agraf@csgraf.de>, Pedro Barbuda <pbarbuda@microsoft.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>", "X-Mailer": "b4 0.15.1", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "- Move common MMIO emulation code from HVF and WHPX backend to\n arm_emulate_mmio() in helper.c.\n- Update HVF and WHPX to use the new helper and shared types.\n\nSigned-off-by: Aastha Rawat <aastharawat@linux.microsoft.com>\n---\n target/arm/helper.c | 60 +++++++++++++++++++++++++++++++++++++++++++\n target/arm/helper.h | 5 ++++\n target/arm/hvf/hvf.c | 64 ++++++++++++++++++++++++----------------------\n target/arm/syndrome.h | 37 +++++++++++++++++++++++++++\n target/arm/whpx/whpx-all.c | 62 +++++++++++---------------------------------\n 5 files changed, 150 insertions(+), 78 deletions(-)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 7389f2988c..c9457c8384 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -34,6 +34,8 @@\n #endif\n #include \"cpregs.h\"\n #include \"target/arm/gtimer.h\"\n+#include \"target/arm/helper.h\"\n+#include \"target/arm/syndrome.h\"\n #include \"qemu/plugin.h\"\n \n static void switch_mode(CPUARMState *env, int mode);\n@@ -9130,6 +9132,64 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)\n take_aarch32_exception(env, new_mode, mask, offset, addr);\n }\n \n+/*\n+ * Emulate a data abort syndrome for MMIO/guest memory access\n+ */\n+int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa)\n+{\n+ CPUARMState *env = &ARM_CPU(cpu)->env;\n+ int ret;\n+ IssDataAbort iss = { 0 };\n+ iss.raw = syndrome.iss;\n+\n+ if (!(syndrome.ec == data_abort_lower || syndrome.ec == data_abort)) {\n+ error_report(\"Unknown exception class 0x%x\", syndrome.ec);\n+ return -1;\n+ }\n+\n+ if (!iss.isv) {\n+ error_report(\"Cannot emulate MMIO. ISS not valid.\");\n+ return -1;\n+ }\n+\n+ AddressSpace *as = cpu_get_address_space(cpu, ARMASIdx_NS);\n+ uint64_t len = 1ULL << iss.sas;\n+ bool sign_extend = iss.sse;\n+ uint64_t reg_index = iss.srt;\n+\n+ if (iss.wnr) {\n+ uint8_t data[8];\n+ uint64_t val = reg_index < 31 ? env->xregs[reg_index] : 0ULL;\n+ val = cpu_to_le64(val);\n+ memcpy(data, &val, sizeof(val));\n+ ret = address_space_write(as, gpa, MEMTXATTRS_UNSPECIFIED, data, len);\n+ if (ret != MEMTX_OK) {\n+ error_report(\"Failed to write guest memory\");\n+ return -1;\n+ }\n+ } else {\n+ uint8_t data[8] = { 0 };\n+ ret = address_space_read(as, gpa, MEMTXATTRS_UNSPECIFIED, data, len);\n+ if (ret != MEMTX_OK) {\n+ error_report(\"Failed to read guest memory\");\n+ return -1;\n+ }\n+ uint64_t val;\n+ memcpy(&val, data, sizeof(val));\n+ val = le64_to_cpu(val);\n+ if (sign_extend) {\n+ uint64_t shift = 64 - (len * 8);\n+ val = (((int64_t)val << shift) >> shift);\n+ }\n+ if (!iss.sf) {\n+ val &= 0xffffffff;\n+ }\n+ env->xregs[reg_index] = val;\n+ }\n+\n+ return 0;\n+}\n+\n static int aarch64_regnum(CPUARMState *env, int aarch32_reg)\n {\n /*\ndiff --git a/target/arm/helper.h b/target/arm/helper.h\nindex b1c26c180e..3bc22595fd 100644\n--- a/target/arm/helper.h\n+++ b/target/arm/helper.h\n@@ -3,8 +3,13 @@\n #ifndef HELPER__H\n #define HELPER__H\n \n+#include <stdint.h>\n+#include <stdbool.h>\n #include \"exec/helper-proto-common.h\"\n #include \"exec/helper-gen-common.h\"\n+#include \"target/arm/syndrome.h\"\n+\n+int arm_emulate_mmio(CPUState *cpu, EsrEl2 syndrome, uint64_t gpa);\n \n #define HELPER_H \"tcg/helper-defs.h\"\n #include \"exec/helper-proto.h.inc\"\ndiff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 5fc8f6bbbd..9ecad6c222 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -13,6 +13,7 @@\n #include \"qemu/error-report.h\"\n #include \"qemu/log.h\"\n \n+#include \"syndrome.h\"\n #include \"system/runstate.h\"\n #include \"system/hvf.h\"\n #include \"system/hvf_int.h\"\n@@ -35,6 +36,7 @@\n #include \"target/arm/multiprocessing.h\"\n #include \"target/arm/gtimer.h\"\n #include \"target/arm/trace.h\"\n+#include \"target/arm/helper.h\"\n #include \"trace.h\"\n #include \"migration/vmstate.h\"\n \n@@ -2072,12 +2074,15 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n {\n CPUARMState *env = cpu_env(cpu);\n ARMCPU *arm_cpu = env_archcpu(env);\n- uint64_t syndrome = excp->syndrome;\n- uint32_t ec = syn_get_ec(syndrome);\n+ uint64_t syndrome;\n+ uint32_t ec;\n bool advance_pc = false;\n hv_return_t r;\n int ret = 0;\n \n+ syndrome = excp->syndrome;\n+ ec = syn_get_ec(syndrome);\n+\n switch (ec) {\n case EC_SOFTWARESTEP: {\n ret = EXCP_DEBUG;\n@@ -2123,29 +2128,22 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n break;\n }\n case EC_DATAABORT: {\n- bool isv = syndrome & ARM_EL_ISV;\n- bool iswrite = (syndrome >> 6) & 1;\n- bool s1ptw = (syndrome >> 7) & 1;\n- bool sse = (syndrome >> 21) & 1;\n- uint32_t sas = (syndrome >> 22) & 3;\n- uint32_t len = 1 << sas;\n- uint32_t srt = (syndrome >> 16) & 0x1f;\n- uint32_t cm = (syndrome >> 8) & 0x1;\n- uint64_t val = 0;\n+ EsrEl2 esr_el2 = { .raw = syndrome };\n+ IssDataAbort iss = { .raw = esr_el2.iss };\n uint64_t ipa = excp->physical_address;\n AddressSpace *as = cpu_get_address_space(cpu, ARMASIdx_NS);\n \n- trace_hvf_data_abort(excp->virtual_address, ipa, isv,\n- iswrite, s1ptw, len, srt);\n+ trace_hvf_data_abort(excp->virtual_address, ipa, iss.isv,\n+ iss.wnr, iss.s1ptw, 1ULL << iss.sas, iss.srt);\n \n- if (cm) {\n+ if (iss.cm) {\n /* We don't cache MMIO regions */\n advance_pc = true;\n break;\n }\n \n /* Handle dirty page logging for ram. */\n- if (iswrite) {\n+ if (iss.wnr) {\n hwaddr xlat;\n MemoryRegion *mr = address_space_translate(as, ipa, &xlat,\n NULL, true,\n@@ -2172,27 +2170,31 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcpu_exit_exception_t *excp)\n * TODO: If s1ptw, this is an error in the guest os page tables.\n * Inject the exception into the guest.\n */\n- assert(!s1ptw);\n-\n- /*\n- * TODO: ISV will be 0 for SIMD or SVE accesses.\n- * Inject the exception into the guest.\n- */\n- assert(isv);\n+ assert(!iss.s1ptw);\n \n /*\n * Emulate MMIO.\n * TODO: Inject faults for errors.\n */\n- if (iswrite) {\n- val = hvf_get_reg(cpu, srt);\n- address_space_write(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len);\n- } else {\n- address_space_read(as, ipa, MEMTXATTRS_UNSPECIFIED, &val, len);\n- if (sse) {\n- val = sextract64(val, 0, len * 8);\n- }\n- hvf_set_reg(cpu, srt, val);\n+ ret = hvf_arch_get_registers(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to get registers for MMIO\");\n+ esr_el2.raw, ipa);\n+ return -1;\n+ }\n+\n+ ret = arm_emulate_mmio(cpu, esr_el2, ipa);\n+ if (ret < 0) {\n+ error_report(\"Failed to emulate MMIO, syndrome=0x%llx, gpa=0x%llx\",\n+ esr_el2.raw, ipa);\n+ return -1;\n+ }\n+\n+ ret = hvf_arch_put_registers(cpu);\n+ if (ret < 0) {\n+ error_report(\"Failed to set registers after MMIO emulation\");\n+ esr_el2.raw, ipa);\n+ return -1;\n }\n advance_pc = true;\n break;\ndiff --git a/target/arm/syndrome.h b/target/arm/syndrome.h\nindex bff61f052c..777d4fb975 100644\n--- a/target/arm/syndrome.h\n+++ b/target/arm/syndrome.h\n@@ -101,6 +101,43 @@ typedef enum {\n GCS_IT_GCSPOPX = 9,\n } GCSInstructionType;\n \n+typedef union {\n+ uint64_t raw;\n+ struct {\n+ uint32_t iss:25;\n+ uint32_t il:1;\n+ uint32_t ec:6;\n+ uint32_t iss2:5;\n+ uint32_t _rsvd:27;\n+ } QEMU_PACKED;\n+} EsrEl2;\n+\n+typedef union {\n+ uint32_t raw;\n+ struct {\n+ uint32_t dfsc:6;\n+ uint32_t wnr:1;\n+ uint32_t s1ptw:1;\n+ uint32_t cm:1;\n+ uint32_t ea:1;\n+ uint32_t fnv:1;\n+ uint32_t set:2;\n+ uint32_t vncr:1;\n+ uint32_t ar:1;\n+ uint32_t sf:1;\n+ uint32_t srt:5;\n+ uint32_t sse:1;\n+ uint32_t sas:2;\n+ uint32_t isv:1;\n+ uint32_t _unused:7;\n+ } QEMU_PACKED;\n+} IssDataAbort;\n+\n+typedef enum {\n+ data_abort_lower = 36,\n+ data_abort = 37,\n+} ExceptionClass;\n+\n #define ARM_EL_EC_LENGTH 6\n #define ARM_EL_EC_SHIFT 26\n #define ARM_EL_IL_SHIFT 25\ndiff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c\nindex 513551bec1..b4daeaff4d 100644\n--- a/target/arm/whpx/whpx-all.c\n+++ b/target/arm/whpx/whpx-all.c\n@@ -28,6 +28,8 @@\n \n #include \"syndrome.h\"\n #include \"target/arm/cpregs.h\"\n+#include \"target/arm/helper.h\"\n+#include \"target/arm/syndrome.h\"\n #include \"internals.h\"\n \n #include \"system/whpx-internal.h\"\n@@ -330,59 +332,25 @@ static void whpx_set_global_reg(WHV_REGISTER_NAME reg, WHV_REGISTER_VALUE val)\n }\n }\n \n-static uint64_t whpx_get_gp_reg(CPUState *cpu, int rt)\n-{\n- assert(rt <= 31);\n- if (rt == 31) {\n- return 0;\n- }\n- WHV_REGISTER_NAME reg = WHvArm64RegisterX0 + rt;\n- WHV_REGISTER_VALUE val;\n- whpx_get_reg(cpu, reg, &val);\n-\n- return val.Reg64;\n-}\n-\n-static void whpx_set_gp_reg(CPUState *cpu, int rt, uint64_t val)\n-{\n- assert(rt < 31);\n- WHV_REGISTER_NAME reg = WHvArm64RegisterX0 + rt;\n- WHV_REGISTER_VALUE reg_val = {.Reg64 = val};\n-\n- whpx_set_reg(cpu, reg, reg_val);\n-}\n-\n static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx)\n {\n- uint64_t syndrome = ctx->Syndrome;\n-\n- bool isv = syndrome & ARM_EL_ISV;\n- bool iswrite = (syndrome >> 6) & 1;\n- bool sse = (syndrome >> 21) & 1;\n- uint32_t sas = (syndrome >> 22) & 3;\n- uint32_t len = 1 << sas;\n- uint32_t srt = (syndrome >> 16) & 0x1f;\n- uint32_t cm = (syndrome >> 8) & 0x1;\n- uint64_t val = 0;\n+ int ret = 0;\n+ EsrEl2 esr = { .raw = ctx->Syndrome };\n+ uint32_t cm = (esr.iss >> 8) & 0x1;\n \n assert(!cm);\n- assert(isv);\n-\n- if (iswrite) {\n- val = whpx_get_gp_reg(cpu, srt);\n- address_space_write(&address_space_memory,\n- ctx->Gpa,\n- MEMTXATTRS_UNSPECIFIED, &val, len);\n- } else {\n- address_space_read(&address_space_memory,\n- ctx->Gpa,\n- MEMTXATTRS_UNSPECIFIED, &val, len);\n- if (sse) {\n- val = sextract64(val, 0, len * 8);\n- }\n- whpx_set_gp_reg(cpu, srt, val);\n+\n+ whpx_get_registers(cpu, WHPX_LEVEL_RUNTIME_STATE);\n+\n+ ret = arm_emulate_mmio(cpu, esr, ctx->Gpa);\n+ if (ret < 0) {\n+ error_report(\"WHPX: Failed to handle MMIO, syndrome=0x%llx, gpa=0x%llx\",\n+ esr.raw, ctx->Gpa);\n+ return -1;\n }\n \n+ whpx_set_registers(cpu, WHPX_LEVEL_RUNTIME_STATE);\n+\n return 0;\n }\n \n", "prefixes": [ "v2", "10/14" ] }