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GET /api/patches/2219144/?format=api
{ "id": 2219144, "url": "http://patchwork.ozlabs.org/api/patches/2219144/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-6-754895c15e9e@linux.microsoft.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260402-mshv_accel_arm64_supp-v2-6-754895c15e9e@linux.microsoft.com>", "list_archive_url": null, "date": "2026-04-02T12:52:33", "name": "[v2,06/14] accel/mshv: add arch-specific accelerator init hook", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "74eb804c44ad99f99c8e8d9be4153fac03342b3a", "submitter": { "id": 92925, "url": "http://patchwork.ozlabs.org/api/people/92925/?format=api", "name": "Aastha Rawat", "email": "aastharawat@linux.microsoft.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402-mshv_accel_arm64_supp-v2-6-754895c15e9e@linux.microsoft.com/mbox/", "series": [ { "id": 498484, "url": "http://patchwork.ozlabs.org/api/series/498484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498484", "date": "2026-04-02T12:52:39", "name": "Add ARM64 support for MSHV accelerator", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498484/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219144/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219144/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.microsoft.com header.i=@linux.microsoft.com\n header.a=rsa-sha256 header.s=default header.b=V/rqnTSf;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmjqg6Kxzz1yGH\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 03 Apr 2026 00:48:31 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8ILJ-0008Pj-6Q; Thu, 02 Apr 2026 09:44:17 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <aastharawat@linux.microsoft.com>)\n id 1w8IKv-0006PC-NZ; Thu, 02 Apr 2026 09:43:53 -0400", "from linux.microsoft.com ([13.77.154.182])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <aastharawat@linux.microsoft.com>)\n id 1w8HXu-0008SF-LC; Thu, 02 Apr 2026 08:53:17 -0400", "from localhost (unknown [131.107.147.136])\n by linux.microsoft.com (Postfix) with ESMTPSA id 3F91F20B7001;\n Thu, 2 Apr 2026 05:53:02 -0700 (PDT)" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 linux.microsoft.com 3F91F20B7001", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com;\n s=default; t=1775134382;\n bh=TMVtmh/ACGMIWBY0kUMfU5jbSQ2Sl8D1oMQaMBRtJhw=;\n h=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n b=V/rqnTSfmOR6z0ZVQiPSoIXMpj9rCQP2OP0mFwi1ui1/62kgIehYjU0wTBDgAmkim\n eHAq5jGTiaNh7fCm+oz7WNeBnsGZTPY/jau8JWP5t7HG1nOcaD5cONldAk/oJ2sYj3\n zxLkRGmqHl8mqWw9dvkKI1heGvyfXooSwXT7fa1M=", "From": "Aastha Rawat <aastharawat@linux.microsoft.com>", "Date": "Thu, 02 Apr 2026 12:52:33 +0000", "Subject": "[PATCH v2 06/14] accel/mshv: add arch-specific accelerator init hook", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260402-mshv_accel_arm64_supp-v2-6-754895c15e9e@linux.microsoft.com>", "References": "\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>", "In-Reply-To": "\n <20260402-mshv_accel_arm64_supp-v2-0-754895c15e9e@linux.microsoft.com>", "To": "qemu-devel@nongnu.org", "Cc": "Magnus Kulke <magnuskulke@linux.microsoft.com>,\n Wei Liu <wei.liu@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>,\n\t=?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= <berrange@redhat.com>, =?utf-8?q?Phil?=\n\t=?utf-8?q?ippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>,\n Anirudh Rayabharam <anirudh@anirudhrb.com>,\n Aastha Rawat <aastharawat@linux.microsoft.com>,\n Magnus Kulke <magnus.kulke@linux.microsoft.com>, qemu-arm@nongnu.org,\n Alexander Graf <agraf@csgraf.de>, Pedro Barbuda <pbarbuda@microsoft.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>", "X-Mailer": "b4 0.15.1", "Received-SPF": "pass client-ip=13.77.154.182;\n envelope-from=aastharawat@linux.microsoft.com; helo=linux.microsoft.com", "X-Spam_score_int": "-42", "X-Spam_score": "-4.3", "X-Spam_bar": "----", "X-Spam_report": "(-4.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: \"Anirudh Rayabharam (Microsoft)\" <anirudh@anirudhrb.com>\n\nIntroduce mshv_arch_accel_init() as an arch-specific hook called early\nin mshv_init(), before VM creation. This allows each architecture to\nperform platform-specific initialization at accelerator init time.\n\nFor arm64, the hook queries the hypervisor for the supported IPA bit\nsize and validates it against the guest memory map via the machine's\nget_physical_address_range callback, following the same pattern used by\nHVF and WHPX. This also populates the memory map which comes in handy\nlater when retreiving the vGIC layout.\n\nFor x86, the hook calls mshv_init_mmio_emu() which was previously called\ndirectly from the common init path. Also move set_unimplemented_msr_action()\nand mshv_arch_post_init_vm() from mshv-cpu.c to the new mshv-all.c, as\nthey are not vCPU-specific.\n\nSigned-off-by: Anirudh Rayabharam (Microsoft) <anirudh@anirudhrb.com>\n---\n accel/mshv/mshv-all.c | 5 ++-\n include/system/mshv_int.h | 1 +\n target/arm/mshv/mshv-all.c | 25 ++++++++++----\n target/i386/mshv/meson.build | 1 +\n target/i386/mshv/mshv-all.c | 80 ++++++++++++++++++++++++++++++++++++++++++++\n target/i386/mshv/mshv-cpu.c | 40 ----------------------\n 6 files changed, 105 insertions(+), 47 deletions(-)", "diff": "diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c\nindex 44f35a1463..6940ad9989 100644\n--- a/accel/mshv/mshv-all.c\n+++ b/accel/mshv/mshv-all.c\n@@ -434,7 +434,10 @@ static int mshv_init(AccelState *as, MachineState *ms)\n return -1;\n }\n \n- mshv_init_mmio_emu();\n+ ret = mshv_arch_accel_init(as, ms, mshv_fd);\n+ if (ret < 0) {\n+ return -1;\n+ }\n \n mshv_init_msicontrol();\n \ndiff --git a/include/system/mshv_int.h b/include/system/mshv_int.h\nindex ff3ab957b5..c72c91cd23 100644\n--- a/include/system/mshv_int.h\n+++ b/include/system/mshv_int.h\n@@ -96,6 +96,7 @@ void mshv_arch_init_vcpu(CPUState *cpu);\n void mshv_arch_destroy_vcpu(CPUState *cpu);\n void mshv_arch_amend_proc_features(\n union hv_partition_synthetic_processor_features *features);\n+int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd);\n int mshv_arch_post_init_vm(int vm_fd);\n void mshv_setup_hvcall_args(AccelCPUState *state);\n \ndiff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c\nindex db1174b444..8d16971c0d 100644\n--- a/target/arm/mshv/mshv-all.c\n+++ b/target/arm/mshv/mshv-all.c\n@@ -9,12 +9,13 @@\n * SPDX-License-Identifier: GPL-2.0-or-later\n */\n \n-\n #include \"qemu/osdep.h\"\n #include <sys/ioctl.h>\n \n #include \"qemu/error-report.h\"\n #include \"qemu/memalign.h\"\n+#include \"hw/arm/bsa.h\"\n+#include \"hw/arm/virt.h\"\n \n #include \"system/cpus.h\"\n #include \"target/arm/cpu.h\"\n@@ -188,11 +189,6 @@ void mshv_arch_destroy_vcpu(CPUState *cpu)\n state->hvcall_args = (MshvHvCallArgs){0};\n }\n \n-void mshv_init_mmio_emu(void)\n-{\n-\n-}\n-\n void mshv_arch_amend_proc_features(\n union hv_partition_synthetic_processor_features *features)\n {\n@@ -394,3 +390,20 @@ void mshv_arm_set_cpu_features_from_host(ARMCPU *cpu)\n cpu->midr = arm_host_cpu_features.midr;\n cpu->reset_sctlr = arm_host_cpu_features.reset_sctlr;\n }\n+\n+int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)\n+{\n+ MachineClass *mc = MACHINE_GET_CLASS(ms);\n+ int pa_range;\n+ uint32_t ipa_size;\n+\n+ if (mc->get_physical_address_range) {\n+ ipa_size = mshv_arm_get_ipa_bit_size(mshv_fd);\n+ pa_range = mc->get_physical_address_range(ms, ipa_size, ipa_size);\n+ if (pa_range < 0) {\n+ return -EINVAL;\n+ }\n+ }\n+\n+ return 0;\n+}\ndiff --git a/target/i386/mshv/meson.build b/target/i386/mshv/meson.build\nindex 6091c21887..ce54e134cb 100644\n--- a/target/i386/mshv/meson.build\n+++ b/target/i386/mshv/meson.build\n@@ -1,6 +1,7 @@\n i386_mshv_ss = ss.source_set()\n \n i386_mshv_ss.add(files(\n+ 'mshv-all.c',\n 'mshv-cpu.c',\n 'msr.c',\n ))\ndiff --git a/target/i386/mshv/mshv-all.c b/target/i386/mshv/mshv-all.c\nnew file mode 100644\nindex 0000000000..f0b43aa86f\n--- /dev/null\n+++ b/target/i386/mshv/mshv-all.c\n@@ -0,0 +1,80 @@\n+/*\n+ * QEMU MSHV support\n+ *\n+ * Copyright Microsoft, Corp. 2026\n+ *\n+ * Authors: Ziqiao Zhou <ziqiaozhou@microsoft.com>\n+ * Magnus Kulke <magnuskulke@microsoft.com>\n+ * Jinank Jain <jinankjain@microsoft.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/error-report.h\"\n+#include \"qemu/memalign.h\"\n+\n+#include \"system/mshv.h\"\n+#include \"system/mshv_int.h\"\n+#include \"system/address-spaces.h\"\n+#include \"linux/mshv.h\"\n+#include \"hw/hyperv/hvgdk.h\"\n+#include \"hw/hyperv/hvgdk_mini.h\"\n+#include \"hw/hyperv/hvhdk_mini.h\"\n+#include \"hw/i386/apic_internal.h\"\n+\n+#include \"cpu.h\"\n+#include \"emulate/x86_decode.h\"\n+#include \"emulate/x86_emu.h\"\n+#include \"emulate/x86_flags.h\"\n+\n+#include \"trace-accel_mshv.h\"\n+#include \"trace.h\"\n+\n+#include <sys/ioctl.h>\n+\n+int mshv_arch_accel_init(AccelState *as, MachineState *ms, int mshv_fd)\n+{\n+ mshv_init_mmio_emu();\n+ return 0;\n+}\n+\n+/*\n+ * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a\n+ * fault to the guest if it tries to access it. It is possible to override\n+ * this behavior with a more suitable option i.e., ignore writes from the guest\n+ * and return zero in attempt to read unimplemented.\n+ */\n+static int set_unimplemented_msr_action(int vm_fd)\n+{\n+ struct hv_input_set_partition_property in = {0};\n+ struct mshv_root_hvcall args = {0};\n+\n+ in.property_code = HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION;\n+ in.property_value = HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZERO;\n+\n+ args.code = HVCALL_SET_PARTITION_PROPERTY;\n+ args.in_sz = sizeof(in);\n+ args.in_ptr = (uint64_t)∈\n+\n+ trace_mshv_hvcall_args(\"unimplemented_msr_action\", args.code, args.in_sz);\n+\n+ int ret = mshv_hvcall(vm_fd, &args);\n+ if (ret < 0) {\n+ error_report(\"Failed to set unimplemented MSR action\");\n+ return -1;\n+ }\n+ return 0;\n+}\n+\n+int mshv_arch_post_init_vm(int vm_fd)\n+{\n+ int ret;\n+\n+ ret = set_unimplemented_msr_action(vm_fd);\n+ if (ret < 0) {\n+ error_report(\"Failed to set unimplemented MSR action\");\n+ }\n+\n+ return ret;\n+}\ndiff --git a/target/i386/mshv/mshv-cpu.c b/target/i386/mshv/mshv-cpu.c\nindex 9a80dc34d0..8325ac74a3 100644\n--- a/target/i386/mshv/mshv-cpu.c\n+++ b/target/i386/mshv/mshv-cpu.c\n@@ -1482,43 +1482,3 @@ void mshv_arch_destroy_vcpu(CPUState *cpu)\n state->hvcall_args = (MshvHvCallArgs){0};\n g_clear_pointer(&env->emu_mmio_buf, g_free);\n }\n-\n-/*\n- * Default Microsoft Hypervisor behavior for unimplemented MSR is to send a\n- * fault to the guest if it tries to access it. It is possible to override\n- * this behavior with a more suitable option i.e., ignore writes from the guest\n- * and return zero in attempt to read unimplemented.\n- */\n-static int set_unimplemented_msr_action(int vm_fd)\n-{\n- struct hv_input_set_partition_property in = {0};\n- struct mshv_root_hvcall args = {0};\n-\n- in.property_code = HV_PARTITION_PROPERTY_UNIMPLEMENTED_MSR_ACTION;\n- in.property_value = HV_UNIMPLEMENTED_MSR_ACTION_IGNORE_WRITE_READ_ZERO;\n-\n- args.code = HVCALL_SET_PARTITION_PROPERTY;\n- args.in_sz = sizeof(in);\n- args.in_ptr = (uint64_t)∈\n-\n- trace_mshv_hvcall_args(\"unimplemented_msr_action\", args.code, args.in_sz);\n-\n- int ret = mshv_hvcall(vm_fd, &args);\n- if (ret < 0) {\n- error_report(\"Failed to set unimplemented MSR action\");\n- return -1;\n- }\n- return 0;\n-}\n-\n-int mshv_arch_post_init_vm(int vm_fd)\n-{\n- int ret;\n-\n- ret = set_unimplemented_msr_action(vm_fd);\n- if (ret < 0) {\n- error_report(\"Failed to set unimplemented MSR action\");\n- }\n-\n- return ret;\n-}\n", "prefixes": [ "v2", "06/14" ] }