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GET /api/patches/2219139/?format=api
{ "id": 2219139, "url": "http://patchwork.ozlabs.org/api/patches/2219139/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402125234.1371897-8-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260402125234.1371897-8-max.chou@sifive.com>", "list_archive_url": null, "date": "2026-04-02T12:52:32", "name": "[v6,7/9] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7202ad3819abf61a61642b0483e4aef18eb05a37", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402125234.1371897-8-max.chou@sifive.com/mbox/", "series": [ { "id": 498485, "url": "http://patchwork.ozlabs.org/api/series/498485/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498485", "date": "2026-04-02T12:52:26", "name": "Add Zvfbfa extension support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498485/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219139/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219139/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=bFqOraMz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x1029.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "According to the Zvfbfa ISA spec (v0.1), improperly NaN-boxed\nf-register operands must substitute the BF16 canonical NaN instead of\nthe FP16 canonical NaN for some vector floating-point instructions.\n\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\n---\n target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------\n target/riscv/translate.c | 8 ++++++++\n 2 files changed, 17 insertions(+), 9 deletions(-)", "diff": "diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 4df9a40b44..03ae85796a 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -2319,17 +2319,17 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)\n */\n static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)\n {\n- switch (s->sew) {\n- case 1:\n- gen_check_nanbox_h(out, in);\n- break;\n- case 2:\n+ if (s->sew == MO_16) {\n+ if (s->altfmt) {\n+ gen_check_nanbox_h_bf16(out, in);\n+ } else {\n+ gen_check_nanbox_h(out, in);\n+ }\n+ } else if (s->sew == MO_32) {\n gen_check_nanbox_s(out, in);\n- break;\n- case 3:\n+ } else if (s->sew == MO_64) {\n tcg_gen_mov_i64(out, in);\n- break;\n- default:\n+ } else {\n g_assert_not_reached();\n }\n }\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 551581b8d8..81087e0a5d 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -214,6 +214,14 @@ static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)\n tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);\n }\n \n+static void gen_check_nanbox_h_bf16(TCGv_i64 out, TCGv_i64 in)\n+{\n+ TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);\n+ TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7fc0ull);\n+\n+ tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);\n+}\n+\n static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)\n {\n TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);\n", "prefixes": [ "v6", "7/9" ] }