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GET /api/patches/2219060/?format=api
{ "id": 2219060, "url": "http://patchwork.ozlabs.org/api/patches/2219060/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/453a9e248b8c2af50cf89912121605db07792dd5.1775122853.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<453a9e248b8c2af50cf89912121605db07792dd5.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-02T10:47:23", "name": "[v2,06/16] target/hexagon: add v68 HVX IEEE float arithmetic insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6289c66f60f7aed610a8eb073782bbeb9902f06e", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/453a9e248b8c2af50cf89912121605db07792dd5.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 498468, "url": "http://patchwork.ozlabs.org/api/series/498468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468", "date": "2026-04-02T10:47:20", "name": "hexagon: add missing HVX float instructions", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219060/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219060/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v2 06/16] target/hexagon: add v68 HVX IEEE float arithmetic\n insns", "Date": "Thu, 2 Apr 2026 03:47:23 -0700", "Message-Id": "\n <453a9e248b8c2af50cf89912121605db07792dd5.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Authority-Analysis": "v=2.4 cv=fdGgCkQF c=1 sm=1 tr=0 ts=69ce494f cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8\n 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score=0\n lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0\n malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604020097", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add HVX IEEE floating-point arithmetic instructions:\n- vmpy_sf_sf, vmpy_sf_hf, vmpy_hf_hf: multiply operations\n- vdmpy_sf_hf: dot-product multiply\n- vmpy_sf_hf_acc, vmpy_hf_hf_acc, vdmpy_sf_hf_acc: multiply-accumulate\n- vadd_sf_sf, vsub_sf_sf, vadd_sf_hf, vsub_sf_hf: add/sub with sf output\n- vadd_hf_hf, vsub_hf_hf: add/sub with hf output\n\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 1 +\n target/hexagon/mmvec/hvx_ieee_fp.h | 47 ++++++++++\n target/hexagon/mmvec/macros.h | 1 +\n target/hexagon/mmvec/mmvec.h | 2 +\n target/hexagon/attribs_def.h.inc | 4 +\n target/hexagon/arch.c | 8 ++\n target/hexagon/cpu.c | 3 +\n target/hexagon/mmvec/hvx_ieee_fp.c | 69 +++++++++++++++\n target/hexagon/hex_common.py | 1 +\n target/hexagon/imported/mmvec/encode_ext.def | 18 ++++\n target/hexagon/imported/mmvec/ext.idef | 93 ++++++++++++++++++++\n target/hexagon/meson.build | 1 +\n 12 files changed, 248 insertions(+)\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex d28beaa92f..5a008d1949 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -87,6 +87,7 @@ typedef struct CPUArchState {\n MemLog mem_log_stores[STORES_MAX];\n \n float_status fp_status;\n+ float_status hvx_fp_status;\n \n target_ulong llsc_addr;\n target_ulong llsc_val;\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nnew file mode 100644\nindex 0000000000..5577179abd\n--- /dev/null\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -0,0 +1,47 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXAGON_HVX_IEEE_H\n+#define HEXAGON_HVX_IEEE_H\n+\n+#include \"fpu/softfloat.h\"\n+\n+/* Hexagon canonical NaN */\n+#define FP32_DEF_NAN 0x7FFFFFFF\n+#define FP16_DEF_NAN 0x7FFF\n+\n+/*\n+ * IEEE - FP ADD/SUB/MPY instructions\n+ */\n+uint32_t fp_mult_sf_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+uint32_t fp_add_sf_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+uint32_t fp_sub_sf_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+\n+uint16_t fp_mult_hf_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+uint16_t fp_add_hf_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+uint16_t fp_sub_hf_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+\n+uint32_t fp_mult_sf_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+uint32_t fp_add_sf_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+uint32_t fp_sub_sf_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+\n+/*\n+ * IEEE - FP Accumulate instructions\n+ */\n+uint16_t fp_mult_hf_hf_acc(uint16_t a1, uint16_t a2, uint16_t acc,\n+ float_status *fp_status);\n+uint32_t fp_mult_sf_hf_acc(uint16_t a1, uint16_t a2, uint32_t acc,\n+ float_status *fp_status);\n+\n+/*\n+ * IEEE - FP Reduce instructions\n+ */\n+uint32_t fp_vdmpy(uint16_t a1, uint16_t a2, uint16_t a3, uint16_t a4,\n+ float_status *fp_status);\n+uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2, uint16_t a3,\n+ uint16_t a4, float_status *fp_status);\n+\n+#endif\ndiff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h\nindex c7840fbf2e..ac709d8993 100644\n--- a/target/hexagon/mmvec/macros.h\n+++ b/target/hexagon/mmvec/macros.h\n@@ -23,6 +23,7 @@\n #include \"mmvec/system_ext_mmvec.h\"\n #include \"accel/tcg/getpc.h\"\n #include \"accel/tcg/probe.h\"\n+#include \"mmvec/hvx_ieee_fp.h\"\n \n #ifndef QEMU_GENERATE\n #define VdV (*(MMVector *restrict)(VdV_void))\ndiff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h\nindex 52d470709c..eaedfe0d6d 100644\n--- a/target/hexagon/mmvec/mmvec.h\n+++ b/target/hexagon/mmvec/mmvec.h\n@@ -38,6 +38,8 @@ typedef union {\n int16_t h[MAX_VEC_SIZE_BYTES / 2];\n uint8_t ub[MAX_VEC_SIZE_BYTES / 1];\n int8_t b[MAX_VEC_SIZE_BYTES / 1];\n+ int32_t sf[MAX_VEC_SIZE_BYTES / 4]; /* single float (32-bit) */\n+ int16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* half float (16-bit) */\n } MMVector;\n \n typedef union {\ndiff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\nindex c85cd5d17c..d3c4bf6301 100644\n--- a/target/hexagon/attribs_def.h.inc\n+++ b/target/hexagon/attribs_def.h.inc\n@@ -175,6 +175,10 @@ DEF_ATTRIB(RESTRICT_LATEPRED, \"Predicate can not be used as a .new.\", \"\", \"\")\n \n /* HVX IEEE FP extension attributes */\n DEF_ATTRIB(HVX_IEEE_FP, \"HVX IEEE FP extension instruction\", \"\", \"\")\n+DEF_ATTRIB(HVX_IEEE_FP_ACC, \"HVX IEEE FP accumulate instruction\", \"\", \"\")\n+DEF_ATTRIB(HVX_IEEE_FP_OUT_16, \"HVX IEEE FP 16-bit output\", \"\", \"\")\n+DEF_ATTRIB(HVX_IEEE_FP_OUT_32, \"HVX IEEE FP 32-bit output\", \"\", \"\")\n+DEF_ATTRIB(CVI_VX_NO_TMP_LD, \"HVX multiply without tmp load\", \"\", \"\")\n \n /* Keep this as the last attribute: */\n DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\ndiff --git a/target/hexagon/arch.c b/target/hexagon/arch.c\nindex e17e714a6a..358aa71e03 100644\n--- a/target/hexagon/arch.c\n+++ b/target/hexagon/arch.c\n@@ -199,6 +199,10 @@ void arch_fpop_start(CPUHexagonState *env)\n set_float_rounding_mode(\n softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)],\n &env->fp_status);\n+ /*\n+ * No need to check env->hvx_fp_status, these instructions don't\n+ * raise exceptions nor interact with usr fields.\n+ */\n }\n \n #ifdef CONFIG_USER_ONLY\n@@ -232,6 +236,10 @@ void arch_fpop_end(CPUHexagonState *env, bool pkt_need_commit)\n SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE);\n SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE);\n }\n+ /*\n+ * No need to check env->hvx_fp_status, these instructions don't\n+ * raise exceptions nor interact with usr fields.\n+ */\n }\n \n int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjust,\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex d7f4df5f96..d6ca51f175 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -300,6 +300,9 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);\n /* Default NaN value: sign bit set, all frac bits set */\n set_float_default_nan_pattern(0b11111111, &env->fp_status);\n+\n+ set_default_nan_mode(1, &env->hvx_fp_status);\n+ set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status);\n }\n \n static void hexagon_cpu_disas_set_info(const CPUState *cs,\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nnew file mode 100644\nindex 0000000000..ceb32ce43b\n--- /dev/null\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -0,0 +1,69 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hvx_ieee_fp.h\"\n+\n+#define DEF_FP_INSN_2(name, rt, a1t, a2t, op) \\\n+ uint##rt##_t fp_##name(uint##a1t##_t a1, uint##a2t##_t a2, \\\n+ float_status *fp_status) { \\\n+ float##a1t f1 = make_float##a1t(a1); \\\n+ float##a2t f2 = make_float##a2t(a2); \\\n+ return (op); \\\n+ }\n+\n+#define DEF_FP_INSN_3(name, rt, a1t, a2t, a3t, op) \\\n+ uint##rt##_t fp_##name(uint##a1t##_t a1, uint##a2t##_t a2, \\\n+ uint##a3t##_t a3, float_status *fp_status) { \\\n+ float##a1t f1 = make_float##a1t(a1); \\\n+ float##a2t f2 = make_float##a2t(a2); \\\n+ float##a3t f3 = make_float##a3t(a3); \\\n+ return (op); \\\n+ }\n+\n+DEF_FP_INSN_2(mult_sf_sf, 32, 32, 32, float32_mul(f1, f2, fp_status))\n+DEF_FP_INSN_2(add_sf_sf, 32, 32, 32, float32_add(f1, f2, fp_status))\n+DEF_FP_INSN_2(sub_sf_sf, 32, 32, 32, float32_sub(f1, f2, fp_status))\n+\n+DEF_FP_INSN_2(mult_hf_hf, 16, 16, 16, float16_mul(f1, f2, fp_status))\n+DEF_FP_INSN_2(add_hf_hf, 16, 16, 16, float16_add(f1, f2, fp_status))\n+DEF_FP_INSN_2(sub_hf_hf, 16, 16, 16, float16_sub(f1, f2, fp_status))\n+\n+DEF_FP_INSN_2(mult_sf_hf, 32, 16, 16,\n+ float32_mul(float16_to_float32(f1, true, fp_status),\n+ float16_to_float32(f2, true, fp_status),\n+ fp_status))\n+DEF_FP_INSN_2(add_sf_hf, 32, 16, 16,\n+ float32_add(float16_to_float32(f1, true, fp_status),\n+ float16_to_float32(f2, true, fp_status),\n+ fp_status))\n+DEF_FP_INSN_2(sub_sf_hf, 32, 16, 16,\n+ float32_sub(float16_to_float32(f1, true, fp_status),\n+ float16_to_float32(f2, true, fp_status),\n+ fp_status))\n+\n+DEF_FP_INSN_3(mult_hf_hf_acc, 16, 16, 16, 16,\n+ float16_muladd(f1, f2, f3, 0, fp_status))\n+DEF_FP_INSN_3(mult_sf_hf_acc, 32, 16, 16, 32,\n+ float32_muladd(float16_to_float32(f1, true, fp_status),\n+ float16_to_float32(f2, true, fp_status),\n+ f3, 0, fp_status))\n+\n+uint32_t fp_vdmpy(uint16_t a1, uint16_t a2, uint16_t a3, uint16_t a4,\n+ float_status *fp_status)\n+{\n+ float32 prod1 = fp_mult_sf_hf(a1, a3, fp_status);\n+ float32 prod2 = fp_mult_sf_hf(a2, a4, fp_status);\n+ return fp_add_sf_sf(float32_val(prod1), float32_val(prod2), fp_status);\n+}\n+\n+uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2,\n+ uint16_t a3, uint16_t a4,\n+ float_status *fp_status)\n+{\n+ float32 red = fp_vdmpy(a1, a2, a3, a4, fp_status);\n+ return fp_add_sf_sf(float32_val(red), acc, fp_status);\n+}\ndiff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\nindex 32a61505ce..9e8bcfdcf0 100755\n--- a/target/hexagon/hex_common.py\n+++ b/target/hexagon/hex_common.py\n@@ -215,6 +215,7 @@ def need_env(tag):\n \"A_LOAD\" in attribdict[tag] or\n \"A_CVI_GATHER\" in attribdict[tag] or\n \"A_CVI_SCATTER\" in attribdict[tag] or\n+ \"A_HVX_IEEE_FP\" in attribdict[tag] or\n \"A_IMPLICIT_WRITES_USR\" in attribdict[tag])\n \n \ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 6d70086b5f..4ce87d09fd 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -804,5 +804,23 @@ DEF_ENC(V6_vmpyewuh, ICLASS_CJ\" 1 111 111 vvvvv PP 0 uuuuu 101 ddddd\")\n DEF_ENC(V6_vmpyowh, ICLASS_CJ\" 1 111 111 vvvvv PP 0 uuuuu 111 ddddd\")\n DEF_ENC(V6_vmpyuhvs,\"00011111110vvvvvPP1uuuuu111ddddd\")\n \n+/* IEEE FP multiply instructions */\n+DEF_ENC(V6_vmpy_sf_sf,\"00011111100vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vmpy_sf_hf,\"00011111100vvvvvPP1uuuuu010ddddd\")\n+DEF_ENC(V6_vmpy_hf_hf,\"00011111100vvvvvPP1uuuuu011ddddd\")\n+DEF_ENC(V6_vdmpy_sf_hf,\"00011111101vvvvvPP1uuuuu110ddddd\")\n+\n+/* IEEE FP multiply-accumulate instructions */\n+DEF_ENC(V6_vmpy_sf_hf_acc,\"00011100010vvvvvPP1uuuuu001xxxxx\")\n+DEF_ENC(V6_vmpy_hf_hf_acc,\"00011100010vvvvvPP1uuuuu010xxxxx\")\n+DEF_ENC(V6_vdmpy_sf_hf_acc,\"00011100010vvvvvPP1uuuuu011xxxxx\")\n+\n+/* IEEE FP add/sub instructions */\n+DEF_ENC(V6_vadd_sf_sf,\"00011111100vvvvvPP1uuuuu110ddddd\")\n+DEF_ENC(V6_vsub_sf_sf,\"00011111100vvvvvPP1uuuuu111ddddd\")\n+DEF_ENC(V6_vadd_sf_hf,\"00011111100vvvvvPP1uuuuu100ddddd\")\n+DEF_ENC(V6_vsub_sf_hf,\"00011111100vvvvvPP1uuuuu101ddddd\")\n+DEF_ENC(V6_vadd_hf_hf,\"00011111101vvvvvPP1uuuuu111ddddd\")\n+DEF_ENC(V6_vsub_hf_hf,\"00011111011vvvvvPP1uuuuu000ddddd\")\n \n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 03d31f6181..e800cda317 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -2895,9 +2895,102 @@ EXTINSN(V6_vprefixqw,\"Vd32.w=prefixsum(Qv4)\", ATTRIBS(A_EXTENSION,A_CVI,A_CVI_\n }\n } )\n \n+/* KVX - IEEE FP Instructions */\n \n+/* Single pipe, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_32), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n+/* Single pipe, 16-bit output */\n+#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n+/* Two pipes: P2 & P3, single output: P2, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* Two pipes: P2 & P3, two outputs, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/*\n+ * single pipe, accumulate instruction, produces 16-bit output, requires 16-bit\n+ * accumulate input\n+ */\n+#define ITERATOR_INSN_IEEE_FP_ACC_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_IEEE_FP_OUT_16,A_CVI_VX_NO_TMP_LD), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/*\n+ * single pipe, accumulate instruction, produces 32-bit output, requires 32-bit\n+ * accumulate input\n+ */\n+#define ITERATOR_INSN_IEEE_FP_ACC_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_ACC,A_HVX_IEEE_FP_OUT_32,A_CVI_VX_NO_TMP_LD), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* IEEE FP multiply instructions */\n+ITERATOR_INSN_IEEE_FP_DOUBLE_SINGLE_32(32, vmpy_sf_sf,\n+ \"Vd32.sf=vmpy(Vu32.sf,Vv32.sf)\", \"Vector IEEE mul: sf\",\n+ VdV.sf[i] = fp_mult_sf_sf(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf,\n+ \"Vdd32.sf=vmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE mul: hf widen to sf\",\n+ VddV.v[0].sf[i] = fp_mult_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = fp_mult_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16(16, vmpy_hf_hf, \"Vd32.hf=vmpy(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE mul: hf\",\n+ VdV.hf[i] = fp_mult_hf_hf(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_32(32, vdmpy_sf_hf, \"Vd32.sf=vdmpy(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE mul reduction: hf widen to sf\",\n+ VdV.sf[i] = fp_vdmpy(VuV.hf[2*i+1], VuV.hf[2*i], VvV.hf[2*i+1],\n+ VvV.hf[2*i], &env->hvx_fp_status))\n+\n+/* IEEE FP multiply-accumulate instructions */\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vmpy_sf_hf_acc,\n+ \"Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE fma: hf widen to sf\",\n+ VxxV.v[0].sf[i] = fp_mult_sf_hf_acc(VuV.hf[2*i], VvV.hf[2*i],\n+ VxxV.v[0].sf[i], &env->hvx_fp_status);\n+ VxxV.v[1].sf[i] = fp_mult_sf_hf_acc(VuV.hf[2*i+1], VvV.hf[2*i+1],\n+ VxxV.v[1].sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_ACC_16(16, vmpy_hf_hf_acc,\n+ \"Vx32.hf+=vmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE fma: hf\",\n+ VxV.hf[i] = fp_mult_hf_hf_acc(VuV.hf[i], VvV.hf[i], VxV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_ACC_32(32, vdmpy_sf_hf_acc,\n+ \"Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf)\", \"Vector IEEE fma reduce: hf widen to sf\",\n+ VxV.sf[i] = fp_vdmpy_acc(VxV.sf[i], VuV.hf[2*i+1], VuV.hf[2*i], VvV.hf[2*i+1],\n+ VvV.hf[2*i], &env->hvx_fp_status))\n+\n+/* IEEE FP add/sub instructions */\n+ITERATOR_INSN_IEEE_FP_32(32, vadd_sf_sf, \"Vd32.sf=vadd(Vu32.sf,Vv32.sf)\",\n+ \"Vector IEEE add: sf\",\n+ VdV.sf[i] = fp_add_sf_sf(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_32(32, vsub_sf_sf, \"Vd32.sf=vsub(Vu32.sf,Vv32.sf)\",\n+ \"Vector IEEE sub: sf\",\n+ VdV.sf[i] = fp_sub_sf_sf(VuV.sf[i], VvV.sf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16(16, vadd_hf_hf, \"Vd32.hf=vadd(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE add: hf\",\n+ VdV.hf[i] = fp_add_hf_hf(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16(16, vsub_hf_hf, \"Vd32.hf=vsub(Vu32.hf,Vv32.hf)\",\n+ \"Vector IEEE sub: hf\",\n+ VdV.hf[i] = fp_sub_hf_hf(VuV.hf[i], VvV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vadd_sf_hf,\n+ \"Vdd32.sf=vadd(Vu32.hf,Vv32.hf)\", \"Vector IEEE add: hf widen to sf\",\n+ VddV.v[0].sf[i] = fp_add_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = fp_add_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf,\n+ \"Vdd32.sf=vsub(Vu32.hf,Vv32.hf)\", \"Vector IEEE sub: hf widen to sf\",\n+ VddV.v[0].sf[i] = fp_sub_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = fp_sub_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->hvx_fp_status))\n \n /******************************************************************************\n DEBUG Vector/Register Printing\ndiff --git a/target/hexagon/meson.build b/target/hexagon/meson.build\nindex d169cf71b2..9195014821 100644\n--- a/target/hexagon/meson.build\n+++ b/target/hexagon/meson.build\n@@ -250,6 +250,7 @@ hexagon_ss.add(files(\n 'fma_emu.c',\n 'mmvec/decode_ext_mmvec.c',\n 'mmvec/system_ext_mmvec.c',\n+ 'mmvec/hvx_ieee_fp.c',\n ))\n \n #\n", "prefixes": [ "v2", "06/16" ] }