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GET /api/patches/2219058/?format=api
{ "id": 2219058, "url": "http://patchwork.ozlabs.org/api/patches/2219058/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/c257371d4d0bdc12ed4c0319ddcbc1b6d8954f80.1775122853.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<c257371d4d0bdc12ed4c0319ddcbc1b6d8954f80.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-02T10:47:21", "name": "[v2,04/16] hexagon: group cpu configurations in their own struct", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "26ea5c655d2a38ecce9ddea56cc0a310ee537ac3", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/c257371d4d0bdc12ed4c0319ddcbc1b6d8954f80.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 498468, "url": "http://patchwork.ozlabs.org/api/series/498468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468", "date": "2026-04-02T10:47:20", "name": "hexagon: add missing HVX float instructions", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219058/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219058/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v2 04/16] hexagon: group cpu configurations in their own\n struct", "Date": "Thu, 2 Apr 2026 03:47:21 -0700", "Message-Id": "\n <c257371d4d0bdc12ed4c0319ddcbc1b6d8954f80.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Authority-Analysis": "v=2.4 cv=fdGgCkQF c=1 sm=1 tr=0 ts=69ce494c cx=c_pps\n a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8\n 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score=0\n lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0\n malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604020097", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This will be used in a follow up commit.\n\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 10 +++-------\n target/hexagon/cpu_bits.h | 7 +++++++\n target/hexagon/cpu.c | 14 +++++++-------\n target/hexagon/translate.c | 6 +++---\n 4 files changed, 20 insertions(+), 17 deletions(-)", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 77822a48b6..d28beaa92f 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -119,19 +119,15 @@ typedef struct HexagonCPUClass {\n ResettablePhases parent_phases;\n } HexagonCPUClass;\n \n+#include \"cpu_bits.h\"\n+\n struct ArchCPU {\n CPUState parent_obj;\n \n CPUHexagonState env;\n-\n- bool lldb_compat;\n- target_ulong lldb_stack_adjust;\n- bool short_circuit;\n- bool ieee_fp_extension;\n+ HexagonCPUConfig cfg;\n };\n \n-#include \"cpu_bits.h\"\n-\n FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)\n \n G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,\ndiff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 19beca81c0..83d13de569 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -20,6 +20,13 @@\n \n #include \"qemu/bitops.h\"\n \n+typedef struct HexagonCPUConfig {\n+ bool lldb_compat;\n+ uint32_t lldb_stack_adjust;\n+ bool short_circuit;\n+ bool ieee_fp_extension;\n+} HexagonCPUConfig;\n+\n #define PCALIGN 4\n #define PCALIGN_MASK (PCALIGN - 1)\n \ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 8b72a5d3c8..5470d9c7ce 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -50,11 +50,11 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n }\n \n static const Property hexagon_cpu_properties[] = {\n- DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n- DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n- qdev_prop_uint32, target_ulong),\n- DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n- DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n+ DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, cfg.lldb_compat, false),\n+ DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, cfg.lldb_stack_adjust,\n+ 0, qdev_prop_uint32, target_ulong),\n+ DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, cfg.short_circuit, true),\n+ DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, cfg.ieee_fp_extension, true),\n };\n \n const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n@@ -77,7 +77,7 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\n static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)\n {\n HexagonCPU *cpu = env_archcpu(env);\n- target_ulong stack_adjust = cpu->lldb_stack_adjust;\n+ target_ulong stack_adjust = cpu->cfg.lldb_stack_adjust;\n target_ulong stack_start = env->stack_start;\n target_ulong stack_size = 0x10000;\n \n@@ -181,7 +181,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)\n {\n HexagonCPU *cpu = env_archcpu(env);\n \n- if (cpu->lldb_compat) {\n+ if (cpu->cfg.lldb_compat) {\n /*\n * When comparing with LLDB, it doesn't step through single-cycle\n * hardware loops the same way. So, we just skip them here\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex fa8f615a9e..ce3af96675 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -987,8 +987,8 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->num_hvx_insns = 0;\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n- ctx->short_circuit = hex_cpu->short_circuit;\n- ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n+ ctx->short_circuit = hex_cpu->cfg.short_circuit;\n+ ctx->ieee_fp_extension = hex_cpu->cfg.ieee_fp_extension;\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n@@ -1041,7 +1041,7 @@ static void hexagon_tr_translate_packet(DisasContextBase *dcbase, CPUState *cpu)\n * so end the TLB after every packet.\n */\n HexagonCPU *hex_cpu = env_archcpu(env);\n- if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n+ if (hex_cpu->cfg.lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) {\n ctx->base.is_jmp = DISAS_TOO_MANY;\n }\n }\n", "prefixes": [ "v2", "04/16" ] }