Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2219052/?format=api
{ "id": 2219052, "url": "http://patchwork.ozlabs.org/api/patches/2219052/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/b9f7a06aedb453f9bc8df21d42f5026472ffbc26.1775122853.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<b9f7a06aedb453f9bc8df21d42f5026472ffbc26.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-02T10:47:26", "name": "[v2,09/16] target/hexagon: add v68 HVX IEEE float conversion insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "efa91ae84a7f24c371c6cb20c50ddfcd2d686e1f", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/b9f7a06aedb453f9bc8df21d42f5026472ffbc26.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 498468, "url": "http://patchwork.ozlabs.org/api/series/498468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468", "date": "2026-04-02T10:47:20", "name": "hexagon: add missing HVX float instructions", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219052/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219052/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ghgO341L;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=OxCCGJkv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmdrk6kVnz1yGH\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 21:49:10 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8Fag-0004jp-4x; Thu, 02 Apr 2026 06:47:58 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <matheus.bernardino@oss.qualcomm.com>)\n id 1w8FaZ-0004gf-61\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 06:47:51 -0400", "from mx0a-0031df01.pphosted.com ([205.220.168.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <matheus.bernardino@oss.qualcomm.com>)\n id 1w8FaV-0007oT-MT\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 06:47:50 -0400", "from pps.filterd (m0279864.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6326w5KS4010110\n for <qemu-devel@nongnu.org>; Thu, 2 Apr 2026 10:47:46 GMT", "from mail-dy1-f197.google.com (mail-dy1-f197.google.com\n [74.125.82.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d97e03jy0-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <qemu-devel@nongnu.org>; Thu, 02 Apr 2026 10:47:46 +0000 (GMT)", "by mail-dy1-f197.google.com with SMTP id\n 5a478bee46e88-2bdf75bc88fso825521eec.0\n for <qemu-devel@nongnu.org>; Thu, 02 Apr 2026 03:47:46 -0700 (PDT)", "from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n 5a478bee46e88-2ca7d00f5easm2004783eec.29.2026.04.02.03.47.44\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 02 Apr 2026 03:47:44 -0700 (PDT)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=3PB+fajE6hK\n x1JiZo+b7XWJ8ECYSiC+34vAh9YpHzhg=; b=ghgO341La5i62AjSVT9JlP4jmCx\n zCyK1m+E6ewZOdwmZ1H+LPGlSGgBDC2xEcl0tUuQdVDqvC8nmw0tkxNhnhZMNqRQ\n osF2GaS686+WpB3IzvQfhzGN00z4XKYovK9LaLP7njylcbhhIfSJM3L0VXlcxXnT\n GlSYVgnxUJIY6VPzDmtHGBP/l3AFw3bCaos7MP9xrIqou1FqXT79Bhc/rw6CA+69\n QB+3Mnr53S65eH4jkZ/W830lV6cJGpaW3aKm/ALSif1iIWR3GZr0zZhNYcI/HLBJ\n qp5ed+u7OsYQZhisLtDJ/cDGuL93xRx2R467n4E5pxqKpLsZSnxGGMfoMcw==", "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775126865; x=1775731665; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=3PB+fajE6hKx1JiZo+b7XWJ8ECYSiC+34vAh9YpHzhg=;\n b=OxCCGJkvFpUN751NwQ2AF3pE2X/hejDw43lN+4MTHrsvzVvxxOOxam+YsRqbEDyYmR\n h0hY0FTLm2py2wAAYMVR2kHdNxFFPm1qqahUQctNcW/QxaZBL3DfR9vRZH2nL5BPBEoc\n 6ApAzJ7FS+9CY5NX5zCsL42jKSw3WRX9S12qi4G84cezV+gJ6rNOzRKAW6WpzuOEfx3a\n G/CHbRMX/cqHqQBWpIQ48O0pInjThkMQDCB4Ac/R1dTNgTIu1tRgnEbN2fRXpbZBCogN\n 0b6+1f05EdhW4JxFtILbVoHd/rWvDs/+GKcvktxAGszLKTT82TK7/iRL/hElqTA4/QVb\n 1vaA==" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775126865; x=1775731665;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=3PB+fajE6hKx1JiZo+b7XWJ8ECYSiC+34vAh9YpHzhg=;\n b=cFTvHY0oAyJPpSnNdSYbBLt4tuB06iF1s3Qmom7hSdhayjS3xHj3DqS6n4gRAbL4aN\n nVuCmSPTDUSuLavwGnblDnb9yeuA5OwphADUuf5YXGqwMj8uDWAYQwB2e8aYn6V/FH8m\n TuiXjUx9n9VNtGUrRPK3OGhygwz68zywr/M6wwDQaTQ0UiqrOvr+VTwI2QozKCk9hSYj\n oWulgTSFeDA2mgKt2AP+jUXimxi4IwxZz7iBUGTIGNNFb51a4MkcTBPjdEaTbPbNrzMw\n o9rhKuva7vlL6yehVoY7SKkX866AT3TaVWQaYUDeVjtkbNWi8XZrNsIr5KOKIgA8cVSf\n i/kQ==", "X-Gm-Message-State": "AOJu0YwdOU3NqYIbGHEY3uPbt8bTy170krFFZst2TId+4bMSab9nXc5S\n K7rELMvUYyiuAX0V6SiN8YzNr02+OkI1L+OmXA0TVvN/5IVtQe4covfM9uKxFi/BjjI57L5eC4D\n gXXmaWa/ywL+fmLGy9qrMLB8AGS793TaPWzhBz5urwp7Gng7+8bWyqG9SHkllHPLrk8t3", "X-Gm-Gg": "ATEYQzxNBJBG/mj0YZcOhA7DPblScuCaXQyl1usyN+IsPgtg6FZj1JY2KxGki46HMgL\n tw6UZ2EbIV5cfNZjCBVeSwwjMi95gmVpKpUFofuBPIkofz/4Jw9eQc+VieApXOflbWXwpWV3H0O\n +9hGQ03liKbZrawW0FeTElBiO5ZC6hCO252lX0lyypkYbdFLsfgYeNWB4m4CV27TReOgefjO+j9\n /fMDuCqeD3jPfCEtv3fBKdj5wR156RXkmPu2+6hn+Y6KkK3jhuIFFZ+gJTJh+PdjTfbPULifVJ0\n jUMf74bcPT1QWs+qU3n+0kmgxdUFhxGU8MRFO6zG1vN7MlZ+g1kc2RCRFp6lNZMqXvUDTNKwFM1\n Ab7rId7qF+PZDfIiTHV5ZCmCMxRQHINbKx9rmkmPqL3Wjy8Lcrt6HZdd/WkblRGXHf8RVmu0yvO\n uKHoBhjeRy", "X-Received": [ "by 2002:a05:7301:fa0d:b0:2c1:85a:d25d with SMTP id\n 5a478bee46e88-2c930e6bc1emr3630270eec.1.1775126865181;\n Thu, 02 Apr 2026 03:47:45 -0700 (PDT)", "by 2002:a05:7301:fa0d:b0:2c1:85a:d25d with SMTP id\n 5a478bee46e88-2c930e6bc1emr3630251eec.1.1775126864614;\n Thu, 02 Apr 2026 03:47:44 -0700 (PDT)" ], "From": "Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v2 09/16] target/hexagon: add v68 HVX IEEE float conversion\n insns", "Date": "Thu, 2 Apr 2026 03:47:26 -0700", "Message-Id": "\n <b9f7a06aedb453f9bc8df21d42f5026472ffbc26.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Authority-Analysis": "v=2.4 cv=fdGgCkQF c=1 sm=1 tr=0 ts=69ce4952 cx=c_pps\n a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8\n a=0QsP6ROi4U8MYujRKJUA:9 a=PxkB5W3o20Ba91AHUih5:22", "X-Proofpoint-ORIG-GUID": "OZlH77gEeTFi41fSFZWzM5CudxbZFM42", "X-Proofpoint-GUID": "OZlH77gEeTFi41fSFZWzM5CudxbZFM42", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAyMDA5NyBTYWx0ZWRfX8/ByERKflPEx\n 15smUxWMVFPHItj8Uzzvv+glQjxWSyG3d2AzWWSeC5yCR73thI746AEsuX/VtUkgOHLaISUSARC\n ZmXCklSPydPg2cx7Z0JX/RqePKrUXP37MlRpxPRe54lMveapjov8yYdgu27ouHqkYvBt9e4yBQI\n i7Mg32r+s8Irq0in4UmtCjMBEZxbIRh1JFXHSC18llCHsdVLMGaWkMIE54x2zp3C6X3cgidBr3F\n cc2RMw+iPJ1pVOIt1LC6aZXqnqD01pTsbmjCfCmK8MdJTWSQPhGzPkCsDBg/UKnSMmarvu3ZYOP\n tz3vcjLeuO8Nr15TgQodYtDORrJoRMMrD894y2im/sfaqAWBhk5AkPzJpS/kwP+hOkAGIvzRel6\n xYxwPSUJ6sqzXagvq8jMpQ9mtJj/Y9ViXtwaxl4d+CBZH12rqP72K6ndMmm9q0HPO28HeW1ItQ+\n IZvpvU/+QxzReghWVCw==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-02_01,2026-04-02_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 clxscore=1015 priorityscore=1501 adultscore=0\n malwarescore=0 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604020097", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add HVX IEEE floating-point conversion instructions:\n- vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations\n- vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions\n- vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float\n- vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int\n\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 21 +++++\n target/hexagon/mmvec/hvx_ieee_fp.c | 88 ++++++++++++++++++\n target/hexagon/imported/mmvec/encode_ext.def | 18 ++++\n target/hexagon/imported/mmvec/ext.idef | 97 ++++++++++++++++++++\n 4 files changed, 224 insertions(+)", "diff": "diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex f4801e3be9..e73f8161b1 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -56,4 +56,25 @@ uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n \n+/*\n+ * IEEE - FP Convert instructions\n+ */\n+uint16_t f32_to_f16(uint32_t a, float_status *fp_status);\n+uint32_t f16_to_f32(uint16_t a, float_status *fp_status);\n+\n+uint16_t f16_to_uh(uint16_t op1, float_status *fp_status);\n+int16_t f16_to_h(uint16_t op1, float_status *fp_status);\n+uint8_t f16_to_ub(uint16_t op1, float_status *fp_status);\n+int8_t f16_to_b(uint16_t op1, float_status *fp_status);\n+\n+uint16_t uh_to_f16(uint16_t op1);\n+uint16_t h_to_f16(int16_t op1);\n+uint16_t ub_to_f16(uint8_t op1);\n+uint16_t b_to_f16(int8_t op1);\n+\n+int32_t conv_sf_w(int32_t a, float_status *fp_status);\n+int16_t conv_hf_h(int16_t a, float_status *fp_status);\n+int32_t conv_w_sf(uint32_t a, float_status *fp_status);\n+int16_t conv_h_hf(uint16_t a, float_status *fp_status);\n+\n #endif\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nindex 086e8dd29e..d39a883ab7 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.c\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -129,3 +129,91 @@ uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status)\n }\n return fp_min_hf(a1, a2, fp_status);\n }\n+\n+uint16_t f32_to_f16(uint32_t a, float_status *fp_status)\n+{\n+ return float16_val(float32_to_float16(make_float32(a), true, fp_status));\n+}\n+\n+uint32_t f16_to_f32(uint16_t a, float_status *fp_status)\n+{\n+ return float32_val(float16_to_float32(make_float16(a), true, fp_status));\n+}\n+\n+uint16_t f16_to_uh(uint16_t op1, float_status *fp_status)\n+{\n+ return float16_to_uint16_scalbn(make_float16(op1),\n+ float_round_nearest_even,\n+ 0, fp_status);\n+}\n+\n+int16_t f16_to_h(uint16_t op1, float_status *fp_status)\n+{\n+ return float16_to_int16_scalbn(make_float16(op1),\n+ float_round_nearest_even,\n+ 0, fp_status);\n+}\n+\n+uint8_t f16_to_ub(uint16_t op1, float_status *fp_status)\n+{\n+ return float16_to_uint8_scalbn(make_float16(op1),\n+ float_round_nearest_even,\n+ 0, fp_status);\n+}\n+\n+int8_t f16_to_b(uint16_t op1, float_status *fp_status)\n+{\n+ return float16_to_int8_scalbn(make_float16(op1),\n+ float_round_nearest_even,\n+ 0, fp_status);\n+}\n+\n+uint16_t uh_to_f16(uint16_t op1)\n+{\n+ return uint64_to_float16_scalbn(op1, float_round_nearest_even, 0);\n+}\n+\n+uint16_t h_to_f16(int16_t op1)\n+{\n+ return int64_to_float16_scalbn(op1, float_round_nearest_even, 0);\n+}\n+\n+uint16_t ub_to_f16(uint8_t op1)\n+{\n+ return uint64_to_float16_scalbn(op1, float_round_nearest_even, 0);\n+}\n+\n+uint16_t b_to_f16(int8_t op1)\n+{\n+ return int64_to_float16_scalbn(op1, float_round_nearest_even, 0);\n+}\n+\n+int32_t conv_sf_w(int32_t a, float_status *fp_status)\n+{\n+ return float32_val(int32_to_float32(a, fp_status));\n+}\n+\n+int16_t conv_hf_h(int16_t a, float_status *fp_status)\n+{\n+ return float16_val(int16_to_float16(a, fp_status));\n+}\n+\n+int32_t conv_w_sf(uint32_t a, float_status *fp_status)\n+{\n+ float32 f1 = make_float32(a);\n+ /* float32_to_int32 converts any NaN to MAX, hexagon looks at the sign. */\n+ if (float32_is_any_nan(f1)) {\n+ return float32_is_neg(f1) ? INT32_MIN : INT32_MAX;\n+ }\n+ return float32_to_int32_round_to_zero(f1, fp_status);\n+}\n+\n+int16_t conv_h_hf(uint16_t a, float_status *fp_status)\n+{\n+ float16 f1 = make_float16(a);\n+ /* float16_to_int16 converts any NaN to MAX, hexagon looks at the sign. */\n+ if (float16_is_any_nan(f1)) {\n+ return float16_is_neg(f1) ? INT16_MIN : INT16_MAX;\n+ }\n+ return float16_to_int16_round_to_zero(f1, fp_status);\n+}\ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 72daf8724c..c1ed1b6c23 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -840,4 +840,22 @@ DEF_ENC(V6_vfneg_sf,\"00011110--0-0110PP1uuuuu011ddddd\")\n DEF_ENC(V6_vabs_hf,\"00011110--0-0110PP1uuuuu100ddddd\")\n DEF_ENC(V6_vabs_sf,\"00011110--0-0110PP1uuuuu101ddddd\")\n \n+/* IEEE FP vcvt instructions */\n+DEF_ENC(V6_vcvt_sf_hf,\"00011110--0-0100PP1uuuuu100ddddd\")\n+DEF_ENC(V6_vcvt_hf_sf,\"00011111011vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vcvt_hf_ub,\"00011110--0-0100PP1uuuuu001ddddd\")\n+DEF_ENC(V6_vcvt_hf_b,\"00011110--0-0100PP1uuuuu010ddddd\")\n+DEF_ENC(V6_vcvt_hf_uh,\"00011110--0-0100PP1uuuuu101ddddd\")\n+DEF_ENC(V6_vcvt_hf_h,\"00011110--0-0100PP1uuuuu111ddddd\")\n+DEF_ENC(V6_vcvt_uh_hf,\"00011110--0--101PP1uuuuu000ddddd\")\n+DEF_ENC(V6_vcvt_h_hf,\"00011110--0-0110PP1uuuuu000ddddd\")\n+DEF_ENC(V6_vcvt_ub_hf,\"00011111110vvvvvPP1uuuuu101ddddd\")\n+DEF_ENC(V6_vcvt_b_hf,\"00011111110vvvvvPP1uuuuu110ddddd\")\n+\n+/* IEEE FP vconv instructions */\n+DEF_ENC(V6_vconv_sf_w,\"00011110--0--101PP1uuuuu011ddddd\")\n+DEF_ENC(V6_vconv_w_sf,\"00011110--0--101PP1uuuuu001ddddd\")\n+DEF_ENC(V6_vconv_hf_h,\"00011110--0--101PP1uuuuu100ddddd\")\n+DEF_ENC(V6_vconv_h_hf,\"00011110--0--101PP1uuuuu010ddddd\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 54bed47083..6d5bab0894 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -63,6 +63,9 @@ ITERATOR_INSN_ANY_SLOT_DOUBLE_VEC(WIDTH,TAG,SYNTAX2,DESCR,CODE)\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS), \\\n DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n+#define ITERATOR_INSN_SHIFT_SLOT_FLT(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_HVX_FLT), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n #define ITERATOR_INSN_SHIFT3_SLOT(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_CVI_VS_3SRC,A_NOTE_SHIFT_RESOURCE,A_NOTE_NOVP,A_NOTE_VA_UNARY), \\\n@@ -3038,6 +3041,100 @@ ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, \"Vd32.hf=vabs(Vu32.hf)\", \\\n ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, \"Vd32.sf=vabs(Vu32.sf)\", \\\n \"Vector IEEE abs: sf\", VdV.hf[i] = float32_abs(VuV.hf[i]))\n \n+/* Two pipes: P2 & P3, two outputs, 16-bit */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_16), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* Two pipes: P2 & P3, two outputs, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* Single pipe, 16-bit output */\n+#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* single pipe, output can feed 16- or 32-bit accumulate */\n+#define ITERATOR_INSN_IEEE_FP_16_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,A_HVX_IEEE_FP_OUT_32), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/******************************************************************************\n+ * IEEE FP convert instructions\n+ ******************************************************************************/\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_ub, \"Vdd32.hf=vcvt(Vu32.ub)\",\n+ \"Vector IEEE cvt from int: ub widen to hf\",\n+ VddV.v[0].hf[2*i] = ub_to_f16(VuV.ub[4*i]);\n+ VddV.v[0].hf[2*i+1] = ub_to_f16(VuV.ub[4*i+1]);\n+ VddV.v[1].hf[2*i] = ub_to_f16(VuV.ub[4*i+2]);\n+ VddV.v[1].hf[2*i+1] = ub_to_f16(VuV.ub[4*i+3]))\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_b, \"Vdd32.hf=vcvt(Vu32.b)\",\n+ \"Vector IEEE cvt from int: b widen to hf\",\n+ VddV.v[0].hf[2*i] = b_to_f16(VuV.b[4*i]);\n+ VddV.v[0].hf[2*i+1] = b_to_f16(VuV.b[4*i+1]);\n+ VddV.v[1].hf[2*i] = b_to_f16(VuV.b[4*i+2]);\n+ VddV.v[1].hf[2*i+1] = b_to_f16(VuV.b[4*i+3]))\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vcvt_sf_hf, \"Vdd32.sf=vcvt(Vu32.hf)\",\n+ \"Vector IEEE cvt: hf widen to sf\",\n+ VddV.v[0].sf[i] = f16_to_f32(VuV.hf[2*i], &env->hvx_fp_status);\n+ VddV.v[1].sf[i] = f16_to_f32(VuV.hf[2*i+1], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_uh, \"Vd32.hf=vcvt(Vu32.uh)\",\n+ \"Vector IEEE cvt from int: uh to hf\",\n+ VdV.hf[i] = uh_to_f16(VuV.uh[i]))\n+ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_h, \"Vd32.hf=vcvt(Vu32.h)\",\n+ \"Vector IEEE cvt from int: h to hf\",\n+ VdV.hf[i] = h_to_f16(VuV.h[i]))\n+ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_uh_hf, \"Vd32.uh=vcvt(Vu32.hf)\",\n+ \"Vector IEEE cvt to int: hf to uh\",\n+ VdV.uh[i] = f16_to_uh(VuV.hf[i], &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_h_hf, \"Vd32.h=vcvt(Vu32.hf)\",\n+ \"Vector IEEE cvt to int: hf to h\",\n+ VdV.h[i] = f16_to_h(VuV.hf[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_IEEE_FP_16(32, vcvt_hf_sf, \"Vd32.hf=vcvt(Vu32.sf,Vv32.sf)\",\n+ \"Vector IEEE cvt: sf to hf\",\n+ VdV.hf[2*i] = f32_to_f16(VuV.sf[i], &env->hvx_fp_status);\n+ VdV.hf[2*i+1] = f32_to_f16(VvV.sf[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_ub_hf, \"Vd32.ub=vcvt(Vu32.hf,Vv32.hf)\", \"Vector cvt to int: hf narrow to ub\",\n+ VdV.ub[4*i] = f16_to_ub(VuV.hf[2*i], &env->hvx_fp_status);\n+ VdV.ub[4*i+1] = f16_to_ub(VuV.hf[2*i+1], &env->hvx_fp_status);\n+ VdV.ub[4*i+2] = f16_to_ub(VvV.hf[2*i], &env->hvx_fp_status);\n+ VdV.ub[4*i+3] = f16_to_ub(VvV.hf[2*i+1], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_b_hf, \"Vd32.b=vcvt(Vu32.hf,Vv32.hf)\",\n+ \"Vector cvt to int: hf narrow to b\",\n+ VdV.b[4*i] = f16_to_b(VuV.hf[2*i], &env->hvx_fp_status);\n+ VdV.b[4*i+1] = f16_to_b(VuV.hf[2*i+1], &env->hvx_fp_status);\n+ VdV.b[4*i+2] = f16_to_b(VvV.hf[2*i], &env->hvx_fp_status);\n+ VdV.b[4*i+3] = f16_to_b(VvV.hf[2*i+1], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_w_sf,\"Vd32.w=Vu32.sf\",\n+ \"Vector conversion of sf32 format to int w\",\n+ VdV.w[i] = conv_w_sf(VuV.sf[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,\"Vd32.h=Vu32.hf\",\n+ \"Vector conversion of hf16 format to int hw\",\n+ VdV.h[i] = conv_h_hf(VuV.hf[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,\"Vd32.sf=Vu32.w\",\n+ \"Vector conversion of int w format to sf32\",\n+ VdV.sf[i] = conv_sf_w(VuV.w[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n+ \"Vector conversion of int hw format to hf16\",\n+ VdV.hf[i] = conv_hf_h(VuV.h[i], &env->hvx_fp_status))\n+\n /******************************************************************************\n DEBUG Vector/Register Printing\n ******************************************************************************/\n", "prefixes": [ "v2", "09/16" ] }