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GET /api/patches/2219045/?format=api
{ "id": 2219045, "url": "http://patchwork.ozlabs.org/api/patches/2219045/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/d8a52cb351422b6adf0252f181bd737f31b2372d.1775122853.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<d8a52cb351422b6adf0252f181bd737f31b2372d.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-02T10:47:24", "name": "[v2,07/16] target/hexagon: add v68 HVX IEEE float min/max insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "25992e27b5fb196bd2be7cd1be4b969e6c162361", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/d8a52cb351422b6adf0252f181bd737f31b2372d.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 498468, "url": "http://patchwork.ozlabs.org/api/series/498468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468", "date": "2026-04-02T10:47:20", "name": "hexagon: add missing HVX float instructions", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219045/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v2 07/16] target/hexagon: add v68 HVX IEEE float min/max insns", "Date": "Thu, 2 Apr 2026 03:47:24 -0700", "Message-Id": "\n <d8a52cb351422b6adf0252f181bd737f31b2372d.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "eXXoUpgHSdauE89wE7-Zb36mzRZnAyT1", "X-Proofpoint-ORIG-GUID": "eXXoUpgHSdauE89wE7-Zb36mzRZnAyT1", "X-Authority-Analysis": "v=2.4 cv=JII2csKb c=1 sm=1 tr=0 ts=69ce494f cx=c_pps\n a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 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adultscore=0 impostorscore=0 phishscore=0 priorityscore=1501\n lowpriorityscore=0 spamscore=0 clxscore=1015 bulkscore=0 suspectscore=0\n malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604020097", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add HVX IEEE floating-point min/max instructions:\n- vfmin_hf, vfmin_sf: IEEE floating-point minimum\n- vfmax_hf, vfmax_sf: IEEE floating-point maximum\n- vmax_hf, vmax_sf: qfloat IEEE maximum\n- vmin_hf, vmin_sf: qfloat IEEE minimum\n\nThe Hexagon qfloat variants are similar to the IEEE-754 ones, but they\nhandle NaN slightly differently. See comment on hvx_ieee_fp.h\n\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 12 ++++\n target/hexagon/mmvec/hvx_ieee_fp.c | 62 ++++++++++++++++++++\n target/hexagon/imported/mmvec/encode_ext.def | 10 ++++\n target/hexagon/imported/mmvec/ext.idef | 36 +++++++++++-\n 4 files changed, 119 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex 5577179abd..f4801e3be9 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -44,4 +44,16 @@ uint32_t fp_vdmpy(uint16_t a1, uint16_t a2, uint16_t a3, uint16_t a4,\n uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2, uint16_t a3,\n uint16_t a4, float_status *fp_status);\n \n+/* IEEE - FP min/max instructions */\n+uint32_t fp_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+uint32_t fp_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+uint16_t fp_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+uint16_t fp_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+\n+/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than -INF */\n+uint32_t qf_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n+uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n+\n #endif\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nindex ceb32ce43b..086e8dd29e 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.c\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -67,3 +67,65 @@ uint32_t fp_vdmpy_acc(uint32_t acc, uint16_t a1, uint16_t a2,\n float32 red = fp_vdmpy(a1, a2, a3, a4, fp_status);\n return fp_add_sf_sf(float32_val(red), acc, fp_status);\n }\n+\n+DEF_FP_INSN_2(min_sf, 32, 32, 32, float32_min(f1, f2, fp_status))\n+DEF_FP_INSN_2(max_sf, 32, 32, 32, float32_max(f1, f2, fp_status))\n+DEF_FP_INSN_2(min_hf, 16, 16, 16, float16_min(f1, f2, fp_status))\n+DEF_FP_INSN_2(max_hf, 16, 16, 16, float16_max(f1, f2, fp_status))\n+\n+#define float32_is_pos_nan(X) (float32_is_any_nan(X) && !float32_is_neg(X))\n+#define float32_is_neg_nan(X) (float32_is_any_nan(X) && float32_is_neg(X))\n+#define float16_is_pos_nan(X) (float16_is_any_nan(X) && !float16_is_neg(X))\n+#define float16_is_neg_nan(X) (float16_is_any_nan(X) && float16_is_neg(X))\n+\n+uint32_t qf_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status)\n+{\n+ float32 f1 = make_float32(a1);\n+ float32 f2 = make_float32(a2);\n+ if (float32_is_pos_nan(f1) || float32_is_neg_nan(f2)) {\n+ return a1;\n+ }\n+ if (float32_is_pos_nan(f2) || float32_is_neg_nan(f1)) {\n+ return a2;\n+ }\n+ return fp_max_sf(a1, a2, fp_status);\n+}\n+\n+uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status)\n+{\n+ float32 f1 = make_float32(a1);\n+ float32 f2 = make_float32(a2);\n+ if (float32_is_pos_nan(f1) || float32_is_neg_nan(f2)) {\n+ return a2;\n+ }\n+ if (float32_is_pos_nan(f2) || float32_is_neg_nan(f1)) {\n+ return a1;\n+ }\n+ return fp_min_sf(a1, a2, fp_status);\n+}\n+\n+uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status)\n+{\n+ float16 f1 = make_float16(a1);\n+ float16 f2 = make_float16(a2);\n+ if (float16_is_pos_nan(f1) || float16_is_neg_nan(f2)) {\n+ return a1;\n+ }\n+ if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) {\n+ return a2;\n+ }\n+ return fp_max_hf(a1, a2, fp_status);\n+}\n+\n+uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status)\n+{\n+ float16 f1 = make_float16(a1);\n+ float16 f2 = make_float16(a2);\n+ if (float16_is_pos_nan(f1) || float16_is_neg_nan(f2)) {\n+ return a2;\n+ }\n+ if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) {\n+ return a1;\n+ }\n+ return fp_min_hf(a1, a2, fp_status);\n+}\ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 4ce87d09fd..d7f50db778 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -823,4 +823,14 @@ DEF_ENC(V6_vsub_sf_hf,\"00011111100vvvvvPP1uuuuu101ddddd\")\n DEF_ENC(V6_vadd_hf_hf,\"00011111101vvvvvPP1uuuuu111ddddd\")\n DEF_ENC(V6_vsub_hf_hf,\"00011111011vvvvvPP1uuuuu000ddddd\")\n \n+/* IEEE FP min/max instructions */\n+DEF_ENC(V6_vfmin_hf,\"00011100011vvvvvPP1uuuuu000ddddd\")\n+DEF_ENC(V6_vfmin_sf,\"00011100011vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vfmax_hf,\"00011100011vvvvvPP1uuuuu010ddddd\")\n+DEF_ENC(V6_vfmax_sf,\"00011100011vvvvvPP1uuuuu011ddddd\")\n+DEF_ENC(V6_vmax_sf,\"00011111110vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vmin_sf,\"00011111110vvvvvPP1uuuuu010ddddd\")\n+DEF_ENC(V6_vmax_hf,\"00011111110vvvvvPP1uuuuu011ddddd\")\n+DEF_ENC(V6_vmin_hf,\"00011111110vvvvvPP1uuuuu100ddddd\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex e800cda317..19135853d4 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -43,7 +43,9 @@\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA), \\\n DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n-\n+#define ITERATOR_INSN_ANY_SLOT_2SRC(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VA,A_CVI_VA_2SRC,A_HVX_FLT), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n #define ITERATOR_INSN2_ANY_SLOT(WIDTH,TAG,SYNTAX,SYNTAX2,DESCR,CODE) \\\n ITERATOR_INSN_ANY_SLOT(WIDTH,TAG,SYNTAX2,DESCR,CODE)\n@@ -2992,6 +2994,38 @@ ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vsub_sf_hf,\n VddV.v[0].sf[i] = fp_sub_sf_hf(VuV.hf[2*i], VvV.hf[2*i], &env->hvx_fp_status);\n VddV.v[1].sf[i] = fp_sub_sf_hf(VuV.hf[2*i+1], VvV.hf[2*i+1], &env->hvx_fp_status))\n \n+#define ITERATOR_INSN_IEEE_FP_16_32_LATE(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,A_HVX_IEEE_FP_OUT_32), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* IEEE FP min/max instructions */\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmin_hf, \"Vd32.hf=vfmin(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector IEEE min: hf\", VdV.hf[i] = fp_min_hf(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmin_sf, \"Vd32.sf=vfmin(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector IEEE min: sf\", VdV.sf[i] = fp_min_sf(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfmax_hf, \"Vd32.hf=vfmax(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector IEEE max: hf\", VdV.hf[i] = fp_max_hf(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfmax_sf, \"Vd32.sf=vfmax(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector IEEE max: sf\", VdV.sf[i] = fp_max_sf(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+\n+ITERATOR_INSN_ANY_SLOT_2SRC(32,vmax_sf,\"Vd32.sf=vmax(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector max of sf input\", VdV.sf[i] = qf_max_sf(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_ANY_SLOT_2SRC(32,vmin_sf,\"Vd32.sf=vmin(Vu32.sf,Vv32.sf)\", \\\n+ \"Vector min of sf input\", VdV.sf[i] = qf_min_sf(VuV.sf[i], VvV.sf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,\"Vd32.hf=vmax(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector max of hf input\", VdV.hf[i] = qf_max_hf(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,\"Vd32.hf=vmin(Vu32.hf,Vv32.hf)\", \\\n+ \"Vector min of hf input\", VdV.hf[i] = qf_min_hf(VuV.hf[i], VvV.hf[i], \\\n+\t&env->hvx_fp_status))\n+\n /******************************************************************************\n DEBUG Vector/Register Printing\n ******************************************************************************/\n", "prefixes": [ "v2", "07/16" ] }