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GET /api/patches/2219044/?format=api
{ "id": 2219044, "url": "http://patchwork.ozlabs.org/api/patches/2219044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/cbb8794e47694bbb0576313b882dd0ecc525cef1.1775122853.git.matheus.bernardino@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<cbb8794e47694bbb0576313b882dd0ecc525cef1.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-02T10:47:20", "name": "[v2,03/16] target/hexagon/cpu: add HVX IEEE FP extension", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "325d3c522c28fca6331f8a99ec517b8a8e8afb5b", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/cbb8794e47694bbb0576313b882dd0ecc525cef1.1775122853.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 498468, "url": "http://patchwork.ozlabs.org/api/series/498468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498468", "date": "2026-04-02T10:47:20", "name": "hexagon: add missing HVX float instructions", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498468/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219044/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219044/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v2 03/16] target/hexagon/cpu: add HVX IEEE FP extension", "Date": "Thu, 2 Apr 2026 03:47:20 -0700", "Message-Id": "\n <cbb8794e47694bbb0576313b882dd0ecc525cef1.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775122853.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "6wSV6cocFeSotUmD9Xu1MsUiLoYIs9Lk", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAyMDA5NyBTYWx0ZWRfX/ZWQ4eAXX3el\n 5dQOTgsT7K2EuUusSXGtZLABD+XnEvyukjzvbfZyUWJUsm+Q+CrMqj21g0sg4mQauJH4DM3OK/s\n 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"X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015\n bulkscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604020097", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This flag will be used to control the HVX IEEE float instructions, which\nare only available at some Hexagon cores. When unavailable, the\ninstruction effectively only set the destination registers to 0.\n\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 1 +\n target/hexagon/translate.h | 1 +\n target/hexagon/attribs_def.h.inc | 3 +++\n target/hexagon/cpu.c | 1 +\n target/hexagon/translate.c | 1 +\n target/hexagon/gen_tcg_funcs.py | 11 ++++++++++\n target/hexagon/hex_common.py | 35 ++++++++++++++++++++++++++++++++\n 7 files changed, 53 insertions(+)", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 85afd59277..77822a48b6 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -127,6 +127,7 @@ struct ArchCPU {\n bool lldb_compat;\n target_ulong lldb_stack_adjust;\n bool short_circuit;\n+ bool ieee_fp_extension;\n };\n \n #include \"cpu_bits.h\"\ndiff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\nindex b37cb49238..516aab7038 100644\n--- a/target/hexagon/translate.h\n+++ b/target/hexagon/translate.h\n@@ -70,6 +70,7 @@ typedef struct DisasContext {\n target_ulong branch_dest;\n bool is_tight_loop;\n bool short_circuit;\n+ bool ieee_fp_extension;\n bool read_after_write;\n bool has_hvx_overlap;\n TCGv new_value[TOTAL_PER_THREAD_REGS];\ndiff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\nindex 9e3a05f882..c85cd5d17c 100644\n--- a/target/hexagon/attribs_def.h.inc\n+++ b/target/hexagon/attribs_def.h.inc\n@@ -173,5 +173,8 @@ DEF_ATTRIB(NOTE_SHIFT_RESOURCE, \"Uses the HVX shift resource.\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, \"Packet must not have slot 1 store\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_LATEPRED, \"Predicate can not be used as a .new.\", \"\", \"\")\n \n+/* HVX IEEE FP extension attributes */\n+DEF_ATTRIB(HVX_IEEE_FP, \"HVX IEEE FP extension instruction\", \"\", \"\")\n+\n /* Keep this as the last attribute: */\n DEF_ATTRIB(ZZ_LASTATTRIB, \"Last attribute in the file\", \"\", \"\")\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex ffd14bb467..8b72a5d3c8 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -54,6 +54,7 @@ static const Property hexagon_cpu_properties[] = {\n DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n qdev_prop_uint32, target_ulong),\n DEFINE_PROP_BOOL(\"short-circuit\", HexagonCPU, short_circuit, true),\n+ DEFINE_PROP_BOOL(\"ieee-fp\", HexagonCPU, ieee_fp_extension, true),\n };\n \n const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = {\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 633401451d..fa8f615a9e 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -988,6 +988,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n ctx->short_circuit = hex_cpu->short_circuit;\n+ ctx->ieee_fp_extension = hex_cpu->ieee_fp_extension;\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\ndiff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py\nindex 87b7f10d7f..b752ec883c 100755\n--- a/target/hexagon/gen_tcg_funcs.py\n+++ b/target/hexagon/gen_tcg_funcs.py\n@@ -22,6 +22,14 @@\n import string\n import hex_common\n \n+def gen_disabled_ieee_insn(f, tag, regs):\n+ f.write(\" if (!ctx->ieee_fp_extension) {\\n\")\n+ for regtype, regid in regs:\n+ reg = hex_common.get_register(tag, regtype, regid)\n+ if reg.is_hvx_reg() and reg.is_written():\n+ reg.gen_zero(f)\n+ f.write(\" return;\\n\")\n+ f.write(\" }\\n\")\n \n ##\n ## Generate the TCG code to call the helper\n@@ -62,6 +70,9 @@ def gen_tcg_func(f, tag, regs, imms):\n i = 1 if immlett.isupper() else 0\n f.write(f\" int {hex_common.imm_name(immlett)} = insn->immed[{i}];\\n\")\n \n+ if \"A_HVX_IEEE_FP\" in hex_common.attribdict[tag]:\n+ gen_disabled_ieee_insn(f, tag, regs)\n+\n if hex_common.is_idef_parser_enabled(tag):\n declared = []\n ## Handle registers\ndiff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py\nindex c0e9f26aeb..32a61505ce 100755\n--- a/target/hexagon/hex_common.py\n+++ b/target/hexagon/hex_common.py\n@@ -723,6 +723,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVector), sizeof(MMVector), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -789,6 +794,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVector), sizeof(MMVector), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -821,6 +831,11 @@ def decl_tcg(self, f, tag, regno):\n vreg_src_off(ctx, {self.reg_num}),\n sizeof(MMVector), sizeof(MMVector));\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVector), sizeof(MMVector), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n f.write(code_fmt(f\"\"\"\\\n gen_vreg_write(ctx, {self.hvx_off()}, {self.reg_num},\n@@ -854,6 +869,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -913,6 +933,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMVectorPair), sizeof(MMVectorPair), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n f.write(code_fmt(f\"\"\"\\\n gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},\n@@ -946,6 +971,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMQReg), sizeof(MMQReg), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n@@ -993,6 +1023,11 @@ def decl_tcg(self, f, tag, regno):\n TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n \"\"\"))\n+ def gen_zero(self, f):\n+ f.write(code_fmt(f\"\"\"\\\n+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n+ sizeof(MMQReg), sizeof(MMQReg), 0);\n+ \"\"\"))\n def gen_write(self, f, tag):\n pass\n def helper_hvx_desc(self, f):\n", "prefixes": [ "v2", "03/16" ] }