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GET /api/patches/2218984/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2218984,
    "url": "http://patchwork.ozlabs.org/api/patches/2218984/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260402085545.284457-1-a-garg7@ti.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260402085545.284457-1-a-garg7@ti.com>",
    "list_archive_url": null,
    "date": "2026-04-02T08:55:45",
    "name": "PCI: cadence: Use cdns_pcie_read_sz() for byte or word read access",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "1fe0c21cabc1cc9c9f62d049821a25c57fbe1257",
    "submitter": {
        "id": 92467,
        "url": "http://patchwork.ozlabs.org/api/people/92467/?format=api",
        "name": "Aksh Garg",
        "email": "a-garg7@ti.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260402085545.284457-1-a-garg7@ti.com/mbox/",
    "series": [
        {
            "id": 498453,
            "url": "http://patchwork.ozlabs.org/api/series/498453/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498453",
            "date": "2026-04-02T08:55:45",
            "name": "PCI: cadence: Use cdns_pcie_read_sz() for byte or word read access",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/498453/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2218984/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2218984/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Aksh Garg <a-garg7@ti.com>",
        "To": "<linux-pci@vger.kernel.org>, <lpieralisi@kernel.org>, <mani@kernel.org>,\n\t<kwilczynski@kernel.org>, <bhelgaas@google.com>, <18255117159@163.com>",
        "CC": "<linux-kernel@vger.kernel.org>, <robh@kernel.org>, <mpillai@cadence.com>,\n\t<unicorn_wang@outlook.com>, <s-vadapalli@ti.com>, <danishanwar@ti.com>,\n\t<a-garg7@ti.com>",
        "Subject": "[PATCH] PCI: cadence: Use cdns_pcie_read_sz() for byte or word read\n access",
        "Date": "Thu, 2 Apr 2026 14:25:45 +0530",
        "Message-ID": "<20260402085545.284457-1-a-garg7@ti.com>",
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    },
    "content": "The commit 18ac51ae9df9 (\"PCI: cadence: Implement capability search\nusing PCI core APIs\") assumes all the platforms using Cadence PCIe\ncontroller support byte and word register accesses. This is not true\nfor all platforms (e.g., TI J721E SoC, which only supports dword\nregister accesses).\n\nThis causes capability searches via cdns_pcie_find_capability() to fail\non such platforms.\n\nFix this by using cdns_pcie_read_sz() for config read functions, which\nproperly handles size-aligned accesses. Remove the now-unused byte and\nword read wrapper functions (cdns_pcie_readw and cdns_pcie_readb).\n\nFixes: 18ac51ae9df9 (\"PCI: cadence: Implement capability search using PCI core APIs\")\nSigned-off-by: Aksh Garg <a-garg7@ti.com>\nCc: stable@vger.kernel.org\n---\n drivers/pci/controller/cadence/pcie-cadence.h | 56 +++++++++----------\n 1 file changed, 25 insertions(+), 31 deletions(-)",
    "diff": "diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h\nindex 443033c607d7..277f3706a4f4 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence.h\n@@ -249,37 +249,6 @@ static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie,\n \treturn readl(pcie->reg_base + reg);\n }\n \n-static inline u16 cdns_pcie_readw(struct cdns_pcie *pcie, u32 reg)\n-{\n-\treturn readw(pcie->reg_base + reg);\n-}\n-\n-static inline u8 cdns_pcie_readb(struct cdns_pcie *pcie, u32 reg)\n-{\n-\treturn readb(pcie->reg_base + reg);\n-}\n-\n-static inline int cdns_pcie_read_cfg_byte(struct cdns_pcie *pcie, int where,\n-\t\t\t\t\t  u8 *val)\n-{\n-\t*val = cdns_pcie_readb(pcie, where);\n-\treturn PCIBIOS_SUCCESSFUL;\n-}\n-\n-static inline int cdns_pcie_read_cfg_word(struct cdns_pcie *pcie, int where,\n-\t\t\t\t\t  u16 *val)\n-{\n-\t*val = cdns_pcie_readw(pcie, where);\n-\treturn PCIBIOS_SUCCESSFUL;\n-}\n-\n-static inline int cdns_pcie_read_cfg_dword(struct cdns_pcie *pcie, int where,\n-\t\t\t\t\t   u32 *val)\n-{\n-\t*val = cdns_pcie_readl(pcie, where);\n-\treturn PCIBIOS_SUCCESSFUL;\n-}\n-\n static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)\n {\n \tvoid __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);\n@@ -320,6 +289,31 @@ static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value)\n \twritel(val, aligned_addr);\n }\n \n+static inline int cdns_pcie_read_cfg_byte(struct cdns_pcie *pcie, int where,\n+\t\t\t\t\t  u8 *val)\n+{\n+\tvoid __iomem *addr = pcie->reg_base + where;\n+\n+\t*val = cdns_pcie_read_sz(addr, 0x1);\n+\treturn PCIBIOS_SUCCESSFUL;\n+}\n+\n+static inline int cdns_pcie_read_cfg_word(struct cdns_pcie *pcie, int where,\n+\t\t\t\t\t  u16 *val)\n+{\n+\tvoid __iomem *addr = pcie->reg_base + where;\n+\n+\t*val = cdns_pcie_read_sz(addr, 0x2);\n+\treturn PCIBIOS_SUCCESSFUL;\n+}\n+\n+static inline int cdns_pcie_read_cfg_dword(struct cdns_pcie *pcie, int where,\n+\t\t\t\t\t   u32 *val)\n+{\n+\t*val = cdns_pcie_readl(pcie, where);\n+\treturn PCIBIOS_SUCCESSFUL;\n+}\n+\n /* Root Port register access */\n static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,\n \t\t\t\t       u32 reg, u8 value)\n",
    "prefixes": []
}