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GET /api/patches/2218878/?format=api
{ "id": 2218878, "url": "http://patchwork.ozlabs.org/api/patches/2218878/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260401210238.60010-4-marex@nabladev.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401210238.60010-4-marex@nabladev.com>", "list_archive_url": null, "date": "2026-04-01T21:02:20", "name": "[4/4] arm64: imx8mp: Add 4G 1r DRAM timings on DH i.MX8MP DHCOM SoM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fda7c05a59b251682e9be1f96b4be6723dc64a75", "submitter": { "id": 91452, "url": "http://patchwork.ozlabs.org/api/people/91452/?format=api", "name": "Marek Vasut", "email": "marex@nabladev.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260401210238.60010-4-marex@nabladev.com/mbox/", "series": [ { "id": 498411, "url": "http://patchwork.ozlabs.org/api/series/498411/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498411", "date": "2026-04-01T21:02:17", "name": "[1/4] arm64: imx8mp: Fold inline ECC into spl.c on DH i.MX8MP DHCOM SoM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498411/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218878/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218878/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nabladev.com header.i=@nabladev.com header.a=rsa-sha256\n header.s=dkim header.b=GhvQmQxF;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=nabladev.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nabladev.com header.i=@nabladev.com\n header.b=\"GhvQmQxF\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=reject dis=none)\n header.from=nabladev.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=marex@nabladev.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmLhD5s22z1yFv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 10:25:48 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id DEAD184129;\n\tThu, 2 Apr 2026 01:24:54 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 7728184099; Wed, 1 Apr 2026 23:02:50 +0200 (CEST)", "from mx.nabladev.com (mx.nabladev.com\n [IPv6:2a00:f820:417:0:178:251:229:89])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id D45D884056\n for <u-boot@lists.denx.de>; Wed, 1 Apr 2026 23:02:47 +0200 (CEST)", "from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id 2CD06112C9C; Wed, 1 Apr 2026 23:02:47 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com;\n s=dkim; t=1775077367; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding:in-reply-to:references;\n bh=TB8AmE8toKxrGIMdHx7s2GCUE9CId6Ue08zeAn4FQ9I=;\n b=GhvQmQxFuXdUEyBntHsTAaFGDvkqreIpXvChumRB5qkVmah839ER7llwT9b4esEvG2ija4\n /LyoiivwS0niQtQQOOPQJN6zZqaHLbOt3Yz+henSMdNdiNdBwyXxB4dkgEUhi1S1OW7UUL\n 7hpolnLVDMqw1B/UNK+apCPCCReeFNXVh+B8p3Sun7wqHI0jysFKmoA/FwBQrdhBxhitr9\n h8Ick9u9qZYURRxNDC1clnZlcp+c/9Pz1tLcRWGIqNptqBlIndf4Sx0Fg6td+oI1waswui\n tJCym7a5ECzRH4GHVBEzM41wZ6E/daJ0R9wWpjFF8T4Xhmcn7IHP1NDWxtDMfA==", "From": "Marek Vasut <marex@nabladev.com>", "To": "u-boot@lists.denx.de", "Cc": "Marek Vasut <marex@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Peng Fan <peng.fan@nxp.com>, Tom Rini <trini@konsulko.com>,\n u-boot@dh-electronics.com", "Subject": "[PATCH 4/4] arm64: imx8mp: Add 4G 1r DRAM timings on DH i.MX8MP DHCOM\n SoM", "Date": "Wed, 1 Apr 2026 23:02:20 +0200", "Message-ID": "<20260401210238.60010-4-marex@nabladev.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260401210238.60010-1-marex@nabladev.com>", "References": "<20260401210238.60010-1-marex@nabladev.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Last-TLS-Session-Version": "TLSv1.3", "X-Mailman-Approved-At": "Thu, 02 Apr 2026 01:24:51 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Introduce timing patch which converts 2 GiB DRAM timings to 4 GiB 1-rank\ntimings. This is a new configuration which carries IS43LQ32K01B DRAM part.\nThe 512 MiB SoM strapping that was never used is repurposed for this part.\n\nSigned-off-by: Marek Vasut <marex@nabladev.com>\n---\nCc: Fabio Estevam <festevam@gmail.com>\nCc: Peng Fan <peng.fan@nxp.com>\nCc: Tom Rini <trini@konsulko.com>\nCc: u-boot@dh-electronics.com\nCc: u-boot@lists.denx.de\n---\n board/dhelectronics/dh_imx8mp/lpddr4_timing.h | 3 +-\n .../dh_imx8mp/lpddr4_timing_2G_32.c | 138 ++++++++++++++++++\n board/dhelectronics/dh_imx8mp/spl.c | 4 +-\n 3 files changed, 142 insertions(+), 3 deletions(-)", "diff": "diff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h\nindex ef899dc0678..5dc841a7f5a 100644\n--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h\n+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h\n@@ -7,7 +7,7 @@\n #define __LPDDR4_TIMING_H__\n \n static const u16 dh_imx8mp_dhcom_dram_size[] = {\n-\t512, 1024, 1536, 2048, 3072, 4096, 6144, 8192\n+\t4096, 1024, 1536, 2048, 3072, 4096, 6144, 8192\n };\n \n extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;\n@@ -15,6 +15,7 @@ static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing =\n \t&dh_imx8mp_dhcom_dram_timing_16g_x32;\n void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void);\n void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void);\n+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void);\n \n u8 dh_get_memcfg(void);\n \ndiff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c\nindex f93b3082b63..9574e920352 100644\n--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c\n+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c\n@@ -1910,3 +1910,141 @@ void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void)\n \t\t\tddr_fsp0_2d_cfg[i].val = 0x3;\n \t}\n };\n+\n+/* Convert 2 GiB DRAM settings to 4 GiB 1-rank DRAM settings. */\n+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r(void)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) {\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400064)\n+\t\t\tddr_ddrc_cfg[i].val = 0x6d0156;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400138)\n+\t\t\tddr_ddrc_cfg[i].val = 0x15d;\n+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400200)\n+\t\t\tddr_ddrc_cfg[i].val = 0x1f;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d40020c)\n+\t\t\tddr_ddrc_cfg[i].val = 0x14141400;\n+#else\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400200)\n+\t\t\tddr_ddrc_cfg[i].val = 0x17;\n+#endif\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d40021c)\n+\t\t\tddr_ddrc_cfg[i].val = 0xf04;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402024)\n+\t\t\tddr_ddrc_cfg[i].val = 0x61a800;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402064)\n+\t\t\tddr_ddrc_cfg[i].val = 0x18004c;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d4020dc)\n+\t\t\tddr_ddrc_cfg[i].val = 0x940009;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402100)\n+\t\t\tddr_ddrc_cfg[i].val = 0xc080609;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402104)\n+\t\t\tddr_ddrc_cfg[i].val = 0x3040d;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402108)\n+\t\t\tddr_ddrc_cfg[i].val = 0x3060a0c;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402110)\n+\t\t\tddr_ddrc_cfg[i].val = 0x4040204;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402114)\n+\t\t\tddr_ddrc_cfg[i].val = 0x2030303;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402138)\n+\t\t\tddr_ddrc_cfg[i].val = 0x4e;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402144)\n+\t\t\tddr_ddrc_cfg[i].val = 0x280014;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402180)\n+\t\t\tddr_ddrc_cfg[i].val = 0xc80006;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d402190)\n+\t\t\tddr_ddrc_cfg[i].val = 0x3878202;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d4021b4)\n+\t\t\tddr_ddrc_cfg[i].val = 0x702;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403024)\n+\t\t\tddr_ddrc_cfg[i].val = 0x493fe1;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403064)\n+\t\t\tddr_ddrc_cfg[i].val = 0x12003a;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403100)\n+\t\t\tddr_ddrc_cfg[i].val = 0xa070507;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403104)\n+\t\t\tddr_ddrc_cfg[i].val = 0x3040a;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403108)\n+\t\t\tddr_ddrc_cfg[i].val = 0x203070b;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403110)\n+\t\t\tddr_ddrc_cfg[i].val = 0x3040203;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403114)\n+\t\t\tddr_ddrc_cfg[i].val = 0x2030303;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403138)\n+\t\t\tddr_ddrc_cfg[i].val = 0x3b;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403144)\n+\t\t\tddr_ddrc_cfg[i].val = 0x1f0010;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d403180)\n+\t\t\tddr_ddrc_cfg[i].val = 0x970005;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_ddrphy_cfg); i++) {\n+\t\tif (ddr_ddrphy_cfg[i].reg == 0x12002e)\n+\t\t\tddr_ddrphy_cfg[i].val = 0x1;\n+\t\tif (ddr_ddrphy_cfg[i].reg == 0x22002e)\n+\t\t\tddr_ddrphy_cfg[i].val = 0x1;\n+\t\tif (ddr_ddrphy_cfg[i].reg == 0x120008)\n+\t\t\tddr_ddrphy_cfg[i].val = 0xc8;\n+\t\tif (ddr_ddrphy_cfg[i].reg == 0x220008)\n+\t\t\tddr_ddrphy_cfg[i].val = 0x96;\n+\t\tif (ddr_ddrphy_cfg[i].reg == 0x200f0)\n+\t\t\tddr_ddrphy_cfg[i].val = 0x500;\n+\t\tif (ddr_ddrphy_cfg[i].reg == 0x200f4)\n+\t\t\tddr_ddrphy_cfg[i].val = 0x5555;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) {\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54002)\n+\t\t\tddr_fsp1_cfg[i].val = 0x1;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54003)\n+\t\t\tddr_fsp1_cfg[i].val = 0x320;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54019)\n+\t\t\tddr_fsp1_cfg[i].val = 0x994;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x5401f)\n+\t\t\tddr_fsp1_cfg[i].val = 0x994;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54032)\n+\t\t\tddr_fsp1_cfg[i].val = 0x9400;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54033)\n+\t\t\tddr_fsp1_cfg[i].val = 0xf309;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54038)\n+\t\t\tddr_fsp1_cfg[i].val = 0x9400;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54039)\n+\t\t\tddr_fsp1_cfg[i].val = 0xf309;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) {\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54002)\n+\t\t\tddr_fsp2_cfg[i].val = 0x2;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54003)\n+\t\t\tddr_fsp2_cfg[i].val = 0x258;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54019)\n+\t\t\tddr_fsp2_cfg[i].val = 0x994;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x5401f)\n+\t\t\tddr_fsp2_cfg[i].val = 0x994;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54032)\n+\t\t\tddr_fsp2_cfg[i].val = 0x9400;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54033)\n+\t\t\tddr_fsp2_cfg[i].val = 0xf309;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54038)\n+\t\t\tddr_fsp2_cfg[i].val = 0x9400;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54039)\n+\t\t\tddr_fsp2_cfg[i].val = 0xf309;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_phy_pie); i++) {\n+\t\tif (ddr_phy_pie[i].reg == 0x12000b)\n+\t\t\tddr_phy_pie[i].val = 0xe1;\n+\t\tif (ddr_phy_pie[i].reg == 0x12000c)\n+\t\t\tddr_phy_pie[i].val = 0x32;\n+\t\tif (ddr_phy_pie[i].reg == 0x12000d)\n+\t\t\tddr_phy_pie[i].val = 0x1f4;\n+\t\tif (ddr_phy_pie[i].reg == 0x22000b)\n+\t\t\tddr_phy_pie[i].val = 0xa8;\n+\t\tif (ddr_phy_pie[i].reg == 0x22000c)\n+\t\t\tddr_phy_pie[i].val = 0x25;\n+\t\tif (ddr_phy_pie[i].reg == 0x22000d)\n+\t\t\tddr_phy_pie[i].val = 0x177;\n+\t}\n+};\ndiff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c\nindex 8b9dddab79a..aab8550023e 100644\n--- a/board/dhelectronics/dh_imx8mp/spl.c\n+++ b/board/dhelectronics/dh_imx8mp/spl.c\n@@ -107,7 +107,7 @@ static int dh_imx8mp_board_power_init(void)\n typedef void (*patch_func_t)(void);\n \n static const patch_func_t dram_patch_fn[8] = {\n-\tNULL,\t\t\t\t\t\t\t/* 512 MiB */\n+\tdh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_1r,\t/* 4096 MiB 1-rank */\n \tNULL,\t\t\t\t\t\t\t/* 1024 MiB */\n \tNULL,\t\t\t\t\t\t\t/* 1536 MiB */\n \tdh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32,\t\t/* 2048 MiB */\n@@ -168,7 +168,7 @@ static void dh_imx8mp_dhcom_dram_scrub_32g_x32(void)\n typedef void (*scrub_func_t)(void);\n \n static const scrub_func_t dram_scrub_fn[8] = {\n-\tNULL,\t\t\t\t\t/* 512 MiB */\n+\tdh_imx8mp_dhcom_dram_scrub_32g_x32,\t/* 4096 MiB 1-rank */\n \tNULL,\t\t\t\t\t/* 1024 MiB */\n \tNULL,\t\t\t\t\t/* 1536 MiB */\n \tdh_imx8mp_dhcom_dram_scrub_16g_x32,\t/* 2048 MiB */\n", "prefixes": [ "4/4" ] }