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GET /api/patches/2218875/?format=api
{ "id": 2218875, "url": "http://patchwork.ozlabs.org/api/patches/2218875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260401191617.20141-3-marex@nabladev.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401191617.20141-3-marex@nabladev.com>", "list_archive_url": null, "date": "2026-04-01T19:15:55", "name": "[3/4] arm64: imx8mp: Deduplicate 2G and 4G 2r DRAM timings on DH i.MX8MP DHCOM SoM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e2d23e20e8dd5212fbc79fb3a5ac370e15754c97", "submitter": { "id": 91452, "url": "http://patchwork.ozlabs.org/api/people/91452/?format=api", "name": "Marek Vasut", "email": "marex@nabladev.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260401191617.20141-3-marex@nabladev.com/mbox/", "series": [ { "id": 498410, "url": "http://patchwork.ozlabs.org/api/series/498410/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498410", "date": "2026-04-01T19:15:54", "name": "[1/4] arm64: imx8mp: Fold inline ECC into spl.c on DH i.MX8MP DHCOM SoM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498410/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218875/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218875/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nabladev.com header.i=@nabladev.com header.a=rsa-sha256\n header.s=dkim header.b=PiiXk+zg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=nabladev.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nabladev.com header.i=@nabladev.com\n header.b=\"PiiXk+zg\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=reject dis=none)\n header.from=nabladev.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=marex@nabladev.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmLgj5gnsz1yFv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 10:25:21 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 14E03840D8;\n\tThu, 2 Apr 2026 01:24:54 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 9217F83F7D; Wed, 1 Apr 2026 21:16:43 +0200 (CEST)", "from mx.nabladev.com (mx.nabladev.com\n [IPv6:2a00:f820:417:0:178:251:229:89])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 343DC80517\n for <u-boot@lists.denx.de>; Wed, 1 Apr 2026 21:16:39 +0200 (CEST)", "from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id 9DFAF112C65; Wed, 1 Apr 2026 21:16:36 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nabladev.com;\n s=dkim; t=1775070997; h=from:subject:date:message-id:to:cc:mime-version:\n content-transfer-encoding:in-reply-to:references;\n bh=rU1E3Ppz0ocH7/KjXNRd6+oTjkBld158YH7OSIKI3dY=;\n b=PiiXk+zgV8ZX7OwOk8e7/CGUZBs4aqPiKU8UHV23HIiT1xcTpH7pyyDALc0eZNl0thtlkg\n MzgpKn5oiyS3oeXmuF3LdMb2XERLcjwsu87G0XPCgl0wiCQZdT0p7B0N0a6Ow0apey2T0W\n NcoXfM7UuyLtW961GEgd8b6TtVYyiwUqPPZIF3QZRSFCJ/1Tv7GK0iaKyv+7+ImYvLG6E+\n r5crVgQVWshMVychgFM30NjGapgsVJFV2CeKSnMQPuFS8nR06rBFIEnwJq2U6/DyBF3x8E\n 4AXK/sU+hFSPFFfkXGZKJpVXXBVHNTPgoQ7Cnx1msYqpDDfaZdLpQ1ol0pHtJg==", "From": "Marek Vasut <marex@nabladev.com>", "To": "u-boot@lists.denx.de", "Cc": "Marek Vasut <marex@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Peng Fan <peng.fan@nxp.com>, Tom Rini <trini@konsulko.com>,\n u-boot@dh-electronics.com", "Subject": "[PATCH 3/4] arm64: imx8mp: Deduplicate 2G and 4G 2r DRAM timings on\n DH i.MX8MP DHCOM SoM", "Date": "Wed, 1 Apr 2026 21:15:55 +0200", "Message-ID": "<20260401191617.20141-3-marex@nabladev.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260401191617.20141-1-marex@nabladev.com>", "References": "<20260401191617.20141-1-marex@nabladev.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Last-TLS-Session-Version": "TLSv1.3", "X-Mailman-Approved-At": "Thu, 02 Apr 2026 01:24:51 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The 2 GiB and 4 GiB 2-rank DRAM timings on i.MX8MP DHCOM are very\nsimilar. Instead of carrying around two copies of almost identical\ntiming tables, implement a patch of the 2 GiB table to convert it\ninto 4 GiB 2-rank table and pass the result to DRAM initialization\ncode. This saves us 13640 Bytes in SPL, and frees up space for more\nDRAM initialization tables.\n\nSigned-off-by: Marek Vasut <marex@nabladev.com>\n---\nCc: Fabio Estevam <festevam@gmail.com>\nCc: Peng Fan <peng.fan@nxp.com>\nCc: Tom Rini <trini@konsulko.com>\nCc: u-boot@dh-electronics.com\nCc: u-boot@lists.denx.de\n---\n board/dhelectronics/dh_imx8mp/Makefile | 2 +-\n board/dhelectronics/dh_imx8mp/lpddr4_timing.h | 5 +-\n .../dh_imx8mp/lpddr4_timing_2G_32.c | 57 +\n .../dh_imx8mp/lpddr4_timing_4G_32.c | 1859 -----------------\n board/dhelectronics/dh_imx8mp/spl.c | 31 +-\n 5 files changed, 79 insertions(+), 1875 deletions(-)\n delete mode 100644 board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c", "diff": "diff --git a/board/dhelectronics/dh_imx8mp/Makefile b/board/dhelectronics/dh_imx8mp/Makefile\nindex 7bc8dc21e64..12fb7b71ab6 100644\n--- a/board/dhelectronics/dh_imx8mp/Makefile\n+++ b/board/dhelectronics/dh_imx8mp/Makefile\n@@ -5,7 +5,7 @@\n #\n \n ifdef CONFIG_XPL_BUILD\n-obj-y += spl.o lpddr4_timing_2G_32.o lpddr4_timing_4G_32.o\n+obj-y += spl.o lpddr4_timing_2G_32.o\n else\n obj-y += imx8mp_dhcom_pdk2.o\n endif\ndiff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h\nindex 0f9f47bbe11..ef899dc0678 100644\n--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing.h\n+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing.h\n@@ -11,7 +11,10 @@ static const u16 dh_imx8mp_dhcom_dram_size[] = {\n };\n \n extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32;\n-extern struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32;\n+static __maybe_unused struct dram_timing_info *dh_imx8mp_dhcom_dram_timing =\n+\t&dh_imx8mp_dhcom_dram_timing_16g_x32;\n+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void);\n+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void);\n \n u8 dh_get_memcfg(void);\n \ndiff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c\nindex 3cb868311f3..f93b3082b63 100644\n--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c\n+++ b/board/dhelectronics/dh_imx8mp/lpddr4_timing_2G_32.c\n@@ -1853,3 +1853,60 @@ struct dram_timing_info dh_imx8mp_dhcom_dram_timing_16g_x32 = {\n \t.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),\n \t.fsp_table = { 3600, 400, 100, },\n };\n+\n+/*\n+ * Convert 2 GiB DRAM settings to 2 GiB DRAM settings.\n+ * This does nothing and is only a placeholder to indicate\n+ * that the 2 GiB DRAM settings are valid themselves.\n+ */\n+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32(void)\n+{\n+}\n+\n+/* Convert 2 GiB DRAM settings to 4 GiB 2-rank DRAM settings. */\n+void dh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r(void)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_ddrc_cfg); i++) {\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400000)\n+\t\t\tddr_ddrc_cfg[i].val = 0xa3080020;\n+#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400200)\n+\t\t\tddr_ddrc_cfg[i].val = 0x14;\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d40020c)\n+\t\t\tddr_ddrc_cfg[i].val = 0x14141400;\n+#else\n+\t\tif (ddr_ddrc_cfg[i].reg == 0x3d400200)\n+\t\t\tddr_ddrc_cfg[i].val = 0x17;\n+#endif\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_fsp0_cfg); i++) {\n+\t\tif (ddr_fsp0_cfg[i].reg == 0x54012)\n+\t\t\tddr_fsp0_cfg[i].val = 0x310;\n+\t\tif (ddr_fsp0_cfg[i].reg == 0x5402c)\n+\t\t\tddr_fsp0_cfg[i].val = 0x3;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_fsp1_cfg); i++) {\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x54012)\n+\t\t\tddr_fsp1_cfg[i].val = 0x310;\n+\t\tif (ddr_fsp1_cfg[i].reg == 0x5402c)\n+\t\t\tddr_fsp1_cfg[i].val = 0x3;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_fsp2_cfg); i++) {\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x54012)\n+\t\t\tddr_fsp2_cfg[i].val = 0x310;\n+\t\tif (ddr_fsp2_cfg[i].reg == 0x5402c)\n+\t\t\tddr_fsp2_cfg[i].val = 0x3;\n+\t}\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ddr_fsp0_2d_cfg); i++) {\n+\t\tif (ddr_fsp0_2d_cfg[i].reg == 0x54012)\n+\t\t\tddr_fsp0_2d_cfg[i].val = 0x310;\n+\t\tif (ddr_fsp0_2d_cfg[i].reg == 0x5402c)\n+\t\t\tddr_fsp0_2d_cfg[i].val = 0x3;\n+\t}\n+};\ndiff --git a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c b/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c\ndeleted file mode 100644\nindex 3a475076e75..00000000000\n--- a/board/dhelectronics/dh_imx8mp/lpddr4_timing_4G_32.c\n+++ /dev/null\n@@ -1,1859 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2022 Marek Vasut <marex@denx.de>\n- *\n- * Generated code from MX8M_DDR_tool\n- */\n-\n-#include <linux/kernel.h>\n-#include <asm/arch/ddr.h>\n-\n-static struct dram_cfg_param ddr_ddrc_cfg[] = {\n-\t/** Initialize DDRC registers **/\n-\t{ 0x3d400304, 0x1 },\n-\t{ 0x3d400030, 0x1 },\n-\t{ 0x3d400000, 0xa3080020 },\n-\t{ 0x3d400020, 0x1323 },\n-\t{ 0x3d400024, 0x1b77400 },\n-\t{ 0x3d400064, 0x6d00fc },\n-#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)\n-\t{ 0x3d400070, 0x7027fd4 },\n-#else\n-\t{ 0x3d400070, 0x7027f90 },\n-#endif\n-\t{ 0x3d400074, 0x790 },\n-\t{ 0x3d4000d0, 0xc00306df },\n-\t{ 0x3d4000d4, 0xb10000 },\n-\t{ 0x3d4000dc, 0xe40036 },\n-\t{ 0x3d4000e0, 0xf30000 },\n-\t{ 0x3d4000e8, 0x660048 },\n-\t{ 0x3d4000ec, 0x160048 },\n-\t{ 0x3d400100, 0x1d241e26 },\n-\t{ 0x3d400104, 0x70739 },\n-\t{ 0x3d40010c, 0xd0d000 },\n-\t{ 0x3d400110, 0x11040911 },\n-\t{ 0x3d400114, 0x2050e0e },\n-\t{ 0x3d400118, 0x1010008 },\n-\t{ 0x3d40011c, 0x502 },\n-\t{ 0x3d400130, 0x20700 },\n-\t{ 0x3d400134, 0xd100002 },\n-\t{ 0x3d400138, 0x103 },\n-\t{ 0x3d400144, 0xb4005a },\n-\t{ 0x3d400180, 0x384001b },\n-\t{ 0x3d400184, 0x2d06ddd },\n-\t{ 0x3d400188, 0x0 },\n-\t{ 0x3d400190, 0x49f820c },\n-\t{ 0x3d400194, 0x80303 },\n-\t{ 0x3d4001b4, 0x1f0c },\n-\t{ 0x3d4001a0, 0xe0400018 },\n-\t{ 0x3d4001a4, 0xdf00e4 },\n-\t{ 0x3d4001a8, 0x80000000 },\n-\t{ 0x3d4001b0, 0x11 },\n-\t{ 0x3d4001c0, 0x7 },\n-\t{ 0x3d4001c4, 0x1 },\n-\t{ 0x3d4000f4, 0x799 },\n-\t{ 0x3d400108, 0x8121b1a },\n-#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)\n-\t{ 0x3d400200, 0x14 },\n-#else\n-\t{ 0x3d400200, 0x17 },\n-#endif\n-\t{ 0x3d400208, 0x0 },\n-#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)\n-\t{ 0x3d40020c, 0x14141400 },\n-#else\n-\t{ 0x3d40020c, 0x0 },\n-#endif\n-\t{ 0x3d400210, 0x1f1f },\n-#if IS_ENABLED(CONFIG_IMX8M_DRAM_INLINE_ECC)\n-\t{ 0x3d400204, 0x50505 },\n-\t{ 0x3d400214, 0x4040404 },\n-\t{ 0x3d400218, 0x4040404 },\n-#else\n-\t{ 0x3d400204, 0x80808 },\n-\t{ 0x3d400214, 0x7070707 },\n-\t{ 0x3d400218, 0x7070707 },\n-#endif\n-\t{ 0x3d40021c, 0xf0f },\n-\t{ 0x3d400250, 0x1705 },\n-\t{ 0x3d400254, 0x2c },\n-\t{ 0x3d40025c, 0x4000030 },\n-\t{ 0x3d400264, 0x900093e7 },\n-\t{ 0x3d40026c, 0x2005574 },\n-\t{ 0x3d400400, 0x111 },\n-\t{ 0x3d400404, 0x72ff },\n-\t{ 0x3d400408, 0x72ff },\n-\t{ 0x3d400494, 0x2100e07 },\n-\t{ 0x3d400498, 0x620096 },\n-\t{ 0x3d40049c, 0x1100e07 },\n-\t{ 0x3d4004a0, 0xc8012c },\n-\t{ 0x3d402020, 0x1021 },\n-\t{ 0x3d402024, 0x30d400 },\n-\t{ 0x3d402050, 0x20d000 },\n-\t{ 0x3d402064, 0xc001c },\n-\t{ 0x3d4020dc, 0x840000 },\n-\t{ 0x3d4020e0, 0xf30000 },\n-\t{ 0x3d4020e8, 0x660048 },\n-\t{ 0x3d4020ec, 0x160048 },\n-\t{ 0x3d402100, 0xa040305 },\n-\t{ 0x3d402104, 0x30407 },\n-\t{ 0x3d402108, 0x203060b },\n-\t{ 0x3d40210c, 0x505000 },\n-\t{ 0x3d402110, 0x2040202 },\n-\t{ 0x3d402114, 0x2030202 },\n-\t{ 0x3d402118, 0x1010004 },\n-\t{ 0x3d40211c, 0x302 },\n-\t{ 0x3d402130, 0x20300 },\n-\t{ 0x3d402134, 0xa100002 },\n-\t{ 0x3d402138, 0x1d },\n-\t{ 0x3d402144, 0x14000a },\n-\t{ 0x3d402180, 0x640004 },\n-\t{ 0x3d402190, 0x3818200 },\n-\t{ 0x3d402194, 0x80303 },\n-\t{ 0x3d4021b4, 0x100 },\n-\t{ 0x3d4020f4, 0x599 },\n-\t{ 0x3d403020, 0x1021 },\n-\t{ 0x3d403024, 0xc3500 },\n-\t{ 0x3d403050, 0x20d000 },\n-\t{ 0x3d403064, 0x30007 },\n-\t{ 0x3d4030dc, 0x840000 },\n-\t{ 0x3d4030e0, 0xf30000 },\n-\t{ 0x3d4030e8, 0x660048 },\n-\t{ 0x3d4030ec, 0x160048 },\n-\t{ 0x3d403100, 0xa010102 },\n-\t{ 0x3d403104, 0x30404 },\n-\t{ 0x3d403108, 0x203060b },\n-\t{ 0x3d40310c, 0x505000 },\n-\t{ 0x3d403110, 0x2040202 },\n-\t{ 0x3d403114, 0x2030202 },\n-\t{ 0x3d403118, 0x1010004 },\n-\t{ 0x3d40311c, 0x302 },\n-\t{ 0x3d403130, 0x20300 },\n-\t{ 0x3d403134, 0xa100002 },\n-\t{ 0x3d403138, 0x8 },\n-\t{ 0x3d403144, 0x50003 },\n-\t{ 0x3d403180, 0x190004 },\n-\t{ 0x3d403190, 0x3818200 },\n-\t{ 0x3d403194, 0x80303 },\n-\t{ 0x3d4031b4, 0x100 },\n-\t{ 0x3d4030f4, 0x599 },\n-\t{ 0x3d400028, 0x0 },\n-};\n-\n-/* PHY Initialize Configuration */\n-static struct dram_cfg_param ddr_ddrphy_cfg[] = {\n-\t{ 0x100a0, 0x0 },\n-\t{ 0x100a1, 0x1 },\n-\t{ 0x100a2, 0x2 },\n-\t{ 0x100a3, 0x3 },\n-\t{ 0x100a4, 0x4 },\n-\t{ 0x100a5, 0x5 },\n-\t{ 0x100a6, 0x6 },\n-\t{ 0x100a7, 0x7 },\n-\t{ 0x110a0, 0x0 },\n-\t{ 0x110a1, 0x1 },\n-\t{ 0x110a2, 0x3 },\n-\t{ 0x110a3, 0x4 },\n-\t{ 0x110a4, 0x5 },\n-\t{ 0x110a5, 0x2 },\n-\t{ 0x110a6, 0x7 },\n-\t{ 0x110a7, 0x6 },\n-\t{ 0x120a0, 0x0 },\n-\t{ 0x120a1, 0x1 },\n-\t{ 0x120a2, 0x3 },\n-\t{ 0x120a3, 0x2 },\n-\t{ 0x120a4, 0x5 },\n-\t{ 0x120a5, 0x4 },\n-\t{ 0x120a6, 0x7 },\n-\t{ 0x120a7, 0x6 },\n-\t{ 0x130a0, 0x0 },\n-\t{ 0x130a1, 0x1 },\n-\t{ 0x130a2, 0x2 },\n-\t{ 0x130a3, 0x3 },\n-\t{ 0x130a4, 0x4 },\n-\t{ 0x130a5, 0x5 },\n-\t{ 0x130a6, 0x6 },\n-\t{ 0x130a7, 0x7 },\n-\t{ 0x1005f, 0x1ff },\n-\t{ 0x1015f, 0x1ff },\n-\t{ 0x1105f, 0x1ff },\n-\t{ 0x1115f, 0x1ff },\n-\t{ 0x1205f, 0x1ff },\n-\t{ 0x1215f, 0x1ff },\n-\t{ 0x1305f, 0x1ff },\n-\t{ 0x1315f, 0x1ff },\n-\t{ 0x11005f, 0x1ff },\n-\t{ 0x11015f, 0x1ff },\n-\t{ 0x11105f, 0x1ff },\n-\t{ 0x11115f, 0x1ff },\n-\t{ 0x11205f, 0x1ff },\n-\t{ 0x11215f, 0x1ff },\n-\t{ 0x11305f, 0x1ff },\n-\t{ 0x11315f, 0x1ff },\n-\t{ 0x21005f, 0x1ff },\n-\t{ 0x21015f, 0x1ff },\n-\t{ 0x21105f, 0x1ff },\n-\t{ 0x21115f, 0x1ff },\n-\t{ 0x21205f, 0x1ff },\n-\t{ 0x21215f, 0x1ff },\n-\t{ 0x21305f, 0x1ff },\n-\t{ 0x21315f, 0x1ff },\n-\t{ 0x55, 0x1ff },\n-\t{ 0x1055, 0x1ff },\n-\t{ 0x2055, 0x1ff },\n-\t{ 0x3055, 0x1ff },\n-\t{ 0x4055, 0x1ff },\n-\t{ 0x5055, 0x1ff },\n-\t{ 0x6055, 0x1ff },\n-\t{ 0x7055, 0x1ff },\n-\t{ 0x8055, 0x1ff },\n-\t{ 0x9055, 0x1ff },\n-\t{ 0x200c5, 0x19 },\n-\t{ 0x1200c5, 0x7 },\n-\t{ 0x2200c5, 0x7 },\n-\t{ 0x2002e, 0x2 },\n-\t{ 0x12002e, 0x2 },\n-\t{ 0x22002e, 0x2 },\n-\t{ 0x90204, 0x0 },\n-\t{ 0x190204, 0x0 },\n-\t{ 0x290204, 0x0 },\n-\t{ 0x20024, 0x1e3 },\n-\t{ 0x2003a, 0x2 },\n-\t{ 0x120024, 0x1e3 },\n-\t{ 0x2003a, 0x2 },\n-\t{ 0x220024, 0x1e3 },\n-\t{ 0x2003a, 0x2 },\n-\t{ 0x20056, 0x3 },\n-\t{ 0x120056, 0x3 },\n-\t{ 0x220056, 0x3 },\n-\t{ 0x1004d, 0xe00 },\n-\t{ 0x1014d, 0xe00 },\n-\t{ 0x1104d, 0xe00 },\n-\t{ 0x1114d, 0xe00 },\n-\t{ 0x1204d, 0xe00 },\n-\t{ 0x1214d, 0xe00 },\n-\t{ 0x1304d, 0xe00 },\n-\t{ 0x1314d, 0xe00 },\n-\t{ 0x11004d, 0xe00 },\n-\t{ 0x11014d, 0xe00 },\n-\t{ 0x11104d, 0xe00 },\n-\t{ 0x11114d, 0xe00 },\n-\t{ 0x11204d, 0xe00 },\n-\t{ 0x11214d, 0xe00 },\n-\t{ 0x11304d, 0xe00 },\n-\t{ 0x11314d, 0xe00 },\n-\t{ 0x21004d, 0xe00 },\n-\t{ 0x21014d, 0xe00 },\n-\t{ 0x21104d, 0xe00 },\n-\t{ 0x21114d, 0xe00 },\n-\t{ 0x21204d, 0xe00 },\n-\t{ 0x21214d, 0xe00 },\n-\t{ 0x21304d, 0xe00 },\n-\t{ 0x21314d, 0xe00 },\n-\t{ 0x10049, 0xeba },\n-\t{ 0x10149, 0xeba },\n-\t{ 0x11049, 0xeba },\n-\t{ 0x11149, 0xeba },\n-\t{ 0x12049, 0xeba },\n-\t{ 0x12149, 0xeba },\n-\t{ 0x13049, 0xeba },\n-\t{ 0x13149, 0xeba },\n-\t{ 0x110049, 0xeba },\n-\t{ 0x110149, 0xeba },\n-\t{ 0x111049, 0xeba },\n-\t{ 0x111149, 0xeba },\n-\t{ 0x112049, 0xeba },\n-\t{ 0x112149, 0xeba },\n-\t{ 0x113049, 0xeba },\n-\t{ 0x113149, 0xeba },\n-\t{ 0x210049, 0xeba },\n-\t{ 0x210149, 0xeba },\n-\t{ 0x211049, 0xeba },\n-\t{ 0x211149, 0xeba },\n-\t{ 0x212049, 0xeba },\n-\t{ 0x212149, 0xeba },\n-\t{ 0x213049, 0xeba },\n-\t{ 0x213149, 0xeba },\n-\t{ 0x43, 0x63 },\n-\t{ 0x1043, 0x63 },\n-\t{ 0x2043, 0x63 },\n-\t{ 0x3043, 0x63 },\n-\t{ 0x4043, 0x63 },\n-\t{ 0x5043, 0x63 },\n-\t{ 0x6043, 0x63 },\n-\t{ 0x7043, 0x63 },\n-\t{ 0x8043, 0x63 },\n-\t{ 0x9043, 0x63 },\n-\t{ 0x20018, 0x3 },\n-\t{ 0x20075, 0x4 },\n-\t{ 0x20050, 0x0 },\n-\t{ 0x20008, 0x384 },\n-\t{ 0x120008, 0x64 },\n-\t{ 0x220008, 0x19 },\n-\t{ 0x20088, 0x9 },\n-\t{ 0x200b2, 0x104 },\n-\t{ 0x10043, 0x5a1 },\n-\t{ 0x10143, 0x5a1 },\n-\t{ 0x11043, 0x5a1 },\n-\t{ 0x11143, 0x5a1 },\n-\t{ 0x12043, 0x5a1 },\n-\t{ 0x12143, 0x5a1 },\n-\t{ 0x13043, 0x5a1 },\n-\t{ 0x13143, 0x5a1 },\n-\t{ 0x1200b2, 0x104 },\n-\t{ 0x110043, 0x5a1 },\n-\t{ 0x110143, 0x5a1 },\n-\t{ 0x111043, 0x5a1 },\n-\t{ 0x111143, 0x5a1 },\n-\t{ 0x112043, 0x5a1 },\n-\t{ 0x112143, 0x5a1 },\n-\t{ 0x113043, 0x5a1 },\n-\t{ 0x113143, 0x5a1 },\n-\t{ 0x2200b2, 0x104 },\n-\t{ 0x210043, 0x5a1 },\n-\t{ 0x210143, 0x5a1 },\n-\t{ 0x211043, 0x5a1 },\n-\t{ 0x211143, 0x5a1 },\n-\t{ 0x212043, 0x5a1 },\n-\t{ 0x212143, 0x5a1 },\n-\t{ 0x213043, 0x5a1 },\n-\t{ 0x213143, 0x5a1 },\n-\t{ 0x200fa, 0x1 },\n-\t{ 0x1200fa, 0x1 },\n-\t{ 0x2200fa, 0x1 },\n-\t{ 0x20019, 0x1 },\n-\t{ 0x120019, 0x1 },\n-\t{ 0x220019, 0x1 },\n-\t{ 0x200f0, 0x660 },\n-\t{ 0x200f1, 0x0 },\n-\t{ 0x200f2, 0x4444 },\n-\t{ 0x200f3, 0x8888 },\n-\t{ 0x200f4, 0x5665 },\n-\t{ 0x200f5, 0x0 },\n-\t{ 0x200f6, 0x0 },\n-\t{ 0x200f7, 0xf000 },\n-\t{ 0x20025, 0x0 },\n-\t{ 0x2002d, 0x1 },\n-\t{ 0x12002d, 0x1 },\n-\t{ 0x22002d, 0x1 },\n-\t{ 0x2007d, 0x212 },\n-\t{ 0x12007d, 0x212 },\n-\t{ 0x22007d, 0x212 },\n-\t{ 0x2007c, 0x61 },\n-\t{ 0x12007c, 0x61 },\n-\t{ 0x22007c, 0x61 },\n-\t{ 0x2002c, 0x0 },\n-};\n-\n-/* ddr phy trained csr */\n-static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {\n-\t{ 0x200b2, 0x0 },\n-\t{ 0x1200b2, 0x0 },\n-\t{ 0x2200b2, 0x0 },\n-\t{ 0x200cb, 0x0 },\n-\t{ 0x10043, 0x0 },\n-\t{ 0x110043, 0x0 },\n-\t{ 0x210043, 0x0 },\n-\t{ 0x10143, 0x0 },\n-\t{ 0x110143, 0x0 },\n-\t{ 0x210143, 0x0 },\n-\t{ 0x11043, 0x0 },\n-\t{ 0x111043, 0x0 },\n-\t{ 0x211043, 0x0 },\n-\t{ 0x11143, 0x0 },\n-\t{ 0x111143, 0x0 },\n-\t{ 0x211143, 0x0 },\n-\t{ 0x12043, 0x0 },\n-\t{ 0x112043, 0x0 },\n-\t{ 0x212043, 0x0 },\n-\t{ 0x12143, 0x0 },\n-\t{ 0x112143, 0x0 },\n-\t{ 0x212143, 0x0 },\n-\t{ 0x13043, 0x0 },\n-\t{ 0x113043, 0x0 },\n-\t{ 0x213043, 0x0 },\n-\t{ 0x13143, 0x0 },\n-\t{ 0x113143, 0x0 },\n-\t{ 0x213143, 0x0 },\n-\t{ 0x80, 0x0 },\n-\t{ 0x100080, 0x0 },\n-\t{ 0x200080, 0x0 },\n-\t{ 0x1080, 0x0 },\n-\t{ 0x101080, 0x0 },\n-\t{ 0x201080, 0x0 },\n-\t{ 0x2080, 0x0 },\n-\t{ 0x102080, 0x0 },\n-\t{ 0x202080, 0x0 },\n-\t{ 0x3080, 0x0 },\n-\t{ 0x103080, 0x0 },\n-\t{ 0x203080, 0x0 },\n-\t{ 0x4080, 0x0 },\n-\t{ 0x104080, 0x0 },\n-\t{ 0x204080, 0x0 },\n-\t{ 0x5080, 0x0 },\n-\t{ 0x105080, 0x0 },\n-\t{ 0x205080, 0x0 },\n-\t{ 0x6080, 0x0 },\n-\t{ 0x106080, 0x0 },\n-\t{ 0x206080, 0x0 },\n-\t{ 0x7080, 0x0 },\n-\t{ 0x107080, 0x0 },\n-\t{ 0x207080, 0x0 },\n-\t{ 0x8080, 0x0 },\n-\t{ 0x108080, 0x0 },\n-\t{ 0x208080, 0x0 },\n-\t{ 0x9080, 0x0 },\n-\t{ 0x109080, 0x0 },\n-\t{ 0x209080, 0x0 },\n-\t{ 0x10080, 0x0 },\n-\t{ 0x110080, 0x0 },\n-\t{ 0x210080, 0x0 },\n-\t{ 0x10180, 0x0 },\n-\t{ 0x110180, 0x0 },\n-\t{ 0x210180, 0x0 },\n-\t{ 0x11080, 0x0 },\n-\t{ 0x111080, 0x0 },\n-\t{ 0x211080, 0x0 },\n-\t{ 0x11180, 0x0 },\n-\t{ 0x111180, 0x0 },\n-\t{ 0x211180, 0x0 },\n-\t{ 0x12080, 0x0 },\n-\t{ 0x112080, 0x0 },\n-\t{ 0x212080, 0x0 },\n-\t{ 0x12180, 0x0 },\n-\t{ 0x112180, 0x0 },\n-\t{ 0x212180, 0x0 },\n-\t{ 0x13080, 0x0 },\n-\t{ 0x113080, 0x0 },\n-\t{ 0x213080, 0x0 },\n-\t{ 0x13180, 0x0 },\n-\t{ 0x113180, 0x0 },\n-\t{ 0x213180, 0x0 },\n-\t{ 0x10081, 0x0 },\n-\t{ 0x110081, 0x0 },\n-\t{ 0x210081, 0x0 },\n-\t{ 0x10181, 0x0 },\n-\t{ 0x110181, 0x0 },\n-\t{ 0x210181, 0x0 },\n-\t{ 0x11081, 0x0 },\n-\t{ 0x111081, 0x0 },\n-\t{ 0x211081, 0x0 },\n-\t{ 0x11181, 0x0 },\n-\t{ 0x111181, 0x0 },\n-\t{ 0x211181, 0x0 },\n-\t{ 0x12081, 0x0 },\n-\t{ 0x112081, 0x0 },\n-\t{ 0x212081, 0x0 },\n-\t{ 0x12181, 0x0 },\n-\t{ 0x112181, 0x0 },\n-\t{ 0x212181, 0x0 },\n-\t{ 0x13081, 0x0 },\n-\t{ 0x113081, 0x0 },\n-\t{ 0x213081, 0x0 },\n-\t{ 0x13181, 0x0 },\n-\t{ 0x113181, 0x0 },\n-\t{ 0x213181, 0x0 },\n-\t{ 0x100d0, 0x0 },\n-\t{ 0x1100d0, 0x0 },\n-\t{ 0x2100d0, 0x0 },\n-\t{ 0x101d0, 0x0 },\n-\t{ 0x1101d0, 0x0 },\n-\t{ 0x2101d0, 0x0 },\n-\t{ 0x110d0, 0x0 },\n-\t{ 0x1110d0, 0x0 },\n-\t{ 0x2110d0, 0x0 },\n-\t{ 0x111d0, 0x0 },\n-\t{ 0x1111d0, 0x0 },\n-\t{ 0x2111d0, 0x0 },\n-\t{ 0x120d0, 0x0 },\n-\t{ 0x1120d0, 0x0 },\n-\t{ 0x2120d0, 0x0 },\n-\t{ 0x121d0, 0x0 },\n-\t{ 0x1121d0, 0x0 },\n-\t{ 0x2121d0, 0x0 },\n-\t{ 0x130d0, 0x0 },\n-\t{ 0x1130d0, 0x0 },\n-\t{ 0x2130d0, 0x0 },\n-\t{ 0x131d0, 0x0 },\n-\t{ 0x1131d0, 0x0 },\n-\t{ 0x2131d0, 0x0 },\n-\t{ 0x100d1, 0x0 },\n-\t{ 0x1100d1, 0x0 },\n-\t{ 0x2100d1, 0x0 },\n-\t{ 0x101d1, 0x0 },\n-\t{ 0x1101d1, 0x0 },\n-\t{ 0x2101d1, 0x0 },\n-\t{ 0x110d1, 0x0 },\n-\t{ 0x1110d1, 0x0 },\n-\t{ 0x2110d1, 0x0 },\n-\t{ 0x111d1, 0x0 },\n-\t{ 0x1111d1, 0x0 },\n-\t{ 0x2111d1, 0x0 },\n-\t{ 0x120d1, 0x0 },\n-\t{ 0x1120d1, 0x0 },\n-\t{ 0x2120d1, 0x0 },\n-\t{ 0x121d1, 0x0 },\n-\t{ 0x1121d1, 0x0 },\n-\t{ 0x2121d1, 0x0 },\n-\t{ 0x130d1, 0x0 },\n-\t{ 0x1130d1, 0x0 },\n-\t{ 0x2130d1, 0x0 },\n-\t{ 0x131d1, 0x0 },\n-\t{ 0x1131d1, 0x0 },\n-\t{ 0x2131d1, 0x0 },\n-\t{ 0x10068, 0x0 },\n-\t{ 0x10168, 0x0 },\n-\t{ 0x10268, 0x0 },\n-\t{ 0x10368, 0x0 },\n-\t{ 0x10468, 0x0 },\n-\t{ 0x10568, 0x0 },\n-\t{ 0x10668, 0x0 },\n-\t{ 0x10768, 0x0 },\n-\t{ 0x10868, 0x0 },\n-\t{ 0x11068, 0x0 },\n-\t{ 0x11168, 0x0 },\n-\t{ 0x11268, 0x0 },\n-\t{ 0x11368, 0x0 },\n-\t{ 0x11468, 0x0 },\n-\t{ 0x11568, 0x0 },\n-\t{ 0x11668, 0x0 },\n-\t{ 0x11768, 0x0 },\n-\t{ 0x11868, 0x0 },\n-\t{ 0x12068, 0x0 },\n-\t{ 0x12168, 0x0 },\n-\t{ 0x12268, 0x0 },\n-\t{ 0x12368, 0x0 },\n-\t{ 0x12468, 0x0 },\n-\t{ 0x12568, 0x0 },\n-\t{ 0x12668, 0x0 },\n-\t{ 0x12768, 0x0 },\n-\t{ 0x12868, 0x0 },\n-\t{ 0x13068, 0x0 },\n-\t{ 0x13168, 0x0 },\n-\t{ 0x13268, 0x0 },\n-\t{ 0x13368, 0x0 },\n-\t{ 0x13468, 0x0 },\n-\t{ 0x13568, 0x0 },\n-\t{ 0x13668, 0x0 },\n-\t{ 0x13768, 0x0 },\n-\t{ 0x13868, 0x0 },\n-\t{ 0x10069, 0x0 },\n-\t{ 0x10169, 0x0 },\n-\t{ 0x10269, 0x0 },\n-\t{ 0x10369, 0x0 },\n-\t{ 0x10469, 0x0 },\n-\t{ 0x10569, 0x0 },\n-\t{ 0x10669, 0x0 },\n-\t{ 0x10769, 0x0 },\n-\t{ 0x10869, 0x0 },\n-\t{ 0x11069, 0x0 },\n-\t{ 0x11169, 0x0 },\n-\t{ 0x11269, 0x0 },\n-\t{ 0x11369, 0x0 },\n-\t{ 0x11469, 0x0 },\n-\t{ 0x11569, 0x0 },\n-\t{ 0x11669, 0x0 },\n-\t{ 0x11769, 0x0 },\n-\t{ 0x11869, 0x0 },\n-\t{ 0x12069, 0x0 },\n-\t{ 0x12169, 0x0 },\n-\t{ 0x12269, 0x0 },\n-\t{ 0x12369, 0x0 },\n-\t{ 0x12469, 0x0 },\n-\t{ 0x12569, 0x0 },\n-\t{ 0x12669, 0x0 },\n-\t{ 0x12769, 0x0 },\n-\t{ 0x12869, 0x0 },\n-\t{ 0x13069, 0x0 },\n-\t{ 0x13169, 0x0 },\n-\t{ 0x13269, 0x0 },\n-\t{ 0x13369, 0x0 },\n-\t{ 0x13469, 0x0 },\n-\t{ 0x13569, 0x0 },\n-\t{ 0x13669, 0x0 },\n-\t{ 0x13769, 0x0 },\n-\t{ 0x13869, 0x0 },\n-\t{ 0x1008c, 0x0 },\n-\t{ 0x11008c, 0x0 },\n-\t{ 0x21008c, 0x0 },\n-\t{ 0x1018c, 0x0 },\n-\t{ 0x11018c, 0x0 },\n-\t{ 0x21018c, 0x0 },\n-\t{ 0x1108c, 0x0 },\n-\t{ 0x11108c, 0x0 },\n-\t{ 0x21108c, 0x0 },\n-\t{ 0x1118c, 0x0 },\n-\t{ 0x11118c, 0x0 },\n-\t{ 0x21118c, 0x0 },\n-\t{ 0x1208c, 0x0 },\n-\t{ 0x11208c, 0x0 },\n-\t{ 0x21208c, 0x0 },\n-\t{ 0x1218c, 0x0 },\n-\t{ 0x11218c, 0x0 },\n-\t{ 0x21218c, 0x0 },\n-\t{ 0x1308c, 0x0 },\n-\t{ 0x11308c, 0x0 },\n-\t{ 0x21308c, 0x0 },\n-\t{ 0x1318c, 0x0 },\n-\t{ 0x11318c, 0x0 },\n-\t{ 0x21318c, 0x0 },\n-\t{ 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0x90208, 0x0 },\n-\t{ 0x190208, 0x0 },\n-\t{ 0x290208, 0x0 },\n-\t{ 0x10062, 0x0 },\n-\t{ 0x10162, 0x0 },\n-\t{ 0x10262, 0x0 },\n-\t{ 0x10362, 0x0 },\n-\t{ 0x10462, 0x0 },\n-\t{ 0x10562, 0x0 },\n-\t{ 0x10662, 0x0 },\n-\t{ 0x10762, 0x0 },\n-\t{ 0x10862, 0x0 },\n-\t{ 0x11062, 0x0 },\n-\t{ 0x11162, 0x0 },\n-\t{ 0x11262, 0x0 },\n-\t{ 0x11362, 0x0 },\n-\t{ 0x11462, 0x0 },\n-\t{ 0x11562, 0x0 },\n-\t{ 0x11662, 0x0 },\n-\t{ 0x11762, 0x0 },\n-\t{ 0x11862, 0x0 },\n-\t{ 0x12062, 0x0 },\n-\t{ 0x12162, 0x0 },\n-\t{ 0x12262, 0x0 },\n-\t{ 0x12362, 0x0 },\n-\t{ 0x12462, 0x0 },\n-\t{ 0x12562, 0x0 },\n-\t{ 0x12662, 0x0 },\n-\t{ 0x12762, 0x0 },\n-\t{ 0x12862, 0x0 },\n-\t{ 0x13062, 0x0 },\n-\t{ 0x13162, 0x0 },\n-\t{ 0x13262, 0x0 },\n-\t{ 0x13362, 0x0 },\n-\t{ 0x13462, 0x0 },\n-\t{ 0x13562, 0x0 },\n-\t{ 0x13662, 0x0 },\n-\t{ 0x13762, 0x0 },\n-\t{ 0x13862, 0x0 },\n-\t{ 0x20077, 0x0 },\n-\t{ 0x10001, 0x0 },\n-\t{ 0x11001, 0x0 },\n-\t{ 0x12001, 0x0 },\n-\t{ 0x13001, 0x0 },\n-\t{ 0x10040, 0x0 },\n-\t{ 0x10140, 0x0 },\n-\t{ 0x10240, 0x0 },\n-\t{ 0x10340, 0x0 },\n-\t{ 0x10440, 0x0 },\n-\t{ 0x10540, 0x0 },\n-\t{ 0x10640, 0x0 },\n-\t{ 0x10740, 0x0 },\n-\t{ 0x10840, 0x0 },\n-\t{ 0x10030, 0x0 },\n-\t{ 0x10130, 0x0 },\n-\t{ 0x10230, 0x0 },\n-\t{ 0x10330, 0x0 },\n-\t{ 0x10430, 0x0 },\n-\t{ 0x10530, 0x0 },\n-\t{ 0x10630, 0x0 },\n-\t{ 0x10730, 0x0 },\n-\t{ 0x10830, 0x0 },\n-\t{ 0x11040, 0x0 },\n-\t{ 0x11140, 0x0 },\n-\t{ 0x11240, 0x0 },\n-\t{ 0x11340, 0x0 },\n-\t{ 0x11440, 0x0 },\n-\t{ 0x11540, 0x0 },\n-\t{ 0x11640, 0x0 },\n-\t{ 0x11740, 0x0 },\n-\t{ 0x11840, 0x0 },\n-\t{ 0x11030, 0x0 },\n-\t{ 0x11130, 0x0 },\n-\t{ 0x11230, 0x0 },\n-\t{ 0x11330, 0x0 },\n-\t{ 0x11430, 0x0 },\n-\t{ 0x11530, 0x0 },\n-\t{ 0x11630, 0x0 },\n-\t{ 0x11730, 0x0 },\n-\t{ 0x11830, 0x0 },\n-\t{ 0x12040, 0x0 },\n-\t{ 0x12140, 0x0 },\n-\t{ 0x12240, 0x0 },\n-\t{ 0x12340, 0x0 },\n-\t{ 0x12440, 0x0 },\n-\t{ 0x12540, 0x0 },\n-\t{ 0x12640, 0x0 },\n-\t{ 0x12740, 0x0 },\n-\t{ 0x12840, 0x0 },\n-\t{ 0x12030, 0x0 },\n-\t{ 0x12130, 0x0 },\n-\t{ 0x12230, 0x0 },\n-\t{ 0x12330, 0x0 },\n-\t{ 0x12430, 0x0 },\n-\t{ 0x12530, 0x0 },\n-\t{ 0x12630, 0x0 },\n-\t{ 0x12730, 0x0 },\n-\t{ 0x12830, 0x0 },\n-\t{ 0x13040, 0x0 },\n-\t{ 0x13140, 0x0 },\n-\t{ 0x13240, 0x0 },\n-\t{ 0x13340, 0x0 },\n-\t{ 0x13440, 0x0 },\n-\t{ 0x13540, 0x0 },\n-\t{ 0x13640, 0x0 },\n-\t{ 0x13740, 0x0 },\n-\t{ 0x13840, 0x0 },\n-\t{ 0x13030, 0x0 },\n-\t{ 0x13130, 0x0 },\n-\t{ 0x13230, 0x0 },\n-\t{ 0x13330, 0x0 },\n-\t{ 0x13430, 0x0 },\n-\t{ 0x13530, 0x0 },\n-\t{ 0x13630, 0x0 },\n-\t{ 0x13730, 0x0 },\n-\t{ 0x13830, 0x0 },\n-};\n-\n-/* P0 message block paremeter for training firmware */\n-static struct dram_cfg_param ddr_fsp0_cfg[] = {\n-\t{ 0xd0000, 0x0 },\n-\t{ 0x54003, 0xe10 },\n-\t{ 0x54004, 0x2 },\n-\t{ 0x54005, 0x2228 },\n-\t{ 0x54006, 0x14 },\n-\t{ 0x54008, 0x131f },\n-\t{ 0x54009, 0xc8 },\n-\t{ 0x5400b, 0x2 },\n-\t{ 0x5400f, 0x100 },\n-\t{ 0x54012, 0x310 },\n-\t{ 0x54019, 0x36e4 },\n-\t{ 0x5401a, 0xf3 },\n-\t{ 0x5401b, 0x4866 },\n-\t{ 0x5401c, 0x4800 },\n-\t{ 0x5401e, 0x16 },\n-\t{ 0x5401f, 0x36e4 },\n-\t{ 0x54020, 0xf3 },\n-\t{ 0x54021, 0x4866 },\n-\t{ 0x54022, 0x4800 },\n-\t{ 0x54024, 0x16 },\n-\t{ 0x5402b, 0x1000 },\n-\t{ 0x5402c, 0x3 },\n-\t{ 0x54032, 0xe400 },\n-\t{ 0x54033, 0xf336 },\n-\t{ 0x54034, 0x6600 },\n-\t{ 0x54035, 0x48 },\n-\t{ 0x54036, 0x48 },\n-\t{ 0x54037, 0x1600 },\n-\t{ 0x54038, 0xe400 },\n-\t{ 0x54039, 0xf336 },\n-\t{ 0x5403a, 0x6600 },\n-\t{ 0x5403b, 0x48 },\n-\t{ 0x5403c, 0x48 },\n-\t{ 0x5403d, 0x1600 },\n-\t{ 0xd0000, 0x1 },\n-};\n-\n-/* P1 message block paremeter for training firmware */\n-static struct dram_cfg_param ddr_fsp1_cfg[] = {\n-\t{ 0xd0000, 0x0 },\n-\t{ 0x54002, 0x101 },\n-\t{ 0x54003, 0x190 },\n-\t{ 0x54004, 0x2 },\n-\t{ 0x54005, 0x2228 },\n-\t{ 0x54006, 0x14 },\n-\t{ 0x54008, 0x121f },\n-\t{ 0x54009, 0xc8 },\n-\t{ 0x5400b, 0x2 },\n-\t{ 0x5400f, 0x100 },\n-\t{ 0x54012, 0x310 },\n-\t{ 0x54019, 0x84 },\n-\t{ 0x5401a, 0xf3 },\n-\t{ 0x5401b, 0x4866 },\n-\t{ 0x5401c, 0x4800 },\n-\t{ 0x5401e, 0x16 },\n-\t{ 0x5401f, 0x84 },\n-\t{ 0x54020, 0xf3 },\n-\t{ 0x54021, 0x4866 },\n-\t{ 0x54022, 0x4800 },\n-\t{ 0x54024, 0x16 },\n-\t{ 0x5402b, 0x1000 },\n-\t{ 0x5402c, 0x3 },\n-\t{ 0x54032, 0x8400 },\n-\t{ 0x54033, 0xf300 },\n-\t{ 0x54034, 0x6600 },\n-\t{ 0x54035, 0x48 },\n-\t{ 0x54036, 0x48 },\n-\t{ 0x54037, 0x1600 },\n-\t{ 0x54038, 0x8400 },\n-\t{ 0x54039, 0xf300 },\n-\t{ 0x5403a, 0x6600 },\n-\t{ 0x5403b, 0x48 },\n-\t{ 0x5403c, 0x48 },\n-\t{ 0x5403d, 0x1600 },\n-\t{ 0xd0000, 0x1 },\n-};\n-\n-/* P2 message block paremeter for training firmware */\n-static struct dram_cfg_param ddr_fsp2_cfg[] = {\n-\t{ 0xd0000, 0x0 },\n-\t{ 0x54002, 0x102 },\n-\t{ 0x54003, 0x64 },\n-\t{ 0x54004, 0x2 },\n-\t{ 0x54005, 0x2228 },\n-\t{ 0x54006, 0x14 },\n-\t{ 0x54008, 0x121f },\n-\t{ 0x54009, 0xc8 },\n-\t{ 0x5400b, 0x2 },\n-\t{ 0x5400f, 0x100 },\n-\t{ 0x54012, 0x310 },\n-\t{ 0x54019, 0x84 },\n-\t{ 0x5401a, 0xf3 },\n-\t{ 0x5401b, 0x4866 },\n-\t{ 0x5401c, 0x4800 },\n-\t{ 0x5401e, 0x16 },\n-\t{ 0x5401f, 0x84 },\n-\t{ 0x54020, 0xf3 },\n-\t{ 0x54021, 0x4866 },\n-\t{ 0x54022, 0x4800 },\n-\t{ 0x54024, 0x16 },\n-\t{ 0x5402b, 0x1000 },\n-\t{ 0x5402c, 0x3 },\n-\t{ 0x54032, 0x8400 },\n-\t{ 0x54033, 0xf300 },\n-\t{ 0x54034, 0x6600 },\n-\t{ 0x54035, 0x48 },\n-\t{ 0x54036, 0x48 },\n-\t{ 0x54037, 0x1600 },\n-\t{ 0x54038, 0x8400 },\n-\t{ 0x54039, 0xf300 },\n-\t{ 0x5403a, 0x6600 },\n-\t{ 0x5403b, 0x48 },\n-\t{ 0x5403c, 0x48 },\n-\t{ 0x5403d, 0x1600 },\n-\t{ 0xd0000, 0x1 },\n-};\n-\n-/* P0 2D message block paremeter for training firmware */\n-static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {\n-\t{ 0xd0000, 0x0 },\n-\t{ 0x54003, 0xe10 },\n-\t{ 0x54004, 0x2 },\n-\t{ 0x54005, 0x2228 },\n-\t{ 0x54006, 0x14 },\n-\t{ 0x54008, 0x61 },\n-\t{ 0x54009, 0xc8 },\n-\t{ 0x5400b, 0x2 },\n-\t{ 0x5400f, 0x100 },\n-\t{ 0x54010, 0x1f7f },\n-\t{ 0x54012, 0x310 },\n-\t{ 0x54019, 0x36e4 },\n-\t{ 0x5401a, 0xf3 },\n-\t{ 0x5401b, 0x4866 },\n-\t{ 0x5401c, 0x4800 },\n-\t{ 0x5401e, 0x16 },\n-\t{ 0x5401f, 0x36e4 },\n-\t{ 0x54020, 0xf3 },\n-\t{ 0x54021, 0x4866 },\n-\t{ 0x54022, 0x4800 },\n-\t{ 0x54024, 0x16 },\n-\t{ 0x5402b, 0x1000 },\n-\t{ 0x5402c, 0x3 },\n-\t{ 0x54032, 0xe400 },\n-\t{ 0x54033, 0xf336 },\n-\t{ 0x54034, 0x6600 },\n-\t{ 0x54035, 0x48 },\n-\t{ 0x54036, 0x48 },\n-\t{ 0x54037, 0x1600 },\n-\t{ 0x54038, 0xe400 },\n-\t{ 0x54039, 0xf336 },\n-\t{ 0x5403a, 0x6600 },\n-\t{ 0x5403b, 0x48 },\n-\t{ 0x5403c, 0x48 },\n-\t{ 0x5403d, 0x1600 },\n-\t{ 0xd0000, 0x1 },\n-};\n-\n-/* DRAM PHY init engine image */\n-static struct dram_cfg_param ddr_phy_pie[] = {\n-\t{ 0xd0000, 0x0 },\n-\t{ 0x90000, 0x10 },\n-\t{ 0x90001, 0x400 },\n-\t{ 0x90002, 0x10e },\n-\t{ 0x90003, 0x0 },\n-\t{ 0x90004, 0x0 },\n-\t{ 0x90005, 0x8 },\n-\t{ 0x90029, 0xb },\n-\t{ 0x9002a, 0x480 },\n-\t{ 0x9002b, 0x109 },\n-\t{ 0x9002c, 0x8 },\n-\t{ 0x9002d, 0x448 },\n-\t{ 0x9002e, 0x139 },\n-\t{ 0x9002f, 0x8 },\n-\t{ 0x90030, 0x478 },\n-\t{ 0x90031, 0x109 },\n-\t{ 0x90032, 0x0 },\n-\t{ 0x90033, 0xe8 },\n-\t{ 0x90034, 0x109 },\n-\t{ 0x90035, 0x2 },\n-\t{ 0x90036, 0x10 },\n-\t{ 0x90037, 0x139 },\n-\t{ 0x90038, 0xb },\n-\t{ 0x90039, 0x7c0 },\n-\t{ 0x9003a, 0x139 },\n-\t{ 0x9003b, 0x44 },\n-\t{ 0x9003c, 0x633 },\n-\t{ 0x9003d, 0x159 },\n-\t{ 0x9003e, 0x14f },\n-\t{ 0x9003f, 0x630 },\n-\t{ 0x90040, 0x159 },\n-\t{ 0x90041, 0x47 },\n-\t{ 0x90042, 0x633 },\n-\t{ 0x90043, 0x149 },\n-\t{ 0x90044, 0x4f },\n-\t{ 0x90045, 0x633 },\n-\t{ 0x90046, 0x179 },\n-\t{ 0x90047, 0x8 },\n-\t{ 0x90048, 0xe0 },\n-\t{ 0x90049, 0x109 },\n-\t{ 0x9004a, 0x0 },\n-\t{ 0x9004b, 0x7c8 },\n-\t{ 0x9004c, 0x109 },\n-\t{ 0x9004d, 0x0 },\n-\t{ 0x9004e, 0x1 },\n-\t{ 0x9004f, 0x8 },\n-\t{ 0x90050, 0x0 },\n-\t{ 0x90051, 0x45a },\n-\t{ 0x90052, 0x9 },\n-\t{ 0x90053, 0x0 },\n-\t{ 0x90054, 0x448 },\n-\t{ 0x90055, 0x109 },\n-\t{ 0x90056, 0x40 },\n-\t{ 0x90057, 0x633 },\n-\t{ 0x90058, 0x179 },\n-\t{ 0x90059, 0x1 },\n-\t{ 0x9005a, 0x618 },\n-\t{ 0x9005b, 0x109 },\n-\t{ 0x9005c, 0x40c0 },\n-\t{ 0x9005d, 0x633 },\n-\t{ 0x9005e, 0x149 },\n-\t{ 0x9005f, 0x8 },\n-\t{ 0x90060, 0x4 },\n-\t{ 0x90061, 0x48 },\n-\t{ 0x90062, 0x4040 },\n-\t{ 0x90063, 0x633 },\n-\t{ 0x90064, 0x149 },\n-\t{ 0x90065, 0x0 },\n-\t{ 0x90066, 0x4 },\n-\t{ 0x90067, 0x48 },\n-\t{ 0x90068, 0x40 },\n-\t{ 0x90069, 0x633 },\n-\t{ 0x9006a, 0x149 },\n-\t{ 0x9006b, 0x10 },\n-\t{ 0x9006c, 0x4 },\n-\t{ 0x9006d, 0x18 },\n-\t{ 0x9006e, 0x0 },\n-\t{ 0x9006f, 0x4 },\n-\t{ 0x90070, 0x78 },\n-\t{ 0x90071, 0x549 },\n-\t{ 0x90072, 0x633 },\n-\t{ 0x90073, 0x159 },\n-\t{ 0x90074, 0xd49 },\n-\t{ 0x90075, 0x633 },\n-\t{ 0x90076, 0x159 },\n-\t{ 0x90077, 0x94a },\n-\t{ 0x90078, 0x633 },\n-\t{ 0x90079, 0x159 },\n-\t{ 0x9007a, 0x441 },\n-\t{ 0x9007b, 0x633 },\n-\t{ 0x9007c, 0x149 },\n-\t{ 0x9007d, 0x42 },\n-\t{ 0x9007e, 0x633 },\n-\t{ 0x9007f, 0x149 },\n-\t{ 0x90080, 0x1 },\n-\t{ 0x90081, 0x633 },\n-\t{ 0x90082, 0x149 },\n-\t{ 0x90083, 0x0 },\n-\t{ 0x90084, 0xe0 },\n-\t{ 0x90085, 0x109 },\n-\t{ 0x90086, 0xa },\n-\t{ 0x90087, 0x10 },\n-\t{ 0x90088, 0x109 },\n-\t{ 0x90089, 0x9 },\n-\t{ 0x9008a, 0x3c0 },\n-\t{ 0x9008b, 0x149 },\n-\t{ 0x9008c, 0x9 },\n-\t{ 0x9008d, 0x3c0 },\n-\t{ 0x9008e, 0x159 },\n-\t{ 0x9008f, 0x18 },\n-\t{ 0x90090, 0x10 },\n-\t{ 0x90091, 0x109 },\n-\t{ 0x90092, 0x0 },\n-\t{ 0x90093, 0x3c0 },\n-\t{ 0x90094, 0x109 },\n-\t{ 0x90095, 0x18 },\n-\t{ 0x90096, 0x4 },\n-\t{ 0x90097, 0x48 },\n-\t{ 0x90098, 0x18 },\n-\t{ 0x90099, 0x4 },\n-\t{ 0x9009a, 0x58 },\n-\t{ 0x9009b, 0xb },\n-\t{ 0x9009c, 0x10 },\n-\t{ 0x9009d, 0x109 },\n-\t{ 0x9009e, 0x1 },\n-\t{ 0x9009f, 0x10 },\n-\t{ 0x900a0, 0x109 },\n-\t{ 0x900a1, 0x5 },\n-\t{ 0x900a2, 0x7c0 },\n-\t{ 0x900a3, 0x109 },\n-\t{ 0x40000, 0x811 },\n-\t{ 0x40020, 0x880 },\n-\t{ 0x40040, 0x0 },\n-\t{ 0x40060, 0x0 },\n-\t{ 0x40001, 0x4008 },\n-\t{ 0x40021, 0x83 },\n-\t{ 0x40041, 0x4f },\n-\t{ 0x40061, 0x0 },\n-\t{ 0x40002, 0x4040 },\n-\t{ 0x40022, 0x83 },\n-\t{ 0x40042, 0x51 },\n-\t{ 0x40062, 0x0 },\n-\t{ 0x40003, 0x811 },\n-\t{ 0x40023, 0x880 },\n-\t{ 0x40043, 0x0 },\n-\t{ 0x40063, 0x0 },\n-\t{ 0x40004, 0x720 },\n-\t{ 0x40024, 0xf },\n-\t{ 0x40044, 0x1740 },\n-\t{ 0x40064, 0x0 },\n-\t{ 0x40005, 0x16 },\n-\t{ 0x40025, 0x83 },\n-\t{ 0x40045, 0x4b },\n-\t{ 0x40065, 0x0 },\n-\t{ 0x40006, 0x716 },\n-\t{ 0x40026, 0xf },\n-\t{ 0x40046, 0x2001 },\n-\t{ 0x40066, 0x0 },\n-\t{ 0x40007, 0x716 },\n-\t{ 0x40027, 0xf },\n-\t{ 0x40047, 0x2800 },\n-\t{ 0x40067, 0x0 },\n-\t{ 0x40008, 0x716 },\n-\t{ 0x40028, 0xf },\n-\t{ 0x40048, 0xf00 },\n-\t{ 0x40068, 0x0 },\n-\t{ 0x40009, 0x720 },\n-\t{ 0x40029, 0xf },\n-\t{ 0x40049, 0x1400 },\n-\t{ 0x40069, 0x0 },\n-\t{ 0x4000a, 0xe08 },\n-\t{ 0x4002a, 0xc15 },\n-\t{ 0x4004a, 0x0 },\n-\t{ 0x4006a, 0x0 },\n-\t{ 0x4000b, 0x625 },\n-\t{ 0x4002b, 0x15 },\n-\t{ 0x4004b, 0x0 },\n-\t{ 0x4006b, 0x0 },\n-\t{ 0x4000c, 0x4028 },\n-\t{ 0x4002c, 0x80 },\n-\t{ 0x4004c, 0x0 },\n-\t{ 0x4006c, 0x0 },\n-\t{ 0x4000d, 0xe08 },\n-\t{ 0x4002d, 0xc1a },\n-\t{ 0x4004d, 0x0 },\n-\t{ 0x4006d, 0x0 },\n-\t{ 0x4000e, 0x625 },\n-\t{ 0x4002e, 0x1a },\n-\t{ 0x4004e, 0x0 },\n-\t{ 0x4006e, 0x0 },\n-\t{ 0x4000f, 0x4040 },\n-\t{ 0x4002f, 0x80 },\n-\t{ 0x4004f, 0x0 },\n-\t{ 0x4006f, 0x0 },\n-\t{ 0x40010, 0x2604 },\n-\t{ 0x40030, 0x15 },\n-\t{ 0x40050, 0x0 },\n-\t{ 0x40070, 0x0 },\n-\t{ 0x40011, 0x708 },\n-\t{ 0x40031, 0x5 },\n-\t{ 0x40051, 0x0 },\n-\t{ 0x40071, 0x2002 },\n-\t{ 0x40012, 0x8 },\n-\t{ 0x40032, 0x80 },\n-\t{ 0x40052, 0x0 },\n-\t{ 0x40072, 0x0 },\n-\t{ 0x40013, 0x2604 },\n-\t{ 0x40033, 0x1a },\n-\t{ 0x40053, 0x0 },\n-\t{ 0x40073, 0x0 },\n-\t{ 0x40014, 0x708 },\n-\t{ 0x40034, 0xa },\n-\t{ 0x40054, 0x0 },\n-\t{ 0x40074, 0x2002 },\n-\t{ 0x40015, 0x4040 },\n-\t{ 0x40035, 0x80 },\n-\t{ 0x40055, 0x0 },\n-\t{ 0x40075, 0x0 },\n-\t{ 0x40016, 0x60a },\n-\t{ 0x40036, 0x15 },\n-\t{ 0x40056, 0x1200 },\n-\t{ 0x40076, 0x0 },\n-\t{ 0x40017, 0x61a },\n-\t{ 0x40037, 0x15 },\n-\t{ 0x40057, 0x1300 },\n-\t{ 0x40077, 0x0 },\n-\t{ 0x40018, 0x60a },\n-\t{ 0x40038, 0x1a },\n-\t{ 0x40058, 0x1200 },\n-\t{ 0x40078, 0x0 },\n-\t{ 0x40019, 0x642 },\n-\t{ 0x40039, 0x1a },\n-\t{ 0x40059, 0x1300 },\n-\t{ 0x40079, 0x0 },\n-\t{ 0x4001a, 0x4808 },\n-\t{ 0x4003a, 0x880 },\n-\t{ 0x4005a, 0x0 },\n-\t{ 0x4007a, 0x0 },\n-\t{ 0x900a4, 0x0 },\n-\t{ 0x900a5, 0x790 },\n-\t{ 0x900a6, 0x11a },\n-\t{ 0x900a7, 0x8 },\n-\t{ 0x900a8, 0x7aa },\n-\t{ 0x900a9, 0x2a },\n-\t{ 0x900aa, 0x10 },\n-\t{ 0x900ab, 0x7b2 },\n-\t{ 0x900ac, 0x2a },\n-\t{ 0x900ad, 0x0 },\n-\t{ 0x900ae, 0x7c8 },\n-\t{ 0x900af, 0x109 },\n-\t{ 0x900b0, 0x10 },\n-\t{ 0x900b1, 0x10 },\n-\t{ 0x900b2, 0x109 },\n-\t{ 0x900b3, 0x10 },\n-\t{ 0x900b4, 0x2a8 },\n-\t{ 0x900b5, 0x129 },\n-\t{ 0x900b6, 0x8 },\n-\t{ 0x900b7, 0x370 },\n-\t{ 0x900b8, 0x129 },\n-\t{ 0x900b9, 0xa },\n-\t{ 0x900ba, 0x3c8 },\n-\t{ 0x900bb, 0x1a9 },\n-\t{ 0x900bc, 0xc },\n-\t{ 0x900bd, 0x408 },\n-\t{ 0x900be, 0x199 },\n-\t{ 0x900bf, 0x14 },\n-\t{ 0x900c0, 0x790 },\n-\t{ 0x900c1, 0x11a },\n-\t{ 0x900c2, 0x8 },\n-\t{ 0x900c3, 0x4 },\n-\t{ 0x900c4, 0x18 },\n-\t{ 0x900c5, 0xe },\n-\t{ 0x900c6, 0x408 },\n-\t{ 0x900c7, 0x199 },\n-\t{ 0x900c8, 0x8 },\n-\t{ 0x900c9, 0x8568 },\n-\t{ 0x900ca, 0x108 },\n-\t{ 0x900cb, 0x18 },\n-\t{ 0x900cc, 0x790 },\n-\t{ 0x900cd, 0x16a },\n-\t{ 0x900ce, 0x8 },\n-\t{ 0x900cf, 0x1d8 },\n-\t{ 0x900d0, 0x169 },\n-\t{ 0x900d1, 0x10 },\n-\t{ 0x900d2, 0x8558 },\n-\t{ 0x900d3, 0x168 },\n-\t{ 0x900d4, 0x70 },\n-\t{ 0x900d5, 0x788 },\n-\t{ 0x900d6, 0x16a },\n-\t{ 0x900d7, 0x1ff8 },\n-\t{ 0x900d8, 0x85a8 },\n-\t{ 0x900d9, 0x1e8 },\n-\t{ 0x900da, 0x50 },\n-\t{ 0x900db, 0x798 },\n-\t{ 0x900dc, 0x16a },\n-\t{ 0x900dd, 0x60 },\n-\t{ 0x900de, 0x7a0 },\n-\t{ 0x900df, 0x16a },\n-\t{ 0x900e0, 0x8 },\n-\t{ 0x900e1, 0x8310 },\n-\t{ 0x900e2, 0x168 },\n-\t{ 0x900e3, 0x8 },\n-\t{ 0x900e4, 0xa310 },\n-\t{ 0x900e5, 0x168 },\n-\t{ 0x900e6, 0xa },\n-\t{ 0x900e7, 0x408 },\n-\t{ 0x900e8, 0x169 },\n-\t{ 0x900e9, 0x6e },\n-\t{ 0x900ea, 0x0 },\n-\t{ 0x900eb, 0x68 },\n-\t{ 0x900ec, 0x0 },\n-\t{ 0x900ed, 0x408 },\n-\t{ 0x900ee, 0x169 },\n-\t{ 0x900ef, 0x0 },\n-\t{ 0x900f0, 0x8310 },\n-\t{ 0x900f1, 0x168 },\n-\t{ 0x900f2, 0x0 },\n-\t{ 0x900f3, 0xa310 },\n-\t{ 0x900f4, 0x168 },\n-\t{ 0x900f5, 0x1ff8 },\n-\t{ 0x900f6, 0x85a8 },\n-\t{ 0x900f7, 0x1e8 },\n-\t{ 0x900f8, 0x68 },\n-\t{ 0x900f9, 0x798 },\n-\t{ 0x900fa, 0x16a },\n-\t{ 0x900fb, 0x78 },\n-\t{ 0x900fc, 0x7a0 },\n-\t{ 0x900fd, 0x16a },\n-\t{ 0x900fe, 0x68 },\n-\t{ 0x900ff, 0x790 },\n-\t{ 0x90100, 0x16a },\n-\t{ 0x90101, 0x8 },\n-\t{ 0x90102, 0x8b10 },\n-\t{ 0x90103, 0x168 },\n-\t{ 0x90104, 0x8 },\n-\t{ 0x90105, 0xab10 },\n-\t{ 0x90106, 0x168 },\n-\t{ 0x90107, 0xa },\n-\t{ 0x90108, 0x408 },\n-\t{ 0x90109, 0x169 },\n-\t{ 0x9010a, 0x58 },\n-\t{ 0x9010b, 0x0 },\n-\t{ 0x9010c, 0x68 },\n-\t{ 0x9010d, 0x0 },\n-\t{ 0x9010e, 0x408 },\n-\t{ 0x9010f, 0x169 },\n-\t{ 0x90110, 0x0 },\n-\t{ 0x90111, 0x8b10 },\n-\t{ 0x90112, 0x168 },\n-\t{ 0x90113, 0x1 },\n-\t{ 0x90114, 0xab10 },\n-\t{ 0x90115, 0x168 },\n-\t{ 0x90116, 0x0 },\n-\t{ 0x90117, 0x1d8 },\n-\t{ 0x90118, 0x169 },\n-\t{ 0x90119, 0x80 },\n-\t{ 0x9011a, 0x790 },\n-\t{ 0x9011b, 0x16a },\n-\t{ 0x9011c, 0x18 },\n-\t{ 0x9011d, 0x7aa },\n-\t{ 0x9011e, 0x6a },\n-\t{ 0x9011f, 0xa },\n-\t{ 0x90120, 0x0 },\n-\t{ 0x90121, 0x1e9 },\n-\t{ 0x90122, 0x8 },\n-\t{ 0x90123, 0x8080 },\n-\t{ 0x90124, 0x108 },\n-\t{ 0x90125, 0xf },\n-\t{ 0x90126, 0x408 },\n-\t{ 0x90127, 0x169 },\n-\t{ 0x90128, 0xc },\n-\t{ 0x90129, 0x0 },\n-\t{ 0x9012a, 0x68 },\n-\t{ 0x9012b, 0x9 },\n-\t{ 0x9012c, 0x0 },\n-\t{ 0x9012d, 0x1a9 },\n-\t{ 0x9012e, 0x0 },\n-\t{ 0x9012f, 0x408 },\n-\t{ 0x90130, 0x169 },\n-\t{ 0x90131, 0x0 },\n-\t{ 0x90132, 0x8080 },\n-\t{ 0x90133, 0x108 },\n-\t{ 0x90134, 0x8 },\n-\t{ 0x90135, 0x7aa },\n-\t{ 0x90136, 0x6a },\n-\t{ 0x90137, 0x0 },\n-\t{ 0x90138, 0x8568 },\n-\t{ 0x90139, 0x108 },\n-\t{ 0x9013a, 0xb7 },\n-\t{ 0x9013b, 0x790 },\n-\t{ 0x9013c, 0x16a },\n-\t{ 0x9013d, 0x1f },\n-\t{ 0x9013e, 0x0 },\n-\t{ 0x9013f, 0x68 },\n-\t{ 0x90140, 0x8 },\n-\t{ 0x90141, 0x8558 },\n-\t{ 0x90142, 0x168 },\n-\t{ 0x90143, 0xf },\n-\t{ 0x90144, 0x408 },\n-\t{ 0x90145, 0x169 },\n-\t{ 0x90146, 0xd },\n-\t{ 0x90147, 0x0 },\n-\t{ 0x90148, 0x68 },\n-\t{ 0x90149, 0x0 },\n-\t{ 0x9014a, 0x408 },\n-\t{ 0x9014b, 0x169 },\n-\t{ 0x9014c, 0x0 },\n-\t{ 0x9014d, 0x8558 },\n-\t{ 0x9014e, 0x168 },\n-\t{ 0x9014f, 0x8 },\n-\t{ 0x90150, 0x3c8 },\n-\t{ 0x90151, 0x1a9 },\n-\t{ 0x90152, 0x3 },\n-\t{ 0x90153, 0x370 },\n-\t{ 0x90154, 0x129 },\n-\t{ 0x90155, 0x20 },\n-\t{ 0x90156, 0x2aa },\n-\t{ 0x90157, 0x9 },\n-\t{ 0x90158, 0x8 },\n-\t{ 0x90159, 0xe8 },\n-\t{ 0x9015a, 0x109 },\n-\t{ 0x9015b, 0x0 },\n-\t{ 0x9015c, 0x8140 },\n-\t{ 0x9015d, 0x10c },\n-\t{ 0x9015e, 0x10 },\n-\t{ 0x9015f, 0x8138 },\n-\t{ 0x90160, 0x104 },\n-\t{ 0x90161, 0x8 },\n-\t{ 0x90162, 0x448 },\n-\t{ 0x90163, 0x109 },\n-\t{ 0x90164, 0xf },\n-\t{ 0x90165, 0x7c0 },\n-\t{ 0x90166, 0x109 },\n-\t{ 0x90167, 0x0 },\n-\t{ 0x90168, 0xe8 },\n-\t{ 0x90169, 0x109 },\n-\t{ 0x9016a, 0x47 },\n-\t{ 0x9016b, 0x630 },\n-\t{ 0x9016c, 0x109 },\n-\t{ 0x9016d, 0x8 },\n-\t{ 0x9016e, 0x618 },\n-\t{ 0x9016f, 0x109 },\n-\t{ 0x90170, 0x8 },\n-\t{ 0x90171, 0xe0 },\n-\t{ 0x90172, 0x109 },\n-\t{ 0x90173, 0x0 },\n-\t{ 0x90174, 0x7c8 },\n-\t{ 0x90175, 0x109 },\n-\t{ 0x90176, 0x8 },\n-\t{ 0x90177, 0x8140 },\n-\t{ 0x90178, 0x10c },\n-\t{ 0x90179, 0x0 },\n-\t{ 0x9017a, 0x478 },\n-\t{ 0x9017b, 0x109 },\n-\t{ 0x9017c, 0x0 },\n-\t{ 0x9017d, 0x1 },\n-\t{ 0x9017e, 0x8 },\n-\t{ 0x9017f, 0x8 },\n-\t{ 0x90180, 0x4 },\n-\t{ 0x90181, 0x0 },\n-\t{ 0x90006, 0x8 },\n-\t{ 0x90007, 0x7c8 },\n-\t{ 0x90008, 0x109 },\n-\t{ 0x90009, 0x0 },\n-\t{ 0x9000a, 0x400 },\n-\t{ 0x9000b, 0x106 },\n-\t{ 0xd00e7, 0x400 },\n-\t{ 0x90017, 0x0 },\n-\t{ 0x9001f, 0x29 },\n-\t{ 0x90026, 0x68 },\n-\t{ 0x400d0, 0x0 },\n-\t{ 0x400d1, 0x101 },\n-\t{ 0x400d2, 0x105 },\n-\t{ 0x400d3, 0x107 },\n-\t{ 0x400d4, 0x10f },\n-\t{ 0x400d5, 0x202 },\n-\t{ 0x400d6, 0x20a },\n-\t{ 0x400d7, 0x20b },\n-\t{ 0x2003a, 0x2 },\n-\t{ 0x200be, 0x3 },\n-\t{ 0x2000b, 0x3f4 },\n-\t{ 0x2000c, 0xe1 },\n-\t{ 0x2000d, 0x8ca },\n-\t{ 0x2000e, 0x2c },\n-\t{ 0x12000b, 0x70 },\n-\t{ 0x12000c, 0x19 },\n-\t{ 0x12000d, 0xfa },\n-\t{ 0x12000e, 0x10 },\n-\t{ 0x22000b, 0x1c },\n-\t{ 0x22000c, 0x6 },\n-\t{ 0x22000d, 0x3e },\n-\t{ 0x22000e, 0x10 },\n-\t{ 0x9000c, 0x0 },\n-\t{ 0x9000d, 0x173 },\n-\t{ 0x9000e, 0x60 },\n-\t{ 0x9000f, 0x6110 },\n-\t{ 0x90010, 0x2152 },\n-\t{ 0x90011, 0xdfbd },\n-\t{ 0x90012, 0x2060 },\n-\t{ 0x90013, 0x6152 },\n-\t{ 0x20010, 0x5a },\n-\t{ 0x20011, 0x3 },\n-\t{ 0x40080, 0xe0 },\n-\t{ 0x40081, 0x12 },\n-\t{ 0x40082, 0xe0 },\n-\t{ 0x40083, 0x12 },\n-\t{ 0x40084, 0xe0 },\n-\t{ 0x40085, 0x12 },\n-\t{ 0x140080, 0xe0 },\n-\t{ 0x140081, 0x12 },\n-\t{ 0x140082, 0xe0 },\n-\t{ 0x140083, 0x12 },\n-\t{ 0x140084, 0xe0 },\n-\t{ 0x140085, 0x12 },\n-\t{ 0x240080, 0xe0 },\n-\t{ 0x240081, 0x12 },\n-\t{ 0x240082, 0xe0 },\n-\t{ 0x240083, 0x12 },\n-\t{ 0x240084, 0xe0 },\n-\t{ 0x240085, 0x12 },\n-\t{ 0x400fd, 0xf },\n-\t{ 0x10011, 0x1 },\n-\t{ 0x10012, 0x1 },\n-\t{ 0x10013, 0x180 },\n-\t{ 0x10018, 0x1 },\n-\t{ 0x10002, 0x6209 },\n-\t{ 0x100b2, 0x1 },\n-\t{ 0x101b4, 0x1 },\n-\t{ 0x102b4, 0x1 },\n-\t{ 0x103b4, 0x1 },\n-\t{ 0x104b4, 0x1 },\n-\t{ 0x105b4, 0x1 },\n-\t{ 0x106b4, 0x1 },\n-\t{ 0x107b4, 0x1 },\n-\t{ 0x108b4, 0x1 },\n-\t{ 0x11011, 0x1 },\n-\t{ 0x11012, 0x1 },\n-\t{ 0x11013, 0x180 },\n-\t{ 0x11018, 0x1 },\n-\t{ 0x11002, 0x6209 },\n-\t{ 0x110b2, 0x1 },\n-\t{ 0x111b4, 0x1 },\n-\t{ 0x112b4, 0x1 },\n-\t{ 0x113b4, 0x1 },\n-\t{ 0x114b4, 0x1 },\n-\t{ 0x115b4, 0x1 },\n-\t{ 0x116b4, 0x1 },\n-\t{ 0x117b4, 0x1 },\n-\t{ 0x118b4, 0x1 },\n-\t{ 0x12011, 0x1 },\n-\t{ 0x12012, 0x1 },\n-\t{ 0x12013, 0x180 },\n-\t{ 0x12018, 0x1 },\n-\t{ 0x12002, 0x6209 },\n-\t{ 0x120b2, 0x1 },\n-\t{ 0x121b4, 0x1 },\n-\t{ 0x122b4, 0x1 },\n-\t{ 0x123b4, 0x1 },\n-\t{ 0x124b4, 0x1 },\n-\t{ 0x125b4, 0x1 },\n-\t{ 0x126b4, 0x1 },\n-\t{ 0x127b4, 0x1 },\n-\t{ 0x128b4, 0x1 },\n-\t{ 0x13011, 0x1 },\n-\t{ 0x13012, 0x1 },\n-\t{ 0x13013, 0x180 },\n-\t{ 0x13018, 0x1 },\n-\t{ 0x13002, 0x6209 },\n-\t{ 0x130b2, 0x1 },\n-\t{ 0x131b4, 0x1 },\n-\t{ 0x132b4, 0x1 },\n-\t{ 0x133b4, 0x1 },\n-\t{ 0x134b4, 0x1 },\n-\t{ 0x135b4, 0x1 },\n-\t{ 0x136b4, 0x1 },\n-\t{ 0x137b4, 0x1 },\n-\t{ 0x138b4, 0x1 },\n-\t{ 0x20089, 0x1 },\n-\t{ 0x20088, 0x19 },\n-\t{ 0xc0080, 0x2 },\n-\t{ 0xd0000, 0x1 }\n-};\n-\n-static struct dram_fsp_msg ddr_dram_fsp_msg[] = {\n-\t{\n-\t\t/* P0 3600mts 1D */\n-\t\t.drate = 3600,\n-\t\t.fw_type = FW_1D_IMAGE,\n-\t\t.fsp_cfg = ddr_fsp0_cfg,\n-\t\t.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),\n-\t},\n-\t{\n-\t\t/* P1 400mts 1D */\n-\t\t.drate = 400,\n-\t\t.fw_type = FW_1D_IMAGE,\n-\t\t.fsp_cfg = ddr_fsp1_cfg,\n-\t\t.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),\n-\t},\n-\t{\n-\t\t/* P2 100mts 1D */\n-\t\t.drate = 100,\n-\t\t.fw_type = FW_1D_IMAGE,\n-\t\t.fsp_cfg = ddr_fsp2_cfg,\n-\t\t.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),\n-\t},\n-\t{\n-\t\t/* P0 3600mts 2D */\n-\t\t.drate = 3600,\n-\t\t.fw_type = FW_2D_IMAGE,\n-\t\t.fsp_cfg = ddr_fsp0_2d_cfg,\n-\t\t.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),\n-\t},\n-};\n-\n-/* ddr timing config params */\n-struct dram_timing_info dh_imx8mp_dhcom_dram_timing_32g_x32 = {\n-\t.ddrc_cfg = ddr_ddrc_cfg,\n-\t.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),\n-\t.ddrphy_cfg = ddr_ddrphy_cfg,\n-\t.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),\n-\t.fsp_msg = ddr_dram_fsp_msg,\n-\t.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),\n-\t.ddrphy_trained_csr = ddr_ddrphy_trained_csr,\n-\t.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),\n-\t.ddrphy_pie = ddr_phy_pie,\n-\t.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),\n-\t.fsp_table = { 3600, 400, 100, },\n-};\ndiff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c\nindex ece790da66a..8b9dddab79a 100644\n--- a/board/dhelectronics/dh_imx8mp/spl.c\n+++ b/board/dhelectronics/dh_imx8mp/spl.c\n@@ -104,15 +104,17 @@ static int dh_imx8mp_board_power_init(void)\n \treturn 0;\n }\n \n-static struct dram_timing_info *dram_timing_info[8] = {\n-\tNULL,\t\t\t\t\t/* 512 MiB */\n-\tNULL,\t\t\t\t\t/* 1024 MiB */\n-\tNULL,\t\t\t\t\t/* 1536 MiB */\n-\t&dh_imx8mp_dhcom_dram_timing_16g_x32,\t/* 2048 MiB */\n-\tNULL,\t\t\t\t\t/* 3072 MiB */\n-\t&dh_imx8mp_dhcom_dram_timing_32g_x32,\t/* 4096 MiB */\n-\tNULL,\t\t\t\t\t/* 6144 MiB */\n-\tNULL,\t\t\t\t\t/* 8192 MiB */\n+typedef void (*patch_func_t)(void);\n+\n+static const patch_func_t dram_patch_fn[8] = {\n+\tNULL,\t\t\t\t\t\t\t/* 512 MiB */\n+\tNULL,\t\t\t\t\t\t\t/* 1024 MiB */\n+\tNULL,\t\t\t\t\t\t\t/* 1536 MiB */\n+\tdh_imx8mp_dhcom_dram_patch_16g_x32_to_16g_x32,\t\t/* 2048 MiB */\n+\tNULL,\t\t\t\t\t\t\t/* 3072 MiB */\n+\tdh_imx8mp_dhcom_dram_patch_16g_x32_to_32g_x32_2r,\t/* 4096 MiB 2-rank */\n+\tNULL,\t\t\t\t\t\t\t/* 6144 MiB */\n+\tNULL,\t\t\t\t\t\t\t/* 8192 MiB */\n };\n \n static void spl_dram_init(void)\n@@ -122,15 +124,16 @@ static void spl_dram_init(void)\n \n \tprintf(\"DDR: %d MiB [0x%x]\\n\", dh_imx8mp_dhcom_dram_size[memcfg], memcfg);\n \n-\tif (!dram_timing_info[memcfg]) {\n+\tif (!dram_patch_fn[memcfg]) {\n \t\tprintf(\"Unsupported DRAM strapping, trying lowest supported. MEMCFG=0x%x\\n\",\n \t\t memcfg);\n-\t\tfor (i = 0; i < ARRAY_SIZE(dram_timing_info); i++)\n-\t\t\tif (dram_timing_info[i])\t/* Configuration found */\n+\t\tfor (i = 0; i < ARRAY_SIZE(dram_patch_fn); i++)\n+\t\t\tif (dram_patch_fn[i])\t/* Configuration found */\n \t\t\t\tbreak;\n \t}\n \n-\tddr_init(dram_timing_info[memcfg]);\n+\tdram_patch_fn[memcfg]();\n+\tddr_init(dh_imx8mp_dhcom_dram_timing);\n \n \tprintf(\"DDR: Inline ECC %sabled\\n\",\n \t (readl(DDRC_ECCCFG0(0)) & DDRC_ECCCFG0_ECC_MODE_MASK) ?\n@@ -170,7 +173,7 @@ static const scrub_func_t dram_scrub_fn[8] = {\n \tNULL,\t\t\t\t\t/* 1536 MiB */\n \tdh_imx8mp_dhcom_dram_scrub_16g_x32,\t/* 2048 MiB */\n \tNULL,\t\t\t\t\t/* 3072 MiB */\n-\tdh_imx8mp_dhcom_dram_scrub_32g_x32,\t/* 4096 MiB */\n+\tdh_imx8mp_dhcom_dram_scrub_32g_x32,\t/* 4096 MiB 2-rank */\n \tNULL,\t\t\t\t\t/* 6144 MiB */\n \tNULL,\t\t\t\t\t/* 8192 MiB */\n };\n", "prefixes": [ "3/4" ] }