Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2218764/?format=api
{ "id": 2218764, "url": "http://patchwork.ozlabs.org/api/patches/2218764/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260401213831.187569-3-suneelg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401213831.187569-3-suneelg@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T21:38:30", "name": "[2/3] hte: tegra194: Add Tegra264 GTE support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e399371b996265572bc39c72d4c1b93f68351eb", "submitter": { "id": 93021, "url": "http://patchwork.ozlabs.org/api/people/93021/?format=api", "name": "Suneel Garapati", "email": "suneelg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260401213831.187569-3-suneelg@nvidia.com/mbox/", "series": [ { "id": 498395, "url": "http://patchwork.ozlabs.org/api/series/498395/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=498395", "date": "2026-04-01T21:38:30", "name": "Add Tegra264 HTE provider", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498395/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218764/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218764/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13519-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=essWss//;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13519-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"essWss//\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=52.101.85.52", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmJL92Vdzz1yFv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 08:40:01 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 372983020EB4\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 1 Apr 2026 21:39:26 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id C563C369985;\n\tWed, 1 Apr 2026 21:39:25 +0000 (UTC)", "from BYAPR05CU005.outbound.protection.outlook.com\n (mail-westusazon11010052.outbound.protection.outlook.com [52.101.85.52])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 223B026299;\n\tWed, 1 Apr 2026 21:39:23 +0000 (UTC)", "from SJ2PR07CA0009.namprd07.prod.outlook.com (2603:10b6:a03:505::6)\n by DS0PR12MB6559.namprd12.prod.outlook.com (2603:10b6:8:d1::6) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9769.10; Wed, 1 Apr 2026 21:39:18 +0000", "from SJ5PEPF00000208.namprd05.prod.outlook.com\n (2603:10b6:a03:505:cafe::8) by SJ2PR07CA0009.outlook.office365.com\n (2603:10b6:a03:505::6) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9745.29 via Frontend Transport; Wed,\n 1 Apr 2026 21:39:17 +0000", "from mail.nvidia.com (216.228.117.161) by\n SJ5PEPF00000208.mail.protection.outlook.com (10.167.244.41) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9769.17 via Frontend Transport; Wed, 1 Apr 2026 21:39:17 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 1 Apr\n 2026 14:39:01 -0700", "from build-suneelg-jammy-20260204.internal (10.126.230.35) by\n rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.2562.20; Wed, 1 Apr 2026 14:38:59 -0700" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775079565; cv=fail;\n b=NbEHFUi1ohA//C85zuflBEswI8WdS2Hv4C4g5j3kZPGtx17lL3aMOJCjA3N9DOXF67t1nQoq1zQ6WyArqa+jCNNSoXGv5bf8GuLegHdwIT2y16un7y48J6joLaeJvq4clzQ7tKIbPs+kTUF0Y3wAA5VQ+7J1NAeiDCLEI3srZuw=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=yq272BETEKYLowCjwaHQWzCYoBtM4Jd3YI5GqhPN9Haun92Mr2jBWqC5uMICgvomIqyhmNkjs/9+drgV+HfNLLKhHolpahMPPOmLua7syer+333PiRSZtRVY55hNnibcZ/sHFT27s7fcSH+qRJXsObSP4YqnT1aNDStLcQfYzjaT03AXLK+09iCjqNB/4+hS1BBYSZsZL6nOdYGVGv3dOUBhyxcHTr6BMHSN/0fr51o9Fa68mP7vXt/lE6RHANPvbduz43A9lnhTDbla59u+RK7tJs8NbmcH5TU+waDBMugCVMa5e7gc9qu+v/0tm1qNkHCdiVsTk6IgRqZhcRPL1Q==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775079565; c=relaxed/simple;\n\tbh=g846JjvWG4WhfJ3hN2NgLOI0yIAMgfMRAKuroKIb7dA=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=ij2HpoCo7uOb0kNToDKk/BEG6N0X/vBG7KP1+adScz2BBAfX+CdSYXV/VwM3R7N5ThdIcDCGu33+hHjAcKQKaQdj0VUtGK+s9nHlU5UgbycFQMpEEWDtvKNs/3M5aUBRqEJCzAgmDcuFAETU806rmVCNn9HGN6KjTmdfzKo2rDc=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=az7i3yFJClaQFHZd5y+MNbffAWModNfUk7UGn5JhgCo=;\n b=lfYlno4uspp/sJDlVszplqW5Ot867y01/APaZjDACJtYowgTiQWucaPeURXdnwpzn/ztW0cG8h9YrNxtx1OiEErUqza8QLDW3hme38PGq2o0Z4n4FuKKGupBWrHQj4LyxlPjxhyymflvUGgqRNgnFe3u6sReBRVNibKnXYFz8XrNrjEKGvYnkjoN0GJfr7OrMgGeZcMzp+bIQRatsT47YhitBXTHl1LWf8YQe8ml/A/Q5wv2oPmo+D/rVdRSK+kxYiMm4bhNT4mWyxuaPojD+vt6M8sd68SyMuR4pwVkZu6co0xmzhvLfRfPkj75akkgrAbAEn+n+al3pTz6P9p4hA==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=essWss//; arc=fail smtp.client-ip=52.101.85.52", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=az7i3yFJClaQFHZd5y+MNbffAWModNfUk7UGn5JhgCo=;\n b=essWss//aMoIaWthOWyrXvpmP/ILvVkWC430OUl/+0Mue54fhG+HEI8PMSEm6UnLdcwvhQL2onN2nCmNQl0eSswrgsS8U132y7YqITj4/NG9sL7Re8Bl+Mpkb9gVDOqrsxb2CanAJHYYln9GdR0pbvPYw/E//INoZkiMsVgm6DAo9UtjPxjcLn9Y63HQcIDC5o2LFhVjm8tU4OsfbNY1aguuEt3hgV5ljc/DB+WlcNYwOzOAusJQi0KgsOISWMZsIw2h7z9YKYPvYx2Qh8IODniI9E4lJMAObWbZoeotUOxs4cyV9sicaXdAQSR01T0QudHHxfNfjvVSPNn0nuVOnQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Suneel Garapati <suneelg@nvidia.com>", "To": "<dipenp@nvidia.com>, <jonathanh@nvidia.com>, <thierry.reding@gmail.com>,\n\t<krzk+dt@kernel.org>, <conor+dt@kernel.org>, <amhetre@nvidia.com>,\n\t<sheetal@nvidia.com>, <kkartik@nvidia.com>, <robh@kernel.org>,\n\t<pshete@nvidia.com>, <timestamp@list.linux.dev>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Suneel Garapati <suneelg@nvidia.com>", "Subject": "[PATCH 2/3] hte: tegra194: Add Tegra264 GTE support", "Date": "Wed, 1 Apr 2026 21:38:30 +0000", "Message-ID": "<20260401213831.187569-3-suneelg@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401213831.187569-1-suneelg@nvidia.com>", "References": "<20260401213831.187569-1-suneelg@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF00000208:EE_|DS0PR12MB6559:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b5a34266-cbe1-4d6e-3820-08de903720a7", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|376014|36860700016|82310400026|921020|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tcne3wKfr7x1Aoar+wH6LCJoAR8YwZrXkgNk3ekq/o3ib5/K3GlWGBBHnYKs3tD8lJZtgMbPTFI2TK+j0cGcYqqf6dJyPdwXIewOCV00fuF5LSeUYK2loOoSOF4XsB1PkEZCZXNfN0NkFQ/iWBTASdY+WJr2YDuP/lCompp8CnF7LBcAVWRZ6skB2EklVeZU7KVRZTBBtm7r/EYeI+e5h2SyA0obv5PRs2Gg1u84E5vQ+BQ5XaCc24UnP2j121VJPExL6ibWY+ApY2sC5SQXYx7YmXOqcaZzowNpEVCK62/Up6egtWZ01wjf97ZTz7EjJ62h9VFw3RimQYcbVIZvgCYFZPvMl9MtewTStP4ycS1qszTzxwD0pBiXIb6HITqfNJ9HN6LWVSlwpwOsk1epitHHoWz8Rl3h95Wpmb5HQEgWgOmur5tsKFW9ndWYhm1yxX00v89XE+mugFMdEUwjOyO+P8IQuUacsOhox863L7VT2mcOPO+dZ5PrRKmWzDYruLcLRZZU2jsL+5y9+NAtX77xWS+qRMJ1i+psGuxM9cH/uWnaG2GpunA5WRsa5cZT9QO5YEgmVtODDt36cFLdF2LA+HSjYvGJcoBm+/ROfpIzNSpKoRajSewdCyIiELUXCiUs32ROSpRU7tr1Nqx/TAxqpwo0qca9eF9b7qNq0S58L3zMAqASmhSHPzmBAivCNIqBbU2WpBM1CMoM9ey9rgKrfm3p4rBh107iAHzlAgx0rfGjpKjY8Qbl5NpcxDlRb8re9JeTuFN33xDfYta2txt6bW8gSkFRN8/8op6wLFMVBDOMG75KcazYc17w1MaA8", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700016)(82310400026)(921020)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tuCy64vEFUCS0VCNBXQCKCTpi8SzGmrPc4RAzDgjPr9upCPtMmOJW2I2No5ZBJEGW/8LGh8sMtsJG9uT/XDo/PTUpFkV59SoXAgcYGlP++6xxTHKXcnIWe8wph2FpOhmsjCb2h+QB/qP7iZTDKUnEAMWaZwzay9RRz8+LnB1Wo/+1JItT6MpltwwhiWrQuA8EovP9iKcxCsFuIHtrqYlChZ4noc4BJvS3qOwDfrIXcGSJqGfqj5NgNnRpBwTI/d9BgAvlHmMjXmrXbmHQL9iitun5uQU3Oy/ckq1wHz0kdxD71mKskMbttphzdqj74TGoH/Rf/6KrMrW8oCbRAMPIxUomfuy39ugm8ySzVoUfGuzEMt+DVgp420PutygLOOfc6H7ZIeWiXBPPbyRRJPuTJBpTv0txn+sUUgp/z61rPYVdsBCIAR5ldhqEohcSXodk", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Apr 2026 21:39:17.7164\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b5a34266-cbe1-4d6e-3820-08de903720a7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ5PEPF00000208.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB6559" }, "content": "Add AON-GTE mapping and LIC GTE instance support for the Tegra264.\nMove TSC clock parameters from macros to members of SoC data\nas values differ for Tegra264 chip.\n\nSigned-off-by: Suneel Garapati <suneelg@nvidia.com>\n---\n drivers/hte/hte-tegra194.c | 133 +++++++++++++++++++++++++++++++++++--\n 1 file changed, 128 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c\nindex 690eb9be30fb..4a7702b32b24 100644\n--- a/drivers/hte/hte-tegra194.c\n+++ b/drivers/hte/hte-tegra194.c\n@@ -20,10 +20,11 @@\n \n #define HTE_SUSPEND\t0\n \n-/* HTE source clock TSC is 31.25MHz */\n+/* HTE source clock TSC is 1GHz for T264 and 31.25MHz for others */\n #define HTE_TS_CLK_RATE_HZ\t31250000ULL\n+#define HTE_TS_CLK_RATE_1G\t1000000000ULL\n #define HTE_CLK_RATE_NS\t\t32\n-#define HTE_TS_NS_SHIFT\t__builtin_ctz(HTE_CLK_RATE_NS)\n+#define HTE_CLK_RATE_NS_1G\t1\n \n #define NV_AON_SLICE_INVALID\t-1\n #define NV_LINES_IN_SLICE\t32\n@@ -120,6 +121,8 @@ struct tegra_hte_data {\n \tu32 slices;\n \tu32 map_sz;\n \tu32 sec_map_sz;\n+\tu64 tsc_clkrate_hz;\n+\tu32 tsc_clkrate_ns;\n \tconst struct tegra_hte_line_mapped *map;\n \tconst struct tegra_hte_line_mapped *sec_map;\n };\n@@ -317,6 +320,94 @@ static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {\n \t[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},\n };\n \n+static const struct tegra_hte_line_mapped tegra264_aon_gpio_map[] = {\n+\t/* gpio, slice, bit_index */\n+\t/* AA port */\n+\t[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},\n+\t[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},\n+\t[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},\n+\t[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},\n+\t[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},\n+\t[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},\n+\t[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},\n+\t[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},\n+\t/* BB port */\n+\t[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},\n+\t[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},\n+\t/* CC port */\n+\t[10] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},\n+\t[11] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},\n+\t[12] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},\n+\t[13] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},\n+\t[14] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},\n+\t[15] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},\n+\t[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},\n+\t[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},\n+\t/* DD port */\n+\t[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},\n+\t[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},\n+\t[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},\n+\t[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},\n+\t[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},\n+\t[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},\n+\t[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},\n+\t[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},\n+\t/* EE port */\n+\t[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},\n+\t[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},\n+\t[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},\n+\t[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},\n+};\n+\n+static const struct tegra_hte_line_mapped tegra264_aon_gpio_sec_map[] = {\n+\t/* gpio, slice, bit_index */\n+\t/* AA port */\n+\t[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},\n+\t[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},\n+\t[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},\n+\t[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},\n+\t[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},\n+\t[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},\n+\t[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},\n+\t[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},\n+\t/* BB port */\n+\t[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},\n+\t[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},\n+\t[10] = {NV_AON_SLICE_INVALID, 0},\n+\t[11] = {NV_AON_SLICE_INVALID, 0},\n+\t[12] = {NV_AON_SLICE_INVALID, 0},\n+\t[13] = {NV_AON_SLICE_INVALID, 0},\n+\t[14] = {NV_AON_SLICE_INVALID, 0},\n+\t[15] = {NV_AON_SLICE_INVALID, 0},\n+\t/* CC port */\n+\t[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},\n+\t[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},\n+\t[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},\n+\t[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},\n+\t[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},\n+\t[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},\n+\t[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},\n+\t[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},\n+\t/* DD port */\n+\t[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},\n+\t[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},\n+\t[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},\n+\t[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},\n+\t[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},\n+\t[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},\n+\t[30] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},\n+\t[31] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},\n+\t/* EE port */\n+\t[32] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},\n+\t[33] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},\n+\t[34] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},\n+\t[35] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},\n+\t[36] = {NV_AON_SLICE_INVALID, 0},\n+\t[37] = {NV_AON_SLICE_INVALID, 0},\n+\t[38] = {NV_AON_SLICE_INVALID, 0},\n+\t[39] = {NV_AON_SLICE_INVALID, 0},\n+};\n+\n static const struct tegra_hte_data t194_aon_hte = {\n \t.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),\n \t.map = tegra194_aon_gpio_map,\n@@ -324,6 +415,8 @@ static const struct tegra_hte_data t194_aon_hte = {\n \t.sec_map = tegra194_aon_gpio_sec_map,\n \t.type = HTE_TEGRA_TYPE_GPIO,\n \t.slices = 3,\n+\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n+\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n };\n \n static const struct tegra_hte_data t234_aon_hte = {\n@@ -333,6 +426,19 @@ static const struct tegra_hte_data t234_aon_hte = {\n \t.sec_map = tegra234_aon_gpio_sec_map,\n \t.type = HTE_TEGRA_TYPE_GPIO,\n \t.slices = 3,\n+\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n+\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n+};\n+\n+static const struct tegra_hte_data t264_aon_hte = {\n+\t.map_sz = ARRAY_SIZE(tegra264_aon_gpio_map),\n+\t.map = tegra264_aon_gpio_map,\n+\t.sec_map_sz = ARRAY_SIZE(tegra264_aon_gpio_sec_map),\n+\t.sec_map = tegra264_aon_gpio_sec_map,\n+\t.type = HTE_TEGRA_TYPE_GPIO,\n+\t.slices = 4,\n+\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,\n+\t.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,\n };\n \n static const struct tegra_hte_data t194_lic_hte = {\n@@ -340,6 +446,8 @@ static const struct tegra_hte_data t194_lic_hte = {\n \t.map = NULL,\n \t.type = HTE_TEGRA_TYPE_LIC,\n \t.slices = 11,\n+\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n+\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n };\n \n static const struct tegra_hte_data t234_lic_hte = {\n@@ -347,6 +455,17 @@ static const struct tegra_hte_data t234_lic_hte = {\n \t.map = NULL,\n \t.type = HTE_TEGRA_TYPE_LIC,\n \t.slices = 17,\n+\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,\n+\t.tsc_clkrate_ns = HTE_CLK_RATE_NS,\n+};\n+\n+static const struct tegra_hte_data t264_lic_hte = {\n+\t.map_sz = 0,\n+\t.map = NULL,\n+\t.type = HTE_TEGRA_TYPE_LIC,\n+\t.slices = 10,\n+\t.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,\n+\t.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,\n };\n \n static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)\n@@ -574,12 +693,12 @@ static int tegra_hte_release(struct hte_chip *chip, struct hte_ts_desc *desc,\n static int tegra_hte_clk_src_info(struct hte_chip *chip,\n \t\t\t\t struct hte_clk_info *ci)\n {\n-\t(void)chip;\n+\tstruct tegra_hte_soc *hte_dev = chip->data;\n \n \tif (!ci)\n \t\treturn -EINVAL;\n \n-\tci->hz = HTE_TS_CLK_RATE_HZ;\n+\tci->hz = hte_dev->prov_data->tsc_clkrate_hz;\n \tci->type = CLOCK_MONOTONIC;\n \n \treturn 0;\n@@ -602,8 +721,10 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)\n {\n \tu32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;\n \tu64 tsc;\n+\tu8 tsc_ns_shift;\n \tstruct hte_ts_data el;\n \n+\ttsc_ns_shift = __builtin_ctz(gs->prov_data->tsc_clkrate_ns);\n \twhile ((tegra_hte_readl(gs, HTE_TESTATUS) >>\n \t\tHTE_TESTATUS_OCCUPANCY_SHIFT) &\n \t\tHTE_TESTATUS_OCCUPANCY_MASK) {\n@@ -621,7 +742,7 @@ static void tegra_hte_read_fifo(struct tegra_hte_soc *gs)\n \t\twhile (acv) {\n \t\t\tbit_index = __builtin_ctz(acv);\n \t\t\tline_id = bit_index + (slice << 5);\n-\t\t\tel.tsc = tsc << HTE_TS_NS_SHIFT;\n+\t\t\tel.tsc = tsc << tsc_ns_shift;\n \t\t\tel.raw_level = tegra_hte_get_level(gs, line_id);\n \t\t\thte_push_ts_ns(gs->chip, line_id, &el);\n \t\t\tacv &= ~BIT(bit_index);\n@@ -656,6 +777,8 @@ static const struct of_device_id tegra_hte_of_match[] = {\n \t{ .compatible = \"nvidia,tegra194-gte-aon\", .data = &t194_aon_hte},\n \t{ .compatible = \"nvidia,tegra234-gte-lic\", .data = &t234_lic_hte},\n \t{ .compatible = \"nvidia,tegra234-gte-aon\", .data = &t234_aon_hte},\n+\t{ .compatible = \"nvidia,tegra264-gte-lic\", .data = &t264_lic_hte},\n+\t{ .compatible = \"nvidia,tegra264-gte-aon\", .data = &t264_aon_hte},\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, tegra_hte_of_match);\n", "prefixes": [ "2/3" ] }