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GET /api/patches/2218653/?format=api
{ "id": 2218653, "url": "http://patchwork.ozlabs.org/api/patches/2218653/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-38-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-38-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:57", "name": "[v6,37/37] target/hexagon: Add hex_interrupts support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7b8f2f059aae62cf7de8df60480b80be5b270a9e", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-38-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218653/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218653/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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<sidneym@quicinc.com>, Michael Lambert <mlambert@quicinc.com>", "Subject": "[PATCH v6 37/37] target/hexagon: Add hex_interrupts support", "Date": "Wed, 1 Apr 2026 08:26:57 -0700", "Message-Id": "<20260401152657.314902-38-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "References": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfXzFaFD1rkqbtd\n TxZMnJRuw5rIOPxUUf5fc0juyU6j3nlIbg3FIsSniqfYCRFKivASTPDce32KdMQ7EeG9cPoH7eq\n wnonN780Y8Xu/bLJGfDSv93QEvx3EWyxTLYXeCmyMfEImw5yiX+MbrKI80QZ6fDKxIj7NK9o4tT\n xZ4v5gO+1/BmoQaUI69CN/VhDIeG/4i/X43JpoZ8lQZA8s4pPMGIPfbGwL8awpvEEeAUIVGsXgB\n RZft3tpzxtsq5QcKx/AGNCoGxCA8ByKUyBXb9kdh6zzEJ4mB76jFFr4zXBxT4LUjyckG/3ZhR8r\n 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score=0\n phishscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0\n clxscore=1015 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nCo-authored-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nCo-authored-by: Sid Manning <sidneym@quicinc.com>\nCo-authored-by: Michael Lambert <mlambert@quicinc.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 2 +\n target/hexagon/hex_interrupts.h | 15 ++\n target/hexagon/cpu.c | 4 +\n target/hexagon/hex_interrupts.c | 379 ++++++++++++++++++++++++++++++++\n 4 files changed, 400 insertions(+)\n create mode 100644 target/hexagon/hex_interrupts.h\n create mode 100644 target/hexagon/hex_interrupts.c", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex c4fac9c2d38..3049b5a411a 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -196,6 +196,8 @@ struct ArchCPU {\n bool short_circuit;\n #ifndef CONFIG_USER_ONLY\n HexagonTLBState *tlb;\n+ uint32_t boot_addr;\n+ HexagonGlobalRegState *globalregs;\n uint32_t htid;\n #endif\n };\ndiff --git a/target/hexagon/hex_interrupts.h b/target/hexagon/hex_interrupts.h\nnew file mode 100644\nindex 00000000000..6b6f5403633\n--- /dev/null\n+++ b/target/hexagon/hex_interrupts.h\n@@ -0,0 +1,15 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEX_INTERRUPTS_H\n+#define HEX_INTERRUPTS_H\n+\n+bool hex_check_interrupts(CPUHexagonState *env);\n+void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type);\n+void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type);\n+void hex_interrupt_update(CPUHexagonState *env);\n+\n+#endif\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 4e9c65f785a..9ae8e104043 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -59,6 +59,9 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n \n static const Property hexagon_cpu_properties[] = {\n #if !defined(CONFIG_USER_ONLY)\n+ DEFINE_PROP_UINT32(\"exec-start-addr\", HexagonCPU, boot_addr, 0xffffffff),\n+ DEFINE_PROP_LINK(\"global-regs\", HexagonCPU, globalregs,\n+ TYPE_HEXAGON_GLOBALREG, HexagonGlobalRegState *),\n DEFINE_PROP_UINT32(\"htid\", HexagonCPU, htid, 0),\n #endif\n DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n@@ -341,6 +344,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n \n env->t_sreg[HEX_SREG_HTID] = cpu->htid;\n env->threadId = cpu->htid;\n+ env->gpr[HEX_REG_PC] = cpu->boot_addr;\n #endif\n env->cause_code = HEX_EVENT_NONE;\n }\ndiff --git a/target/hexagon/hex_interrupts.c b/target/hexagon/hex_interrupts.c\nnew file mode 100644\nindex 00000000000..c00b45e1c8b\n--- /dev/null\n+++ b/target/hexagon/hex_interrupts.c\n@@ -0,0 +1,379 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"cpu.h\"\n+#include \"cpu_helper.h\"\n+#include \"exec/cpu-interrupt.h\"\n+#include \"hex_interrupts.h\"\n+#include \"macros.h\"\n+#include \"sys_macros.h\"\n+#include \"system/cpus.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n+\n+static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num);\n+\n+static bool get_syscfg_gie(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t syscfg = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG,\n+ env->threadId) : 0;\n+ return GET_SYSCFG_FIELD(SYSCFG_GIE, syscfg);\n+}\n+\n+static bool get_ssr_ex(CPUHexagonState *env)\n+{\n+ uint32_t ssr = env->t_sreg[HEX_SREG_SSR];\n+ return GET_SSR_FIELD(SSR_EX, ssr);\n+}\n+\n+static bool get_ssr_ie(CPUHexagonState *env)\n+{\n+ uint32_t ssr = env->t_sreg[HEX_SREG_SSR];\n+ return GET_SSR_FIELD(SSR_IE, ssr);\n+}\n+\n+/* Do these together so we only have to call hexagon_modify_ssr once */\n+static void set_ssr_ex_cause(CPUHexagonState *env, int ex, uint32_t cause)\n+{\n+ uint32_t old, new;\n+\n+ old = env->t_sreg[HEX_SREG_SSR];\n+ SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, ex);\n+ SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause);\n+ new = env->t_sreg[HEX_SREG_SSR];\n+ hexagon_modify_ssr(env, new, old);\n+}\n+\n+static bool get_iad_bit(CPUHexagonState *env, int int_num)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ uint32_t iad = GET_FIELD(IPENDAD_IAD, ipendad);\n+ return extract32(iad, int_num, 1);\n+}\n+\n+static void set_iad_bit(CPUHexagonState *env, int int_num, int val)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ uint32_t iad = GET_FIELD(IPENDAD_IAD, ipendad);\n+ iad = deposit32(iad, int_num, 1, val);\n+ fSET_FIELD(ipendad, IPENDAD_IAD, iad);\n+ if (cpu->globalregs) {\n+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,\n+ ipendad, env->threadId);\n+ }\n+}\n+\n+static uint32_t get_ipend(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ return GET_FIELD(IPENDAD_IPEND, ipendad);\n+}\n+\n+static inline bool get_ipend_bit(CPUHexagonState *env, int int_num)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);\n+ return extract32(ipend, int_num, 1);\n+}\n+\n+static void clear_ipend(CPUHexagonState *env, uint32_t mask)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);\n+ ipend &= ~mask;\n+ fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);\n+ if (cpu->globalregs) {\n+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,\n+ ipendad, env->threadId);\n+ }\n+}\n+\n+static void set_ipend(CPUHexagonState *env, uint32_t mask)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);\n+ ipend |= mask;\n+ fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);\n+ if (cpu->globalregs) {\n+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,\n+ ipendad, env->threadId);\n+ }\n+}\n+\n+static void set_ipend_bit(CPUHexagonState *env, int int_num, int val)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ipendad = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_IPENDAD,\n+ env->threadId) : 0;\n+ uint32_t ipend = GET_FIELD(IPENDAD_IPEND, ipendad);\n+ ipend = deposit32(ipend, int_num, 1, val);\n+ fSET_FIELD(ipendad, IPENDAD_IPEND, ipend);\n+ if (cpu->globalregs) {\n+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_IPENDAD,\n+ ipendad, env->threadId);\n+ }\n+}\n+\n+static bool get_imask_bit(CPUHexagonState *env, int int_num)\n+{\n+ uint32_t imask = env->t_sreg[HEX_SREG_IMASK];\n+ return extract32(imask, int_num, 1);\n+}\n+\n+static uint32_t get_prio(CPUHexagonState *env)\n+{\n+ uint32_t stid = env->t_sreg[HEX_SREG_STID];\n+ return extract32(stid, reg_field_info[STID_PRIO].offset,\n+ reg_field_info[STID_PRIO].width);\n+}\n+\n+static void set_elr(CPUHexagonState *env, uint32_t val)\n+{\n+ env->t_sreg[HEX_SREG_ELR] = val;\n+}\n+\n+static bool get_schedcfgen(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t schedcfg = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SCHEDCFG,\n+ env->threadId) : 0;\n+ return extract32(schedcfg, reg_field_info[SCHEDCFG_EN].offset,\n+ reg_field_info[SCHEDCFG_EN].width);\n+}\n+\n+static bool is_lowest_prio(CPUHexagonState *env, int int_num)\n+{\n+ uint32_t my_prio = get_prio(env);\n+ CPUState *cs;\n+\n+ CPU_FOREACH(cs) {\n+ CPUHexagonState *hex_env = cpu_env(cs);\n+ if (!hex_is_qualified_for_int(hex_env, int_num)) {\n+ continue;\n+ }\n+\n+ /* Note that lower values indicate *higher* priority */\n+ if (my_prio < get_prio(hex_env)) {\n+ return false;\n+ }\n+ }\n+ return true;\n+}\n+\n+static bool hex_is_qualified_for_int(CPUHexagonState *env, int int_num)\n+{\n+ bool syscfg_gie = get_syscfg_gie(env);\n+ bool iad = get_iad_bit(env, int_num);\n+ bool ssr_ie = get_ssr_ie(env);\n+ bool ssr_ex = get_ssr_ex(env);\n+ bool imask = get_imask_bit(env, int_num);\n+\n+ return syscfg_gie && !iad && ssr_ie && !ssr_ex && !imask;\n+}\n+\n+static void clear_pending_locks(CPUHexagonState *env)\n+{\n+ g_assert(bql_locked());\n+ if (env->k0_lock_state == HEX_LOCK_WAITING) {\n+ env->k0_lock_state = HEX_LOCK_UNLOCKED;\n+ }\n+ if (env->tlb_lock_state == HEX_LOCK_WAITING) {\n+ env->tlb_lock_state = HEX_LOCK_UNLOCKED;\n+ }\n+}\n+\n+static bool should_not_exec(CPUHexagonState *env)\n+{\n+ return (get_exe_mode(env) == HEX_EXE_MODE_WAIT);\n+}\n+\n+static void restore_state(CPUHexagonState *env, bool int_accepted)\n+{\n+ CPUState *cs = env_cpu(env);\n+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI);\n+ if (!int_accepted && should_not_exec(env)) {\n+ cpu_interrupt(cs, CPU_INTERRUPT_HALT);\n+ }\n+}\n+\n+static void hex_accept_int(CPUHexagonState *env, int int_num)\n+{\n+ CPUState *cs = env_cpu(env);\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t evb = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_EVB,\n+ env->threadId) : 0;\n+ const int exe_mode = get_exe_mode(env);\n+ const bool in_wait_mode = exe_mode == HEX_EXE_MODE_WAIT;\n+\n+ set_ipend_bit(env, int_num, 0);\n+ set_iad_bit(env, int_num, 1);\n+ set_ssr_ex_cause(env, 1, HEX_CAUSE_INT0 | int_num);\n+ cs->exception_index = HEX_EVENT_INT0 + int_num;\n+ env->cause_code = HEX_EVENT_INT0 + int_num;\n+ clear_pending_locks(env);\n+ if (in_wait_mode) {\n+ qemu_log_mask(CPU_LOG_INT,\n+ \"%s: thread \" TARGET_FMT_ld \" resuming, exiting WAIT mode\\n\",\n+ __func__, env->threadId);\n+ set_elr(env, env->wait_next_pc);\n+ clear_wait_mode(env);\n+ cs->halted = false;\n+ } else if (env->k0_lock_state == HEX_LOCK_WAITING) {\n+ g_assert_not_reached();\n+ } else {\n+ set_elr(env, env->gpr[HEX_REG_PC]);\n+ }\n+ env->gpr[HEX_REG_PC] = evb | (cs->exception_index << 2);\n+ if (get_ipend(env) == 0) {\n+ restore_state(env, true);\n+ }\n+}\n+\n+\n+bool hex_check_interrupts(CPUHexagonState *env)\n+{\n+ CPUState *cs = env_cpu(env);\n+ bool int_handled = false;\n+ bool ssr_ex = get_ssr_ex(env);\n+ int max_ints = 32;\n+ bool schedcfgen;\n+\n+ /* Early exit if nothing pending */\n+ if (get_ipend(env) == 0) {\n+ restore_state(env, false);\n+ return false;\n+ }\n+\n+ BQL_LOCK_GUARD();\n+ /* Only check priorities when schedcfgen is set */\n+ schedcfgen = get_schedcfgen(env);\n+ for (int i = 0; i < max_ints; i++) {\n+ if (!get_iad_bit(env, i) && get_ipend_bit(env, i)) {\n+ bool syscfg_gie, iad, ssr_ie, imask;\n+\n+ qemu_log_mask(CPU_LOG_INT,\n+ \"%s: thread[\" TARGET_FMT_ld \"] \"\n+ \"pc = 0x\" TARGET_FMT_lx\n+ \" found int %d\\n\",\n+ __func__, env->threadId,\n+ env->gpr[HEX_REG_PC], i);\n+ if (hex_is_qualified_for_int(env, i) &&\n+ (!schedcfgen || is_lowest_prio(env, i))) {\n+ qemu_log_mask(CPU_LOG_INT,\n+ \"%s: thread[\" TARGET_FMT_ld \"] int %d handled_\\n\",\n+ __func__, env->threadId, i);\n+ hex_accept_int(env, i);\n+ int_handled = true;\n+ break;\n+ }\n+ syscfg_gie = get_syscfg_gie(env);\n+ iad = get_iad_bit(env, i);\n+ ssr_ie = get_ssr_ie(env);\n+ imask = get_imask_bit(env, i);\n+\n+ qemu_log_mask(CPU_LOG_INT,\n+ \"%s: thread[\" TARGET_FMT_ld \"] \"\n+ \"int %d not handled, qualified: %d, \"\n+ \"schedcfg_en: %d, low prio %d\\n\",\n+ __func__, env->threadId, i,\n+ hex_is_qualified_for_int(env, i), schedcfgen,\n+ is_lowest_prio(env, i));\n+\n+ qemu_log_mask(CPU_LOG_INT,\n+ \"%s: thread[\" TARGET_FMT_ld \"] \"\n+ \"int %d not handled, GIE %d, iad %d, \"\n+ \"SSR:IE %d, SSR:EX: %d, imask bit %d\\n\",\n+ __func__, env->threadId, i, syscfg_gie, iad, ssr_ie,\n+ ssr_ex, imask);\n+ }\n+ }\n+\n+ /*\n+ * If we didn't handle the interrupt and it wasn't\n+ * because we were in EX state, then we won't be able\n+ * to execute the interrupt on this CPU unless something\n+ * changes in the CPU state. Clear the interrupt_request bits\n+ * while preserving the IPEND bits, and we can re-assert the\n+ * interrupt_request bit(s) when we execute one of those instructions.\n+ */\n+ if (!int_handled && !ssr_ex) {\n+ restore_state(env, int_handled);\n+ } else if (int_handled) {\n+ assert(!cs->halted);\n+ }\n+\n+ return int_handled;\n+}\n+\n+void hex_clear_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type)\n+{\n+ if (mask == 0) {\n+ return;\n+ }\n+\n+ /*\n+ * Notify all CPUs that the interrupt has happened\n+ */\n+ BQL_LOCK_GUARD();\n+ clear_ipend(env, mask);\n+ hex_interrupt_update(env);\n+}\n+\n+void hex_raise_interrupts(CPUHexagonState *env, uint32_t mask, uint32_t type)\n+{\n+ g_assert(bql_locked());\n+ if (mask == 0) {\n+ return;\n+ }\n+\n+ /*\n+ * Notify all CPUs that the interrupt has happened\n+ */\n+ set_ipend(env, mask);\n+ hex_interrupt_update(env);\n+}\n+\n+void hex_interrupt_update(CPUHexagonState *env)\n+{\n+ CPUState *cs;\n+\n+ g_assert(bql_locked());\n+ if (get_ipend(env) != 0) {\n+ CPU_FOREACH(cs) {\n+ CPUHexagonState *hex_env = cpu_env(cs);\n+ const int exe_mode = get_exe_mode(hex_env);\n+ if (exe_mode != HEX_EXE_MODE_OFF) {\n+ cpu_interrupt(cs, CPU_INTERRUPT_SWI);\n+ cpu_resume(cs);\n+ }\n+ }\n+ }\n+}\n", "prefixes": [ "v6", "37/37" ] }