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GET /api/patches/2218649/?format=api
{ "id": 2218649, "url": "http://patchwork.ozlabs.org/api/patches/2218649/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-30-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-30-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:49", "name": "[v6,29/37] target/hexagon: Add sreg_{read,write} helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0e9cafd2cf7fd6067635320ec3db278f33fe7e24", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-30-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218649/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218649/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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<sidneym@quicinc.com>", "Subject": "[PATCH v6 29/37] target/hexagon: Add sreg_{read,write} helpers", "Date": "Wed, 1 Apr 2026 08:26:49 -0700", "Message-Id": "<20260401152657.314902-30-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "References": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Authority-Analysis": "v=2.4 cv=B+O0EetM c=1 sm=1 tr=0 ts=69cd3994 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22\n a=COk6AnOGAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=rqZXtLhFGwB6yMrbUaoA:9\n a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-ORIG-GUID": "UyHophEKb0n9Vpqo59x2VmoHSeuPAIfN", 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suspectscore=0 phishscore=0\n bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nCo-authored-by: Sid Manning <sidneym@quicinc.com>\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.c | 1 -\n target/hexagon/cpu_helper.c | 354 ++++++++++++++++++++++++++++++++++++\n target/hexagon/op_helper.c | 33 +++-\n 3 files changed, 384 insertions(+), 4 deletions(-)\n create mode 100644 target/hexagon/cpu_helper.c", "diff": "diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex c79b19d059e..79ee4264c70 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -339,7 +339,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)\n \n qemu_init_vcpu(cs);\n cpu_reset(cs);\n-\n mcc->parent_realize(dev, errp);\n }\n \ndiff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c\nnew file mode 100644\nindex 00000000000..a2b486f4bb5\n--- /dev/null\n+++ b/target/hexagon/cpu_helper.c\n@@ -0,0 +1,354 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"cpu_helper.h\"\n+#include \"system/cpus.h\"\n+#include \"hw/core/boards.h\"\n+#include \"hw/hexagon/hexagon.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n+#include \"hex_interrupts.h\"\n+#include \"hex_mmu.h\"\n+#include \"system/runstate.h\"\n+#include \"exec/cpu-interrupt.h\"\n+#include \"exec/target_page.h\"\n+#include \"accel/tcg/cpu-ldst.h\"\n+#include \"exec/cputlb.h\"\n+#include \"qemu/log.h\"\n+#include \"tcg/tcg-op.h\"\n+#include \"internal.h\"\n+#include \"macros.h\"\n+#include \"sys_macros.h\"\n+#include \"arch.h\"\n+\n+\n+uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index)\n+{\n+ g_assert_not_reached();\n+}\n+\n+uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env)\n+{\n+ g_assert_not_reached();\n+}\n+\n+uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env)\n+{\n+ g_assert_not_reached();\n+}\n+\n+uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t val)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t val)\n+{\n+ g_assert_not_reached();\n+}\n+\n+static void hexagon_resume_thread(CPUHexagonState *env)\n+{\n+ CPUState *cs = env_cpu(env);\n+ clear_wait_mode(env);\n+ /*\n+ * The wait instruction keeps the PC pointing to itself\n+ * so that it has an opportunity to check for interrupts.\n+ *\n+ * When we come out of wait mode, adjust the PC to the\n+ * next executable instruction.\n+ */\n+ env->gpr[HEX_REG_PC] = env->wait_next_pc;\n+ cs = env_cpu(env);\n+ ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index);\n+ cs->halted = false;\n+ cs->exception_index = HEX_EVENT_NONE;\n+ qemu_cpu_kick(cs);\n+}\n+\n+void hexagon_resume_threads(CPUHexagonState *current_env, uint32_t mask)\n+{\n+ CPUState *cs;\n+ CPUHexagonState *env;\n+\n+ g_assert(bql_locked());\n+ CPU_FOREACH(cs) {\n+ env = cpu_env(cs);\n+ g_assert(env->threadId < THREADS_MAX);\n+ if ((mask & (0x1 << env->threadId))) {\n+ if (get_exe_mode(env) == HEX_EXE_MODE_WAIT) {\n+ hexagon_resume_thread(env);\n+ }\n+ }\n+ }\n+}\n+\n+void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old)\n+{\n+ bool old_EX, old_UM, old_GM, old_IE;\n+ bool new_EX, new_UM, new_GM, new_IE;\n+ uint8_t old_asid, new_asid;\n+\n+ g_assert(bql_locked());\n+\n+ old_EX = GET_SSR_FIELD(SSR_EX, old);\n+ old_UM = GET_SSR_FIELD(SSR_UM, old);\n+ old_GM = GET_SSR_FIELD(SSR_GM, old);\n+ old_IE = GET_SSR_FIELD(SSR_IE, old);\n+ new_EX = GET_SSR_FIELD(SSR_EX, new);\n+ new_UM = GET_SSR_FIELD(SSR_UM, new);\n+ new_GM = GET_SSR_FIELD(SSR_GM, new);\n+ new_IE = GET_SSR_FIELD(SSR_IE, new);\n+\n+ if ((old_EX != new_EX) ||\n+ (old_UM != new_UM) ||\n+ (old_GM != new_GM)) {\n+ hex_mmu_mode_change(env);\n+ }\n+\n+ old_asid = GET_SSR_FIELD(SSR_ASID, old);\n+ new_asid = GET_SSR_FIELD(SSR_ASID, new);\n+ if (new_asid != old_asid) {\n+ CPUState *cs = env_cpu(env);\n+ tlb_flush(cs);\n+ }\n+\n+ /* See if the interrupts have been enabled or we have exited EX mode */\n+ if ((new_IE && !old_IE) ||\n+ (!new_EX && old_EX)) {\n+ hex_interrupt_update(env);\n+ }\n+}\n+\n+void clear_wait_mode(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu;\n+ uint32_t modectl, thread_wait_mask;\n+\n+ g_assert(bql_locked());\n+\n+ cpu = env_archcpu(env);\n+ if (cpu->globalregs) {\n+ modectl =\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL,\n+ env->threadId);\n+ thread_wait_mask = GET_FIELD(MODECTL_W, modectl);\n+ thread_wait_mask &= ~(0x1 << env->threadId);\n+ SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_W, thread_wait_mask);\n+ }\n+}\n+\n+void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause)\n+{\n+ uint32_t old, new;\n+\n+ g_assert(bql_locked());\n+\n+ old = env->t_sreg[HEX_SREG_SSR];\n+ SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_EX, 1);\n+ SET_SYSTEM_FIELD(env, HEX_SREG_SSR, SSR_CAUSE, cause);\n+ new = env->t_sreg[HEX_SREG_SSR];\n+\n+ hexagon_modify_ssr(env, new, old);\n+}\n+\n+\n+int get_exe_mode(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu;\n+ uint32_t modectl, thread_enabled_mask, thread_wait_mask;\n+ uint32_t isdbst, debugmode;\n+ bool E_bit, W_bit, D_bit;\n+\n+ g_assert(bql_locked());\n+\n+ cpu = env_archcpu(env);\n+ modectl = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL,\n+ env->threadId) : 0;\n+ thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);\n+ E_bit = thread_enabled_mask & (0x1 << env->threadId);\n+ thread_wait_mask = GET_FIELD(MODECTL_W, modectl);\n+ W_bit = thread_wait_mask & (0x1 << env->threadId);\n+ isdbst = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_ISDBST,\n+ env->threadId) : 0;\n+ debugmode = GET_FIELD(ISDBST_DEBUGMODE, isdbst);\n+ D_bit = debugmode & (0x1 << env->threadId);\n+\n+ if (!D_bit && !W_bit && !E_bit) {\n+ return HEX_EXE_MODE_OFF;\n+ }\n+ if (!D_bit && !W_bit && E_bit) {\n+ return HEX_EXE_MODE_RUN;\n+ }\n+ if (!D_bit && W_bit && E_bit) {\n+ return HEX_EXE_MODE_WAIT;\n+ }\n+ if (D_bit && !W_bit && E_bit) {\n+ return HEX_EXE_MODE_DEBUG;\n+ }\n+ g_assert_not_reached();\n+}\n+\n+static uint32_t set_enable_mask(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu;\n+ uint32_t modectl, thread_enabled_mask;\n+\n+ g_assert(bql_locked());\n+\n+ cpu = env_archcpu(env);\n+ if (!cpu->globalregs) {\n+ return 0;\n+ }\n+ modectl =\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL,\n+ env->threadId);\n+ thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);\n+ thread_enabled_mask |= 0x1 << env->threadId;\n+ SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_E, thread_enabled_mask);\n+ return thread_enabled_mask;\n+}\n+\n+static uint32_t clear_enable_mask(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu;\n+ uint32_t modectl, thread_enabled_mask;\n+\n+ g_assert(bql_locked());\n+\n+ cpu = env_archcpu(env);\n+ if (!cpu->globalregs) {\n+ return 0;\n+ }\n+ modectl =\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL,\n+ env->threadId);\n+ thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);\n+ thread_enabled_mask &= ~(0x1 << env->threadId);\n+ SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_E, thread_enabled_mask);\n+ return thread_enabled_mask;\n+}\n+static void do_start_thread(CPUState *cs, run_on_cpu_data tbd)\n+{\n+ CPUHexagonState *env;\n+\n+ BQL_LOCK_GUARD();\n+\n+ env = cpu_env(cs);\n+\n+ hexagon_cpu_soft_reset(env);\n+\n+ set_enable_mask(env);\n+\n+ cs->halted = 0;\n+ cs->exception_index = HEX_EVENT_NONE;\n+ cpu_resume(cs);\n+}\n+\n+void hexagon_start_threads(CPUHexagonState *current_env, uint32_t mask)\n+{\n+ CPUState *cs;\n+ CPU_FOREACH(cs) {\n+ CPUHexagonState *env = cpu_env(cs);\n+ if (!(mask & (0x1 << env->threadId))) {\n+ continue;\n+ }\n+\n+ if (current_env->threadId != env->threadId) {\n+ async_safe_run_on_cpu(cs, do_start_thread, RUN_ON_CPU_NULL);\n+ }\n+ }\n+}\n+\n+/*\n+ * When we have all threads stopped, the return\n+ * value to the shell is register 2 from thread 0.\n+ */\n+static uint32_t get_thread0_r2(void)\n+{\n+ CPUState *cs;\n+ CPU_FOREACH(cs) {\n+ CPUHexagonState *thread = cpu_env(cs);\n+ if (thread->threadId == 0) {\n+ return thread->gpr[2];\n+ }\n+ }\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_stop_thread(CPUHexagonState *env)\n+{\n+ uint32_t thread_enabled_mask;\n+ CPUState *cs;\n+\n+ BQL_LOCK_GUARD();\n+\n+ thread_enabled_mask = clear_enable_mask(env);\n+ cs = env_cpu(env);\n+ cpu_interrupt(cs, CPU_INTERRUPT_HALT);\n+ if (!thread_enabled_mask) {\n+ /* All threads are stopped, request shutdown */\n+ qemu_system_shutdown_request_with_code(\n+ SHUTDOWN_CAUSE_GUEST_SHUTDOWN, get_thread0_r2());\n+ }\n+}\n+\n+static int sys_in_monitor_mode_ssr(uint32_t ssr)\n+{\n+ if ((GET_SSR_FIELD(SSR_EX, ssr) != 0) ||\n+ ((GET_SSR_FIELD(SSR_EX, ssr) == 0) &&\n+ (GET_SSR_FIELD(SSR_UM, ssr) == 0))) {\n+ return 1;\n+ }\n+ return 0;\n+}\n+\n+static int sys_in_guest_mode_ssr(uint32_t ssr)\n+{\n+ if ((GET_SSR_FIELD(SSR_EX, ssr) == 0) &&\n+ (GET_SSR_FIELD(SSR_UM, ssr) != 0) &&\n+ (GET_SSR_FIELD(SSR_GM, ssr) != 0)) {\n+ return 1;\n+ }\n+ return 0;\n+}\n+\n+static int sys_in_user_mode_ssr(uint32_t ssr)\n+{\n+ if ((GET_SSR_FIELD(SSR_EX, ssr) == 0) &&\n+ (GET_SSR_FIELD(SSR_UM, ssr) != 0) &&\n+ (GET_SSR_FIELD(SSR_GM, ssr) == 0)) {\n+ return 1;\n+ }\n+ return 0;\n+}\n+\n+int get_cpu_mode(CPUHexagonState *env)\n+{\n+ uint32_t ssr = env->t_sreg[HEX_SREG_SSR];\n+\n+ if (sys_in_monitor_mode_ssr(ssr)) {\n+ return HEX_CPU_MODE_MONITOR;\n+ } else if (sys_in_guest_mode_ssr(ssr)) {\n+ return HEX_CPU_MODE_GUEST;\n+ } else if (sys_in_user_mode_ssr(ssr)) {\n+ return HEX_CPU_MODE_USER;\n+ }\n+ return HEX_CPU_MODE_MONITOR;\n+}\ndiff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c\nindex 87da1fe430c..947988d2456 100644\n--- a/target/hexagon/op_helper.c\n+++ b/target/hexagon/op_helper.c\n@@ -19,6 +19,7 @@\n #include \"qemu/log.h\"\n #include \"accel/tcg/cpu-ldst.h\"\n #include \"accel/tcg/probe.h\"\n+#include \"qemu/main-loop.h\"\n #include \"cpu.h\"\n #include \"exec/helper-proto.h\"\n #include \"fpu/softfloat.h\"\n@@ -1451,17 +1452,43 @@ void HELPER(setimask)(CPUHexagonState *env, uint32_t tid, uint32_t imask)\n \n void HELPER(sreg_write_masked)(CPUHexagonState *env, uint32_t reg, uint32_t val)\n {\n- g_assert_not_reached();\n+ BQL_LOCK_GUARD();\n+ if (reg < HEX_SREG_GLB_START) {\n+ env->t_sreg[reg] = val;\n+ } else {\n+ HexagonCPU *cpu = env_archcpu(env);\n+ if (cpu->globalregs) {\n+ hexagon_globalreg_write_masked(cpu->globalregs, reg, val);\n+ }\n+ }\n+}\n+\n+static inline QEMU_ALWAYS_INLINE uint32_t sreg_read(CPUHexagonState *env,\n+ uint32_t reg)\n+{\n+ HexagonCPU *cpu;\n+\n+ g_assert(bql_locked());\n+ if (reg < HEX_SREG_GLB_START) {\n+ return env->t_sreg[reg];\n+ }\n+ cpu = env_archcpu(env);\n+ return cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, reg, env->threadId) : 0;\n }\n \n uint32_t HELPER(sreg_read)(CPUHexagonState *env, uint32_t reg)\n {\n- g_assert_not_reached();\n+ BQL_LOCK_GUARD();\n+ return sreg_read(env, reg);\n }\n \n uint64_t HELPER(sreg_read_pair)(CPUHexagonState *env, uint32_t reg)\n {\n- g_assert_not_reached();\n+ BQL_LOCK_GUARD();\n+\n+ return deposit64((uint64_t) sreg_read(env, reg), 32, 32,\n+ sreg_read(env, reg + 1));\n }\n \n uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg)\n", "prefixes": [ "v6", "29/37" ] }