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GET /api/patches/2218643/?format=api
{ "id": 2218643, "url": "http://patchwork.ozlabs.org/api/patches/2218643/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-34-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-34-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:53", "name": "[v6,33/37] target/hexagon: Add cpu modes, mmu indices, next_PC to state", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3e14fd047b39232ac148f7ab8e06ced753a639ed", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-34-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218643/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218643/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=XNlZnaXy;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ffUR9ZdQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 21 ++++++++++++++++++++-\n target/hexagon/cpu.c | 1 +\n 2 files changed, 21 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex d3b7b346841..d3361936d04 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -48,8 +48,26 @@\n #define VSTORES_MAX 2\n \n #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU\n+#ifndef CONFIG_USER_ONLY\n+#define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0\n+\n+#define HEX_CPU_MODE_USER 1\n+#define HEX_CPU_MODE_GUEST 2\n+#define HEX_CPU_MODE_MONITOR 3\n+\n+#define HEX_EXE_MODE_OFF 1\n+#define HEX_EXE_MODE_RUN 2\n+#define HEX_EXE_MODE_WAIT 3\n+#define HEX_EXE_MODE_DEBUG 4\n+#endif\n+\n+#define MMU_USER_IDX 0\n+#ifndef CONFIG_USER_ONLY\n+#define MMU_GUEST_IDX 1\n+#define MMU_KERNEL_IDX 2\n+\n+#endif\n \n-#define MMU_USER_IDX 0\n \n #define HEXAGON_CPU_IRQ_0 0\n #define HEXAGON_CPU_IRQ_1 1\n@@ -111,6 +129,7 @@ typedef struct CPUArchState {\n uint32_t threadId;\n uint64_t t_cycle_count;\n #endif\n+ uint32_t next_PC;\n target_ulong new_value_usr;\n \n MemLog mem_log_stores[STORES_MAX];\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 45ac9a3d24e..ab5bfb0ed0e 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -314,6 +314,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS);\n memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS);\n env->wait_next_pc = 0;\n+ env->next_PC = 0;\n #endif\n env->cause_code = HEX_EVENT_NONE;\n }\n", "prefixes": [ "v6", "33/37" ] }