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GET /api/patches/2218636/?format=api
{ "id": 2218636, "url": "http://patchwork.ozlabs.org/api/patches/2218636/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-24-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-24-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:43", "name": "[v6,23/37] target/hexagon: Add system reg insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d49abd499a77cd03b80f7083063037f37e15bbfd", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-24-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218636/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218636/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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"[PATCH v6 23/37] target/hexagon: Add system reg insns", "Date": "Wed, 1 Apr 2026 08:26:43 -0700", "Message-Id": "<20260401152657.314902-24-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "References": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfX2ocfZZRcANLy\n VRA3xnYuc0bZ5+YKtvjNJ0OBC10iqtdZrcDRAM8yMP61JFJz5fIuaalfoIVQddgfhSP+v8UxYTU\n p8QdKI7YvIxHJgKbS00GJYxlUnbspw0gWx04WncY7pMvU3a9k3U3JQw8coQ0oPKrQhzvpjCIeqQ\n A/IsyfrjfYqe+b3dDvtE6ICj5tnqlMAVjU65iAdyTn9hwPSWSw7Z5Bg/XOxGq+DeaNlzGR/OFxi\n H/6Lw0kMkqK8iNORu5j9WiagxKqAv9QQVT0LszYpubSDotLS01560j1RHwSkgZzuEwO7JY0ZJcV\n 9+m90JDZqJ0jo1FQ6Gaxful8QuRt8UbMKhvGn7Tp7nlGksiargX8RZUzOPjkZYumj18oSH00ky5\n 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suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nAcked-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/imported/encode_pp.def | 128 ++++++++++++--\n target/hexagon/imported/system.idef | 244 ++++++++++++++++++++++++--\n 2 files changed, 345 insertions(+), 27 deletions(-)", "diff": "diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/imported/encode_pp.def\nindex 0cd30a5e857..04e911f59c8 100644\n--- a/target/hexagon/imported/encode_pp.def\n+++ b/target/hexagon/imported/encode_pp.def\n@@ -382,15 +382,18 @@ DEF_ENC32(L4_return_fnew_pt, ICLASS_LD\" 011 0 000 sssss PP1110vv ---ddddd\")\n DEF_ENC32(L4_return_tnew_pnt, ICLASS_LD\" 011 0 000 sssss PP0010vv ---ddddd\")\n DEF_ENC32(L4_return_fnew_pnt, ICLASS_LD\" 011 0 000 sssss PP1010vv ---ddddd\")\n \n-DEF_ENC32(L2_loadw_locked,ICLASS_LD\" 001 0 000 sssss PP000--- 000ddddd\")\n-\n+/** Load Acquire Store Release Encoding **/\n \n+DEF_ENC32(L2_loadw_locked, ICLASS_LD\" 001 0 000 sssss PP000--- 000ddddd\")\n+DEF_ENC32(L4_loadd_locked, ICLASS_LD\" 001 0 000 sssss PP010--- 000ddddd\")\n \n DEF_ENC32(L2_loadw_aq, ICLASS_LD\" 001 0 000 sssss PP001--- 000ddddd\")\n DEF_ENC32(L4_loadd_aq, ICLASS_LD\" 001 0 000 sssss PP011--- 000ddddd\")\n \n-DEF_ENC32(R6_release_at_vi, ICLASS_ST\" 000 01 11sssss PP0ttttt --0011dd\")\n-DEF_ENC32(R6_release_st_vi, ICLASS_ST\" 000 01 11sssss PP0ttttt --1011dd\")\n+\n+DEF_ENC32(S2_storew_locked, ICLASS_ST\" 000 01 01sssss PP-ttttt ----00dd\")\n+DEF_ENC32(S4_stored_locked, ICLASS_ST\" 000 01 11sssss PP0ttttt ----00dd\")\n+\n \n DEF_ENC32(S2_storew_rl_at_vi, ICLASS_ST\" 000 01 01sssss PP-ttttt --0010dd\")\n DEF_ENC32(S2_storew_rl_st_vi, ICLASS_ST\" 000 01 01sssss PP-ttttt --1010dd\")\n@@ -398,17 +401,15 @@ DEF_ENC32(S2_storew_rl_st_vi, ICLASS_ST\" 000 01 01sssss PP-ttttt --1010dd\")\n DEF_ENC32(S4_stored_rl_at_vi, ICLASS_ST\" 000 01 11sssss PP0ttttt --0010dd\")\n DEF_ENC32(S4_stored_rl_st_vi, ICLASS_ST\" 000 01 11sssss PP0ttttt --1010dd\")\n \n-DEF_ENC32(L4_loadd_locked,ICLASS_LD\" 001 0 000 sssss PP010--- 000ddddd\")\n-DEF_EXT_SPACE(EXTRACTW, ICLASS_LD\" 001 0 000 iiiii PP0iiiii -01iiiii\")\n+DEF_ENC32(R6_release_at_vi, ICLASS_ST\" 000 01 11sssss PP0ttttt --0011dd\")\n+DEF_ENC32(R6_release_st_vi, ICLASS_ST\" 000 01 11sssss PP0ttttt --1011dd\")\n+\n+DEF_EXT_SPACE(EXTRACTW, ICLASS_LD\" 001 0 000 iiiii PP0iiiii 001iiiii\")\n DEF_ENC32(Y2_dcfetchbo, ICLASS_LD\" 010 0 000 sssss PP0--iii iiiiiiii\")\n \n \n \n \n-\n-\n-\n-\n /*******************************/\n /* */\n /* */\n@@ -488,13 +489,17 @@ STD_PST_ENC(rinew, \"1 101\",\"10ttt\")\n /* x bus/cache */\n /* x store/cache */\n DEF_ENC32(S2_allocframe, ICLASS_ST\" 000 01 00xxxxx PP000iii iiiiiiii\")\n-DEF_ENC32(S2_storew_locked,ICLASS_ST\" 000 01 01sssss PP-ttttt ----00dd\")\n-DEF_ENC32(S4_stored_locked,ICLASS_ST\" 000 01 11sssss PP0ttttt ----00dd\")\n+DEF_ENC32(Y5_l2locka, ICLASS_ST\" 000 01 11sssss PP1----- ------dd\")\n DEF_ENC32(Y2_dczeroa, ICLASS_ST\" 000 01 10sssss PP0----- --------\")\n \n \n DEF_ENC32(Y2_barrier, ICLASS_ST\" 100 00 00----- PP------ 000-----\")\n DEF_ENC32(Y2_syncht, ICLASS_ST\" 100 00 10----- PP------ --------\")\n+DEF_ENC32(Y2_l2kill, ICLASS_ST\" 100 00 01----- PP-000-- --------\")\n+DEF_ENC32(Y5_l2gunlock, ICLASS_ST\" 100 00 01----- PP-010-- --------\")\n+DEF_ENC32(Y5_l2gclean, ICLASS_ST\" 100 00 01----- PP-100-- --------\")\n+DEF_ENC32(Y5_l2gcleaninv, ICLASS_ST\" 100 00 01----- PP-110-- --------\")\n+DEF_ENC32(Y2_l2cleaninvidx,ICLASS_ST\" 100 00 11sssss PP------ --------\")\n \n \n \n@@ -502,9 +507,28 @@ DEF_ENC32(Y2_dccleana, ICLASS_ST\" 000 00 00sssss PP------ --------\")\n DEF_ENC32(Y2_dcinva, ICLASS_ST\" 000 00 01sssss PP------ --------\")\n DEF_ENC32(Y2_dccleaninva, ICLASS_ST\" 000 00 10sssss PP------ --------\")\n \n-DEF_ENC32(Y4_l2fetch, ICLASS_ST\" 011 00 00sssss PP-ttttt 000-----\")\n+/* Super */\n+DEF_ENC32(Y2_dckill, ICLASS_ST\" 001 00 00----- PP------ --------\")\n+DEF_ENC32(Y2_dccleanidx, ICLASS_ST\" 001 00 01sssss PP------ --------\")\n+DEF_ENC32(Y2_dcinvidx, ICLASS_ST\" 001 00 10sssss PP------ --------\")\n+DEF_ENC32(Y2_dccleaninvidx,ICLASS_ST\" 001 00 11sssss PP------ --------\")\n+\n+DEF_ENC32(Y2_dctagw ,ICLASS_ST\" 010 00 00sssss PP-ttttt --------\")\n+DEF_ENC32(Y2_dctagr ,ICLASS_ST\" 010 00 01sssss PP------ ---ddddd\")\n+\n+DEF_ENC32(Y4_l2tagw ,ICLASS_ST\" 010 00 10sssss PP0ttttt --------\")\n+DEF_ENC32(Y4_l2tagr ,ICLASS_ST\" 010 00 11sssss PP------ ---ddddd\")\n+\n+DEF_ENC32(Y4_l2fetch, ICLASS_ST\" 011 00 00sssss PP-ttttt 000-----\")\n+DEF_ENC32(Y5_l2cleanidx, ICLASS_ST\" 011 00 01sssss PP------ --------\")\n+DEF_ENC32(Y5_l2invidx, ICLASS_ST\" 011 00 10sssss PP------ --------\")\n+DEF_ENC32(Y5_l2unlocka, ICLASS_ST\" 011 00 11sssss PP------ --------\")\n DEF_ENC32(Y5_l2fetch, ICLASS_ST\" 011 01 00sssss PP-ttttt --------\")\n \n+DEF_ENC32(Y6_l2gcleanpa, ICLASS_ST\" 011 01 01----- PP-ttttt --------\")\n+DEF_ENC32(Y6_l2gcleaninvpa,ICLASS_ST\" 011 01 10----- PP-ttttt --------\")\n+\n+\n /*******************************/\n /* */\n /* */\n@@ -547,13 +571,23 @@ DEF_ENC32(J2_jumprfnewpt, ICLASS_J\" 0011 011sssss PP-11-uu --------\")\n \n DEF_FIELDROW_DESC32(ICLASS_J\" 0100 -------- PP------ --------\",\"[#4] (#u8) \")\n DEF_ENC32(J2_trap0, ICLASS_J\" 0100 00------ PP-iiiii ---iii--\")\n-DEF_ENC32(J2_pause, ICLASS_J\" 0100 01------ PP-iiiii ---iii--\")\n+DEF_ENC32(J2_trap1, ICLASS_J\" 0100 10-xxxxx PP-iiiii ---iii--\")\n+DEF_ENC32(J2_pause, ICLASS_J\" 0100 01----ii PP-iiiii ---iii--\")\n+\n+DEF_FIELDROW_DESC32(ICLASS_J\" 0101 -------- PP------ --------\",\"[#5] Rd=(Rs) \")\n+DEF_ENC32(Y2_icdatar, ICLASS_J\" 0101 101sssss PP------ ---ddddd\")\n+DEF_ENC32(Y2_ictagr, ICLASS_J\" 0101 111sssss PP------ ---ddddd\")\n+DEF_ENC32(Y2_ictagw, ICLASS_J\" 0101 110sssss PP0ttttt --------\")\n+DEF_ENC32(Y2_icdataw, ICLASS_J\" 0101 110sssss PP1ttttt --------\")\n \n DEF_FIELDROW_DESC32(ICLASS_J\" 0110 -------- PP------ --------\",\"[#6] icop(Rs) \")\n DEF_ENC32(Y2_icinva, ICLASS_J\" 0110 110sssss PP000--- --------\")\n+DEF_ENC32(Y2_icinvidx, ICLASS_J\" 0110 110sssss PP001--- --------\")\n+DEF_ENC32(Y2_ickill, ICLASS_J\" 0110 110----- PP010--- --------\")\n \n DEF_FIELDROW_DESC32(ICLASS_J\" 0111 -------- PP------ --------\",\"[#7] () \")\n DEF_ENC32(Y2_isync, ICLASS_J\" 0111 11000000 PP0---00 00000010\")\n+DEF_ENC32(J2_rte, ICLASS_J\" 0111 111----- PP00---- 000-----\")\n \n /* JUMP */\n DEF_FIELDROW_DESC32(ICLASS_J\" 100- -------- PP------ --------\",\"[#8,9] PC=(#r22)\")\n@@ -738,12 +772,19 @@ DEF_ENC32(J2_jumprltezpt,ICLASS_CR\" 0001 11isssss PPi1iiii iiiiiii-\")\n \n DEF_FIELDROW_DESC32( ICLASS_CR\" 0010 -------- PP------ --------\",\"[#2] Cd=Rs \")\n DEF_ENC32(A2_tfrrcr, ICLASS_CR\" 0010 001sssss PP------ ---ddddd\")\n+DEF_ENC32(G4_tfrgrcr, ICLASS_CR\" 0010 000sssss PP------ ---ddddd\")\n+DEF_ENC32(Y4_trace, ICLASS_CR\" 0010 010sssss PP------ 000-----\")\n+DEF_ENC32(Y6_diag, ICLASS_CR\" 0010 010sssss PP------ 001-----\")\n+DEF_ENC32(Y6_diag0, ICLASS_CR\" 0010 010sssss PP-ttttt 010-----\")\n+DEF_ENC32(Y6_diag1, ICLASS_CR\" 0010 010sssss PP-ttttt 011-----\")\n \n DEF_FIELDROW_DESC32( ICLASS_CR\" 0011 -------- PP------ --------\",\"[#3] Cdd=Rss \")\n DEF_ENC32(A4_tfrpcp, ICLASS_CR\" 0011 001sssss PP------ ---ddddd\")\n+DEF_ENC32(G4_tfrgpcp, ICLASS_CR\" 0011 000sssss PP------ ---ddddd\")\n \n DEF_FIELDROW_DESC32( ICLASS_CR\" 1000 -------- PP------ --------\",\"[#8] Rdd=Css \")\n DEF_ENC32(A4_tfrcpp, ICLASS_CR\" 1000 000sssss PP------ ---ddddd\")\n+DEF_ENC32(G4_tfrgcpp, ICLASS_CR\" 1000 001sssss PP------ ---ddddd\")\n \n DEF_FIELDROW_DESC32( ICLASS_CR\" 1001 -------- PP------ --------\",\"[#9] (#r8,#U10)\")\n DEF_ENC32(J2_ploop1si, ICLASS_CR\" 1001 101IIIII PP-iiiii IIIii-II\")\n@@ -754,6 +795,7 @@ DEF_ENC32(J2_loop1i, ICLASS_CR\" 1001 001IIIII PP-iiiii IIIii-II\")\n \n DEF_FIELDROW_DESC32( ICLASS_CR\" 1010 -------- PP------ --------\",\"[#10] Rd=Cs \")\n DEF_ENC32(A2_tfrcrr, ICLASS_CR\" 1010 000sssss PP------ ---ddddd\")\n+DEF_ENC32(G4_tfrgcrr, ICLASS_CR\" 1010 001sssss PP------ ---ddddd\")\n DEF_ENC32(C4_addipc, ICLASS_CR\" 1010 01001001 PP-iiiii i--ddddd\")\n \n \n@@ -781,6 +823,64 @@ DEF_ENC32(C4_fastcorner9_not, ICLASS_CR\"1011 0001--ss PP1---tt 1--1--dd\")\n \n \n \n+/* Supervisor CR ops */\n+/* Interrupts */\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 0100 -------- PP------ --------\",\"[#4] (Rs,Pt)\")\n+DEF_ENC32(Y2_swi, ICLASS_CR\" 0100 000sssss PP------ 000-----\")\n+DEF_ENC32(Y2_cswi, ICLASS_CR\" 0100 000sssss PP------ 001-----\")\n+DEF_ENC32(Y2_iassignw, ICLASS_CR\" 0100 000sssss PP------ 010-----\")\n+DEF_ENC32(Y2_ciad, ICLASS_CR\" 0100 000sssss PP------ 011-----\")\n+DEF_ENC32(Y2_setimask, ICLASS_CR\" 0100 100sssss PP----tt 000-----\")\n+DEF_ENC32(Y2_setprio, ICLASS_CR\" 0100 100sssss PP----tt 001-----\")\n+DEF_ENC32(Y4_siad, ICLASS_CR\" 0100 100sssss PP------ 011-----\")\n+\n+DEF_ENC32(Y2_wait, ICLASS_CR\" 0100 010sssss PP------ 000-----\")\n+DEF_ENC32(Y2_resume, ICLASS_CR\" 0100 010sssss PP------ 001-----\")\n+DEF_ENC32(Y2_stop, ICLASS_CR\" 0100 011sssss PP------ 000-----\")\n+DEF_ENC32(Y2_start, ICLASS_CR\" 0100 011sssss PP------ 001-----\")\n+DEF_ENC32(Y4_nmi, ICLASS_CR\" 0100 011sssss PP------ 010-----\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 0101 -------- PP------ --------\",\"[#5] Rx \")\n+DEF_ENC32(Y2_crswap0, ICLASS_CR\" 0101 000xxxxx PP------ --------\")\n+DEF_ENC32(Y4_crswap1, ICLASS_CR\" 0101 001xxxxx PP------ --------\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 0110 -------- PP------ --------\",\"[#6] Rd=(Rs)\")\n+DEF_ENC32(Y2_getimask, ICLASS_CR\" 0110 000sssss PP------ ---ddddd\")\n+DEF_ENC32(Y2_iassignr, ICLASS_CR\" 0110 011sssss PP------ ---ddddd\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 0111 -------- PP------ --------\",\"[#7] cr=Rs \")\n+DEF_ENC32(Y2_tfrsrcr, ICLASS_CR\" 0111 00-sssss PP------ -ddddddd\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 1100 -------- PP------ --------\",\"[#12] \")\n+DEF_ENC32(Y2_break, ICLASS_CR\" 1100 001----- PP------ 000-----\")\n+DEF_ENC32(Y2_tlblock, ICLASS_CR\" 1100 001----- PP------ 001-----\")\n+DEF_ENC32(Y2_tlbunlock,ICLASS_CR\" 1100 001----- PP------ 010-----\")\n+DEF_ENC32(Y2_k0lock, ICLASS_CR\" 1100 001----- PP------ 011-----\")\n+DEF_ENC32(Y2_k0unlock, ICLASS_CR\" 1100 001----- PP------ 100-----\")\n+DEF_ENC32(Y2_tlbp, ICLASS_CR\" 1100 100sssss PP------ ---ddddd\")\n+DEF_ENC32(Y5_tlboc, ICLASS_CR\" 1100 111sssss PP------ ---ddddd\")\n+DEF_ENC32(Y5_tlbasidi, ICLASS_CR\" 1100 101sssss PP------ --------\")\n+DEF_ENC32(Y2_tlbr, ICLASS_CR\" 1100 010sssss PP------ ---ddddd\")\n+DEF_ENC32(Y2_tlbw, ICLASS_CR\" 1100 000sssss PP0ttttt --------\")\n+DEF_ENC32(Y5_ctlbw, ICLASS_CR\" 1100 110sssss PP0ttttt ---ddddd\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 1101 -------- PP------ --------\",\"[#13] Rxx \")\n+DEF_ENC32(Y4_crswap10, ICLASS_CR\" 1101 10-xxxxx PP------ ---00000\")\n+DEF_ENC32(Y4_tfrspcp, ICLASS_CR\" 1101 00-sssss PP------ -ddddddd\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 1110 -------- PP------ --------\",\"[#14] Rd=cr \")\n+DEF_ENC32(Y2_tfrscrr, ICLASS_CR\" 1110 1sssssss PP------ ---ddddd\")\n+\n+DEF_FIELDROW_DESC32( ICLASS_CR\" 1111 -------- PP------ --------\",\"[#15] Rdd=Sss \")\n+DEF_ENC32(Y4_tfrscpp, ICLASS_CR\" 1111 0sssssss PP------ ---ddddd\")\n+\n+\n+\n+\n+\n+\n+\n+\n /*******************************/\n /* */\n /* */\ndiff --git a/target/hexagon/imported/system.idef b/target/hexagon/imported/system.idef\nindex 7c6568e75e4..df4527a5fa9 100644\n--- a/target/hexagon/imported/system.idef\n+++ b/target/hexagon/imported/system.idef\n@@ -25,31 +25,230 @@\n /* User->OS interface */\n /********************************************/\n \n-Q6INSN(J2_trap0,\"trap0(#u8)\",ATTRIBS(A_COF),\n+Q6INSN(J2_trap0,\"trap0(#u8)\",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\n \"Trap to Operating System\",\n fTRAP(0,uiV);\n )\n \n-Q6INSN(J2_pause,\"pause(#u8)\",ATTRIBS(A_COF),\n+Q6INSN(J2_trap1,\"trap1(Rx32,#u8)\",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\n+\"Trap to Operating System\",\n+\t/*\n+\t * Note: if RxV is not written, we get the same as the input.\n+\t * Since trap1 is SOLO, this means the register will effectively not be updated\n+\t */\n+\tif (!fTRAP1_VIRTINSN(uiV)) {\n+\t\tfTRAP(1,uiV);\n+\t} else if (uiV == 1) {\n+\t\tfVIRTINSN_RTE(uiV,RxV);\n+\t} else if (uiV == 3) {\n+\t\tfVIRTINSN_SETIE(uiV,RxV);\n+\t} else if (uiV == 4) {\n+\t\tfVIRTINSN_GETIE(uiV,RxV);\n+\t} else if (uiV == 6) {\n+\t\tfVIRTINSN_SPSWAP(uiV,RxV);\n+\t})\n+\n+Q6INSN(J2_pause,\"pause(#u8)\",ATTRIBS(A_COF,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\n \"Enter low-power state for #u8 cycles\",{fPAUSE(uiV);})\n \n-Q6INSN(Y2_icinva,\"icinva(Rs32)\",ATTRIBS(A_ICOP,A_ICFLUSHOP),\"Instruction Cache Invalidate Address\",{fEA_REG(RsV); fICINVA(EA);})\n+Q6INSN(J2_rte, \"rte\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NO_TIMING_LOG),\n+\"Return from Exception\",\n+{\n+fHIDE(if((thread->timing_on) && (thread->status & EXEC_STATUS_REPLAY)) { return; })\n+fHIDE(CALLBACK(thread->processor_ptr->options->rte_callback,\n+ thread->system_ptr,thread->processor_ptr,\n+ thread->threadId,0);)\n+fCLEAR_RTE_EX();\n+fBRANCH(fREAD_ELR(),COF_TYPE_RTE);})\n \n-Q6INSN(Y2_isync,\"isync\",ATTRIBS(),\"Memory Synchronization\",{fISYNC();})\n-Q6INSN(Y2_barrier,\"barrier\",ATTRIBS(A_RESTRICT_SLOT0ONLY),\"Memory Barrier\",{fBARRIER();})\n-Q6INSN(Y2_syncht,\"syncht\",ATTRIBS(A_RESTRICT_SLOT0ONLY),\"Memory Synchronization\",{fSYNCH();})\n \n+/********************************************/\n+/* Interrupt Management */\n+/********************************************/\n \n-Q6INSN(Y2_dcfetchbo,\"dcfetch(Rs32+#u11:3)\",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH),\"Data Cache Prefetch\",{fEA_RI(RsV,uiV); fDCFETCH(EA);})\n+Q6INSN(Y2_swi,\"swi(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Software Interrupt\",{DO_SWI(RsV);})\n+Q6INSN(Y2_cswi,\"cswi(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Cancel Software Interrupt\",{DO_CSWI(RsV);})\n+Q6INSN(Y2_ciad,\"ciad(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Re-enable interrupt in IAD\",{DO_CIAD(RsV);})\n+Q6INSN(Y4_siad,\"siad(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Disable interrupt in IAD\",{DO_SIAD(RsV);})\n+Q6INSN(Y2_iassignr,\"Rd32=iassignr(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Read interrupt to thread assignments\",{DO_IASSIGNR(RsV,RdV);})\n+Q6INSN(Y2_iassignw,\"iassignw(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Write interrupt to thread assignments\",{DO_IASSIGNW(RsV);})\n \n \n-Q6INSN(Y2_dczeroa,\"dczeroa(Rs32)\",ATTRIBS(A_STORE,A_RESTRICT_SLOT0ONLY,A_DCZEROA),\"Zero an aligned 32-byte cacheline\",{fEA_REG(RsV); fDCZEROA(EA);})\n-Q6INSN(Y2_dccleana,\"dccleana(Rs32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),\"Data Cache Clean Address\",{fEA_REG(RsV); fDCCLEANA(EA);})\n-Q6INSN(Y2_dccleaninva,\"dccleaninva(Rs32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),\"Data Cache Clean and Invalidate Address\",{fEA_REG(RsV); fDCCLEANINVA(EA);})\n-Q6INSN(Y2_dcinva,\"dcinva(Rs32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_DCFLUSHOP),\"Data Cache Invalidate Address\",{fEA_REG(RsV); fDCCLEANINVA(EA);})\n+Q6INSN(Y2_getimask,\"Rd32=getimask(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Read imask register of another thread\",\n+{RdV = READ_IMASK(RsV & thread->processor_ptr->thread_system_mask); })\n \n+Q6INSN(Y2_setimask,\"setimask(Pt4,Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Change imask register of another thread\",\n+{fPREDUSE_TIMING();WRITE_IMASK(PtV & thread->processor_ptr->thread_system_mask,RsV); })\n \n-Q6INSN(Y4_l2fetch,\"l2fetch(Rs32,Rt32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY),\"L2 Cache Prefetch\",\n+\n+\n+/********************************************/\n+/* TLB management */\n+/********************************************/\n+\n+Q6INSN(Y2_tlbw,\"tlbw(Rss32,Rt32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\n+\"Write TLB entry\", {fTLBW(RtV,RssV);})\n+\n+Q6INSN(Y5_ctlbw,\"Rd32=ctlbw(Rss32,Rt32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\n+\"Conditional Write TLB entry\",\n+{\n+ if (fTLB_ENTRY_OVERLAP( (1LL<<63) | RssV )) {\n+ RdV=fTLB_ENTRY_OVERLAP_IDX( (1LL<<63) | RssV);\n+ } else {\n+ fTLBW(RtV,RssV);\n+ RdV=0x80000000;\n+ }\n+})\n+\n+Q6INSN(Y5_tlboc,\"Rd32=tlboc(Rss32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\n+\"TLB overlap check\",\n+{\n+ if (fTLB_ENTRY_OVERLAP( (1LL<<63) | RssV )) {\n+ RdV=fTLB_ENTRY_OVERLAP_IDX( (1LL<<63) | RssV);\n+ } else {\n+ RdV=0x80000000;\n+ }\n+})\n+\n+Q6INSN(Y2_tlbr,\"Rdd32=tlbr(Rs32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), \"Read TLB entry\",\n+{RddV = fTLBR(RsV);})\n+\n+Q6INSN(Y2_tlbp,\"Rd32=tlbp(Rs32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), \"Probe TLB\", {RdV=fTLBP(RsV);})\n+\n+Q6INSN(Y5_tlbasidi,\"tlbinvasid(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), \"Invalidate ASID\",\n+{\n+\tfHIDE(int i;)\n+ fHIDE(unsigned int NUM_TLB_ENTRIES = NUM_TLB_REGS(thread->processor_ptr);)\n+\tfor (i = 0; i < NUM_TLB_ENTRIES; i++) {\n+\t\tif ((fGET_FIELD(fTLBR(i),PTE_G) == 0) &&\n+\t\t\t(fGET_FIELD(fTLBR(i),PTE_ASID) == fEXTRACTU_RANGE(RsV,26,20))) {\n+\t\t\tfTLBW(i,fTLBR(i) & ~(1ULL << 63));\n+\t\t}\n+\t}\n+})\n+\n+Q6INSN(Y2_tlblock,\"tlblock\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_NO_TIMING_LOG), \"Lock TLB\",\n+{fSET_TLB_LOCK();})\n+\n+Q6INSN(Y2_tlbunlock,\"tlbunlock\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), \"Unlock TLB\",\n+{fCLEAR_TLB_LOCK();})\n+\n+Q6INSN(Y2_k0lock,\"k0lock\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_NO_TIMING_LOG), \"Lock K0\",\n+{fSET_K0_LOCK();})\n+\n+Q6INSN(Y2_k0unlock,\"k0unlock\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET), \"Unlock K0\",\n+{fCLEAR_K0_LOCK();})\n+\n+/********************************************/\n+/* Supervisor Reg Management */\n+/********************************************/\n+\n+Q6INSN(Y2_crswap0,\"crswap(Rx32,sgp0)\",ATTRIBS(A_PRIV,A_NOTE_PRIV), \"Swap system general pointer 0 with GPR\",\n+{fHIDE(size4s_t tmp;) tmp = RxV; RxV = READ_SGP0(); WRITE_SGP0(tmp);})\n+Q6INSN(Y4_crswap1,\"crswap(Rx32,sgp1)\",ATTRIBS(A_PRIV,A_NOTE_PRIV), \"Swap system general pointer 1 with GPR\",\n+{fHIDE(size4s_t tmp;) tmp = RxV; RxV = READ_SGP1(); WRITE_SGP1(tmp);})\n+\n+Q6INSN(Y4_crswap10,\"crswap(Rxx32,sgp1:0)\",ATTRIBS(A_PRIV,A_NOTE_PRIV), \"Swap system general purpose 0/1 with GPR Pair\",\n+{fHIDE(size8s_t tmp;) tmp = RxxV; RxxV=READ_SGP10(); WRITE_SGP10(tmp);})\n+\n+Q6INSN(Y2_tfrscrr,\"Rd32=Ss128\",ATTRIBS(A_PRIV,A_NOTE_PRIV),\"Transfer Supervisor Reg to GPR\", {RdV=SsV;})\n+Q6INSN(Y2_tfrsrcr,\"Sd128=Rs32\",ATTRIBS(A_PRIV,A_NOTE_PRIV),\"Transfer GPR to Supervisor Reg\", {SdV=RsV;})\n+Q6INSN(Y4_tfrscpp,\"Rdd32=Sss128\",ATTRIBS(A_PRIV,A_NOTE_PRIV),\"Transfer Supervisor Reg to GPR\", {RddV=SssV;})\n+Q6INSN(Y4_tfrspcp,\"Sdd128=Rss32\",ATTRIBS(A_PRIV,A_NOTE_PRIV),\"Transfer GPR to Supervisor Reg\", {SddV=RssV;})\n+\n+Q6INSN(G4_tfrgcrr,\"Rd32=Gs32\",ATTRIBS(A_GUEST,A_NOTE_GUEST),\"Transfer Guest Reg to GPR\", {RdV=GsV;})\n+Q6INSN(G4_tfrgrcr,\"Gd32=Rs32\",ATTRIBS(A_GUEST,A_NOTE_GUEST),\"Transfer GPR to Guest Reg\", {GdV=RsV;})\n+Q6INSN(G4_tfrgcpp,\"Rdd32=Gss32\",ATTRIBS(A_GUEST,A_NOTE_GUEST),\"Transfer Guest Reg to GPR\", {RddV=GssV;})\n+Q6INSN(G4_tfrgpcp,\"Gdd32=Rss32\",ATTRIBS(A_GUEST,A_NOTE_GUEST),\"Transfer GPR to Guest Reg\", {GddV=RssV;})\n+\n+\n+\n+Q6INSN(Y2_setprio,\"setprio(Pt4,Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV),\"Change TID Prio of another thread\",\n+{fPREDUSE_TIMING();WRITE_PRIO(PtV & thread->processor_ptr->thread_system_mask,RsV); })\n+\n+\n+\n+\n+/********************************************/\n+/* Power Management / Thread on/off */\n+/********************************************/\n+Q6INSN(Y6_diag,\"diag(Rs32)\",ATTRIBS(),\"Send value to Diag trace module\",{\n+})\n+Q6INSN(Y6_diag0,\"diag0(Rss32,Rtt32)\",ATTRIBS(),\"Send values of two register to DIAG Trace. Set X=0\",{\n+})\n+Q6INSN(Y6_diag1,\"diag1(Rss32,Rtt32)\",ATTRIBS(),\"Send values of two register to DIAG Trace. Set X=1\",{\n+})\n+\n+\n+Q6INSN(Y4_trace,\"trace(Rs32)\",ATTRIBS(A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK),\"Send value to ETM trace\",{\n+ fDO_TRACE(RsV);\n+})\n+\n+Q6INSN(Y2_stop,\"stop(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\"Stop thread(s)\",{\n+ fHIDE(RsV=RsV;)\n+ if (!fIN_DEBUG_MODE_NO_ISDB(fGET_TNUM())) fCLEAR_RUN_MODE(fGET_TNUM());\n+})\n+\n+Q6INSN(Y4_nmi,\"nmi(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_NO_TIMING_LOG),\"Raise NMI on thread(s)\",{\n+ fDO_NMI(RsV);\n+})\n+\n+Q6INSN(Y2_start,\"start(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\"Start thread(s)\",fSTART(RsV);)\n+\n+Q6INSN(Y2_wait,\"wait(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_NO_TIMING_LOG),\"Make thread(s) wait\",{\n+ fHIDE(RsV=RsV;)\n+ if (!fIN_DEBUG_MODE(fGET_TNUM())) fSET_WAIT_MODE(fGET_TNUM());\n+\tfIN_DEBUG_MODE_WARN(fGET_TNUM());\n+})\n+\n+Q6INSN(Y2_resume,\"resume(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\"Make thread(s) stop waiting\",fRESUME(RsV);)\n+\n+Q6INSN(Y2_break,\"brkpt\",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\"Breakpoint\",{fBREAK();})\n+\n+\n+/********************************************/\n+/* Cache Management */\n+/********************************************/\n+\n+Q6INSN(Y2_ictagr,\"Rd32=ictagr(Rs32)\",ATTRIBS(A_ICOP,A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_ICTAGOP),\"Instruction Cache Tag Read\",{fICTAGR(RsV,RdV,RdN);})\n+Q6INSN(Y2_ictagw,\"ictagw(Rs32,Rt32)\",ATTRIBS(A_ICOP,A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_ICTAGOP),\"Instruction Cache Tag Write\",{fICTAGW(RsV,RtV);})\n+Q6INSN(Y2_icdataw,\"icdataw(Rs32,Rt32)\",ATTRIBS(A_ICOP,A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_ICTAGOP),\"Instruction Cache Data Write\",{fICDATAW(RsV,RtV);})\n+Q6INSN(Y2_icdatar,\"Rd32=icdatar(Rs32)\",ATTRIBS(A_ICOP,A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_ICTAGOP),\"Instruction Cache Data Read\",{fICDATAR(RsV, RdV);})\n+Q6INSN(Y2_icinva,\"icinva(Rs32)\",ATTRIBS(A_ICOP,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYADDRESS,A_ICFLUSHOP),\"Instruction Cache Invalidate Address\",{fEA_REG(RsV); fICINVA(EA);})\n+Q6INSN(Y2_icinvidx,\"icinvidx(Rs32)\",ATTRIBS(A_ICOP,A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_ICFLUSHOP),\"Instruction Cache Invalidate Index\",{fICINVIDX(RsV);})\n+Q6INSN(Y2_ickill,\"ickill\",ATTRIBS(A_ICOP,A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_ICFLUSHOP),\"Instruction Cache Invalidate\",{fICKILL();})\n+\n+Q6INSN(Y2_isync,\"isync\",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_NOPACKET),\"Memory Synchronization\",{fISYNC();})\n+Q6INSN(Y2_barrier,\"barrier\",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK),\"Memory Barrier\",{fBARRIER();})\n+Q6INSN(Y2_syncht,\"syncht\",ATTRIBS(A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET),\"Memory Synchronization\",{fSYNCH();})\n+\n+\n+Q6INSN(Y2_dcfetchbo,\"dcfetch(Rs32+#u11:3)\",ATTRIBS(A_RESTRICT_PREFERSLOT0,A_DCFETCH,A_RESTRICT_NOSLOT1_STORE),\"Data Cache Prefetch\",{fEA_RI(RsV,uiV); fDCFETCH(EA);})\n+Q6INSN(Y2_dckill,\"dckill\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_DCFLUSHOP),\"Data Cache Invalidate\",{fDCKILL();})\n+\n+\n+Q6INSN(Y2_dczeroa,\"dczeroa(Rs32)\",ATTRIBS(A_STORE,A_RESTRICT_SLOT1_AOK,A_NOTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCZEROA),\"Zero an aligned 32-byte cacheline\",{fEA_REG(RsV); fDCZEROA(EA);})\n+Q6INSN(Y2_dccleana,\"dccleana(Rs32)\",ATTRIBS(A_RESTRICT_SLOT1_AOK,A_NOTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCFLUSHOP),\"Data Cache Clean Address\",{fEA_REG(RsV); fDCCLEANA(EA);})\n+Q6INSN(Y2_dccleanidx,\"dccleanidx(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_DCFLUSHOP),\"Data Cache Clean Index\",{fDCCLEANIDX(RsV);})\n+Q6INSN(Y2_dccleaninva,\"dccleaninva(Rs32)\",ATTRIBS(A_RESTRICT_SLOT1_AOK,A_NOTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCFLUSHOP),\"Data Cache Clean and Invalidate Address\",{fEA_REG(RsV); fDCCLEANINVA(EA);})\n+Q6INSN(Y2_dccleaninvidx,\"dccleaninvidx(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_DCFLUSHOP),\"Data Cache Clean and Invalidate Index\",{fDCCLEANINVIDX(RsV);})\n+Q6INSN(Y2_dcinva,\"dcinva(Rs32)\",ATTRIBS(A_RESTRICT_SLOT1_AOK,A_NOTE_SLOT1_AOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYADDRESS,A_DCFLUSHOP),\"Data Cache Invalidate Address\",{fEA_REG(RsV); fDCCLEANINVA(EA);})\n+Q6INSN(Y2_dcinvidx,\"dcinvidx(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_DCFLUSHOP),\"Data Cache Invalidate Index\",{fDCINVIDX(RsV);})\n+Q6INSN(Y2_dctagr,\"Rd32=dctagr(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_DCTAGOP),\"Data Cache Tag Read\",{fDCTAGR(RsV,RdV,RdN);})\n+Q6INSN(Y2_dctagw,\"dctagw(Rs32,Rt32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_RESTRICT_SLOT0ONLY,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_DCTAGOP),\"Data Cache Tag Write\",{fDCTAGW(RsV,RtV);})\n+\n+\n+Q6INSN(Y2_l2kill,\"l2kill\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_L2FLUSHOP),\"L2 Cache Invalidate\",{fL2KILL();})\n+Q6INSN(Y4_l2tagw,\"l2tagw(Rs32,Rt32)\",ATTRIBS(A_PRIV,A_NOTE_BADTAG_UNDEF,A_NOTE_PRIV,A_RESTRICT_SLOT0ONLY,A_NOTE_NOPACKET,A_RESTRICT_NOPACKET,A_CACHEOP,A_COPBYIDX,A_L2TAGOP),\"L2 Cache Tag Write\",{fL2TAGW(RsV,RtV);})\n+Q6INSN(Y4_l2tagr,\"Rd32=l2tagr(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_BADTAG_UNDEF,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_L2TAGOP),\"L2 Cache Tag Read\",{fL2TAGR(RsV,RdV,RdN);})\n+\n+Q6INSN(Y2_l2cleaninvidx,\"l2cleaninvidx(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_L2FLUSHOP),\"L2 Cache Clean and Invalidate Index\",{fL2CLEANINVIDX(RsV); })\n+Q6INSN(Y5_l2cleanidx,\"l2cleanidx(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_L2FLUSHOP),\"L2 Cache Clean by Index\",{fL2CLEANIDX(RsV); })\n+Q6INSN(Y5_l2invidx,\"l2invidx(Rs32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_AXOK,A_RESTRICT_PACKET_AXOK,A_RESTRICT_SLOT0ONLY,A_CACHEOP,A_COPBYIDX,A_L2FLUSHOP),\"L2 Cache Invalidate by Index\",{fL2INVIDX(RsV); })\n+\n+\n+\n+Q6INSN(Y4_l2fetch,\"l2fetch(Rs32,Rt32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),\"L2 Cache Prefetch\",\n { fL2FETCH(RsV,\n (RtV&0xff), /*height*/\n ((RtV>>8)&0xff), /*width*/\n@@ -59,10 +258,29 @@ Q6INSN(Y4_l2fetch,\"l2fetch(Rs32,Rt32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY),\"L2 Cache P\n \n \n \n-Q6INSN(Y5_l2fetch,\"l2fetch(Rs32,Rtt32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY),\"L2 Cache Prefetch\",\n+Q6INSN(Y5_l2fetch,\"l2fetch(Rs32,Rtt32)\",ATTRIBS(A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK),\"L2 Cache Prefetch\",\n { fL2FETCH(RsV,\n fGETUHALF(0,RttV), /*height*/\n fGETUHALF(1,RttV), /*width*/\n fGETUHALF(2,RttV), /*stride*/\n fGETUHALF(3,RttV)); /*flags*/\n })\n+\n+Q6INSN(Y5_l2locka,\"Pd4=l2locka(Rs32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_CACHEOP,A_COPBYADDRESS,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK,A_RESTRICT_LATEPRED,A_NOTE_LATEPRED),\n+\"Lock L2 cache line by address\", { fEA_REG(RsV); fL2LOCKA(EA,PdV,PdN); fHIDE(MARK_LATE_PRED_WRITE(PdN)) })\n+\n+\n+Q6INSN(Y5_l2unlocka,\"l2unlocka(Rs32)\", ATTRIBS(A_PRIV,A_NOTE_PRIV,A_CACHEOP,A_COPBYADDRESS,A_RESTRICT_SLOT0ONLY,A_RESTRICT_PACKET_AXOK,A_NOTE_AXOK), \"UnLock L2 cache line by address\", { fEA_REG(RsV); fL2UNLOCKA(EA); })\n+\n+\n+\n+Q6INSN(Y5_l2gunlock,\"l2gunlock\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_L2FLUSHOP),\"L2 Global Unlock\",{fL2UNLOCK();})\n+\n+Q6INSN(Y5_l2gclean,\"l2gclean\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_L2FLUSHOP),\"L2 Global Clean\",{fL2CLEAN();})\n+\n+Q6INSN(Y5_l2gcleaninv,\"l2gcleaninv\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_L2FLUSHOP),\"L2 Global Clean and Invalidate\",{fL2CLEANINV();})\n+\n+Q6INSN(Y6_l2gcleanpa,\"l2gclean(Rtt32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_L2FLUSHOP),\"L2 Global Clean by PA Range\",{fL2CLEANPA(RttV);})\n+\n+Q6INSN(Y6_l2gcleaninvpa,\"l2gcleaninv(Rtt32)\",ATTRIBS(A_PRIV,A_NOTE_PRIV,A_NOTE_NOPACKET,A_RESTRICT_SLOT0ONLY,A_RESTRICT_NOPACKET,A_CACHEOP,A_L2FLUSHOP),\"L2 Global Clean and Invalidate by PA Range\",{fL2CLEANINVPA(RttV);})\n+\n", "prefixes": [ "v6", "23/37" ] }