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GET /api/patches/2218634/?format=api
{ "id": 2218634, "url": "http://patchwork.ozlabs.org/api/patches/2218634/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-32-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-32-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:51", "name": "[v6,31/37] target/hexagon: Add implementation of cycle counters", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1efb220570547b7ca614cc8f5ab15571ce9af396", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-32-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218634/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218634/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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Add implementation of cycle counters", "Date": "Wed, 1 Apr 2026 08:26:51 -0700", "Message-Id": "<20260401152657.314902-32-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "References": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Authority-Analysis": "v=2.4 cv=L90QguT8 c=1 sm=1 tr=0 ts=69cd3996 cx=c_pps\n a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22\n a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=Bw4caLd0n_0OF-yX4NUA:9 a=QEXdDO2ut3YA:10\n a=6Ab_bkdmUrQuMsNx7PHu:22", "X-Proofpoint-ORIG-GUID": "bN0JWieXwv1FdluPAT7Ryk0ByUuWAjO2", "X-Proofpoint-GUID": "bN0JWieXwv1FdluPAT7Ryk0ByUuWAjO2", "X-Proofpoint-Spam-Details-Enc": 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route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add cycle counting infrastructure for system emulation:\n- PCYCLE_ENABLED TB flag to gate cycle counting\n- gen_pcycle_counters() to emit cycle count increments\n- Real implementations replacing pcycle stubs in cpu_helper.c\n- hex_cycle_count TCG global for t_cycle_count\n- pcycle_enabled context field in DisasContext\n\nAll pcycle code is guarded by #ifndef CONFIG_USER_ONLY.\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 1 +\n target/hexagon/translate.h | 3 +++\n target/hexagon/cpu.c | 4 ++++\n target/hexagon/cpu_helper.c | 14 +++++++++++---\n target/hexagon/translate.c | 26 ++++++++++++++++++++++++++\n 5 files changed, 45 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 56f89209795..d3b7b346841 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -161,6 +161,7 @@ struct ArchCPU {\n #include \"cpu_bits.h\"\n \n FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)\n+FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1)\n \n G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,\n uint32_t exception,\ndiff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\nindex 7e528379db6..eaf48a865c2 100644\n--- a/target/hexagon/translate.h\n+++ b/target/hexagon/translate.h\n@@ -84,6 +84,9 @@ typedef struct DisasContext {\n TCGv new_pred_value[NUM_PREGS];\n TCGv branch_taken;\n TCGv dczero_addr;\n+ bool pcycle_enabled;\n+ bool pkt_ends_tb;\n+ uint32_t num_cycles;\n } DisasContext;\n \n bool is_gather_store_insn(DisasContext *ctx);\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 79ee4264c70..45ac9a3d24e 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -275,6 +275,10 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)\n hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0);\n }\n \n+#ifndef CONFIG_USER_ONLY\n+ hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1);\n+#endif\n+\n return (TCGTBCPUState){ .pc = pc, .flags = hex_flags };\n }\n \ndiff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c\nindex a2b486f4bb5..bb991a671e8 100644\n--- a/target/hexagon/cpu_helper.c\n+++ b/target/hexagon/cpu_helper.c\n@@ -33,17 +33,25 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index)\n \n uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env)\n {\n- g_assert_not_reached();\n+ uint64_t total = 0;\n+ CPUState *cs;\n+\n+ g_assert(bql_locked());\n+ CPU_FOREACH(cs) {\n+ CPUHexagonState *thread_env = cpu_env(cs);\n+ total += thread_env->t_cycle_count;\n+ }\n+ return total;\n }\n \n uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env)\n {\n- g_assert_not_reached();\n+ return (uint32_t)(hexagon_get_sys_pcycle_count(env) >> 32);\n }\n \n uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env)\n {\n- g_assert_not_reached();\n+ return (uint32_t)(hexagon_get_sys_pcycle_count(env));\n }\n \n void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t val)\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 01445fdcbac..91dff442c80 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -61,6 +61,9 @@ TCGv_i64 hex_store_val64[STORES_MAX];\n TCGv hex_llsc_addr;\n TCGv hex_llsc_val;\n TCGv_i64 hex_llsc_val_i64;\n+#ifndef CONFIG_USER_ONLY\n+TCGv_i64 hex_cycle_count;\n+#endif\n TCGv hex_vstore_addr[VSTORES_MAX];\n TCGv hex_vstore_size[VSTORES_MAX];\n TCGv hex_vstore_pending[VSTORES_MAX];\n@@ -128,6 +131,15 @@ static void gen_exception_raw(int excp)\n gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));\n }\n \n+#ifndef CONFIG_USER_ONLY\n+static void gen_pcycle_counters(DisasContext *ctx)\n+{\n+ if (ctx->pcycle_enabled) {\n+ tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles);\n+ }\n+}\n+#endif\n+\n static void gen_exec_counters(DisasContext *ctx)\n {\n tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT],\n@@ -136,6 +148,9 @@ static void gen_exec_counters(DisasContext *ctx)\n hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns);\n tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT],\n hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns);\n+#ifndef CONFIG_USER_ONLY\n+ gen_pcycle_counters(ctx);\n+#endif\n }\n \n static bool use_goto_tb(DisasContext *ctx, target_ulong dest)\n@@ -821,6 +836,8 @@ static void gen_commit_hvx(DisasContext *ctx)\n }\n }\n \n+#define PCYCLES_PER_PACKET 1\n+\n static void update_exec_counters(DisasContext *ctx)\n {\n Packet *pkt = ctx->pkt;\n@@ -842,6 +859,7 @@ static void update_exec_counters(DisasContext *ctx)\n ctx->num_packets++;\n ctx->num_insns += num_real_insns;\n ctx->num_hvx_insns += num_hvx_insns;\n+ ctx->num_cycles += PCYCLES_PER_PACKET;\n }\n \n static void gen_commit_packet(DisasContext *ctx)\n@@ -994,6 +1012,10 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->branch_cond = TCG_COND_NEVER;\n ctx->is_tight_loop = FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP);\n ctx->short_circuit = hex_cpu->short_circuit;\n+#ifndef CONFIG_USER_ONLY\n+ ctx->num_cycles = 0;\n+ ctx->pcycle_enabled = FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED);\n+#endif\n }\n \n static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n@@ -1136,6 +1158,10 @@ void hexagon_translate_init(void)\n offsetof(CPUHexagonState, llsc_val), \"llsc_val\");\n hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env,\n offsetof(CPUHexagonState, llsc_val_i64), \"llsc_val_i64\");\n+#ifndef CONFIG_USER_ONLY\n+ hex_cycle_count = tcg_global_mem_new_i64(tcg_env,\n+ offsetof(CPUHexagonState, t_cycle_count), \"t_cycle_count\");\n+#endif\n for (i = 0; i < STORES_MAX; i++) {\n snprintf(store_addr_names[i], NAME_LEN, \"store_addr_%d\", i);\n hex_store_addr[i] = tcg_global_mem_new(tcg_env,\n", "prefixes": [ "v6", "31/37" ] }