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GET /api/patches/2218633/?format=api
{ "id": 2218633, "url": "http://patchwork.ozlabs.org/api/patches/2218633/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-10-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-10-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:29", "name": "[v6,09/37] target/hexagon: Add privilege check, use tag_ignore()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "900be6d00755976403fd1670e36a2510459b5c30", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-10-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218633/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218633/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=iuQ56rp2;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=feCMGJn9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-GUID": "62mH5AYyryEiP59zp3jpa5A4uQr0FGQ2", "X-Proofpoint-ORIG-GUID": "62mH5AYyryEiP59zp3jpa5A4uQr0FGQ2", "X-Authority-Analysis": "v=2.4 cv=B/C0EetM c=1 sm=1 tr=0 ts=69cd39a6 cx=c_pps\n a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22\n a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=pksD3ONYjMjZD1LmeuAA:9 a=QEXdDO2ut3YA:10\n a=bBxd6f-gb0O0v-kibOvt:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfX82uKNiIFgksp\n hnntxbs0Rq+jjtvG74VucGSCFMOe+zmu5TMktmhlxj+PXCgM4sATK1hTEx7Ja3P5nxySCG3TNVM\n oi0Lw37eiMw58dGTmzYYP9VO965YZIlBWQDOLTpHYoZYiETtF8zGMZ07cfaxP2lWronIvpv2XaJ\n dS4RQAZWlTxjN2f0yqbbJOfZF3CbcQGhvnW+SjHDhETnv2xH2UZrg73y2fnzUE8nE+1xo2bwtSx\n FJu7s93VVSg7EzImO+D8j7jy5uV5UZr7ho3nHDkmwHTbcOiyguIVUDt1ufO98ujeQJrOjdqgPyd\n g/j8UV1oS8Z6C7MO+TR3N2R6M8eMZy8KsrngDKF2Hhr5+Ivyy84p0geu/OaHjWv/LS8e1hoktRb\n zQR24TerFN1tA789VIyMPr87zN2nu9OMsHHTLyVQ/ik0GQVBzGELsf5Ud3jik+IryFdK+q1aIeH\n sqGT5xk3tTuDTcMlWOA==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-01_04,2026-04-01_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 malwarescore=0\n lowpriorityscore=0 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add system event and cause code definitions needed for exception\nhandling in sysemu mode. Add privilege checks that raise exceptions\nfor guest/supervisor-only instructions executed without appropriate\nprivilege.\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.h | 10 +++++\n target/hexagon/cpu_bits.h | 75 +++++++++++++++++++++++++++++----\n linux-user/hexagon/cpu_loop.c | 16 +++++++\n target/hexagon/cpu.c | 1 +\n target/hexagon/translate.c | 8 ++++\n target/hexagon/gen_tcg_funcs.py | 35 +++++++++------\n 6 files changed, 123 insertions(+), 22 deletions(-)", "diff": "diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 85afd592778..937194e460e 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -44,6 +44,15 @@\n \n #define MMU_USER_IDX 0\n \n+#define HEXAGON_CPU_IRQ_0 0\n+#define HEXAGON_CPU_IRQ_1 1\n+#define HEXAGON_CPU_IRQ_2 2\n+#define HEXAGON_CPU_IRQ_3 3\n+#define HEXAGON_CPU_IRQ_4 4\n+#define HEXAGON_CPU_IRQ_5 5\n+#define HEXAGON_CPU_IRQ_6 6\n+#define HEXAGON_CPU_IRQ_7 7\n+\n typedef struct {\n target_ulong va;\n uint32_t width;\n@@ -76,6 +85,7 @@ typedef struct {\n typedef struct CPUArchState {\n target_ulong gpr[TOTAL_PER_THREAD_REGS];\n target_ulong pred[NUM_PREGS];\n+ uint32_t cause_code;\n \n /* For comparing with LLDB on target - see adjust_stack_ptrs function */\n target_ulong last_pc_dumped;\ndiff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 19beca81c0c..91e9da09e03 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -24,20 +24,77 @@\n #define PCALIGN_MASK (PCALIGN - 1)\n \n enum hex_event {\n- HEX_EVENT_NONE = -1,\n- HEX_EVENT_TRAP0 = 0x008,\n+ HEX_EVENT_NONE = -1,\n+ HEX_EVENT_RESET = 0x0,\n+ HEX_EVENT_IMPRECISE = 0x1,\n+ HEX_EVENT_PRECISE = 0x2,\n+ HEX_EVENT_TLB_MISS_X = 0x4,\n+ HEX_EVENT_TLB_MISS_RW = 0x6,\n+ HEX_EVENT_TRAP0 = 0x8,\n+ HEX_EVENT_TRAP1 = 0x9,\n+ HEX_EVENT_FPTRAP = 0xb,\n+ HEX_EVENT_DEBUG = 0xc,\n+ HEX_EVENT_INT0 = 0x10,\n+ HEX_EVENT_INT1 = 0x11,\n+ HEX_EVENT_INT2 = 0x12,\n+ HEX_EVENT_INT3 = 0x13,\n+ HEX_EVENT_INT4 = 0x14,\n+ HEX_EVENT_INT5 = 0x15,\n+ HEX_EVENT_INT6 = 0x16,\n+ HEX_EVENT_INT7 = 0x17,\n+ HEX_EVENT_INT8 = 0x18,\n+ HEX_EVENT_INT9 = 0x19,\n+ HEX_EVENT_INTA = 0x1a,\n+ HEX_EVENT_INTB = 0x1b,\n+ HEX_EVENT_INTC = 0x1c,\n+ HEX_EVENT_INTD = 0x1d,\n+ HEX_EVENT_INTE = 0x1e,\n+ HEX_EVENT_INTF = 0x1f,\n };\n \n enum hex_cause {\n HEX_CAUSE_NONE = -1,\n- HEX_CAUSE_TRAP0 = 0x172,\n- HEX_CAUSE_FETCH_NO_UPAGE = 0x012,\n- HEX_CAUSE_INVALID_PACKET = 0x015,\n- HEX_CAUSE_INVALID_OPCODE = 0x015,\n+ HEX_CAUSE_RESET = 0x000,\n+ HEX_CAUSE_BIU_PRECISE = 0x001,\n+ HEX_CAUSE_UNSUPPORTED_HVX_64B = 0x002, /* QEMU-specific */\n+ HEX_CAUSE_DOUBLE_EXCEPT = 0x003,\n+ HEX_CAUSE_TRAP0 = 0x008,\n+ HEX_CAUSE_TRAP1 = 0x009,\n+ HEX_CAUSE_FETCH_NO_XPAGE = 0x011,\n+ HEX_CAUSE_FETCH_NO_UPAGE = 0x012,\n+ HEX_CAUSE_INVALID_PACKET = 0x015,\n+ HEX_CAUSE_INVALID_OPCODE = 0x015, /* alias: same cause as INVALID_PACKET */\n+ HEX_CAUSE_NO_COPROC_ENABLE = 0x016,\n+ HEX_CAUSE_NO_COPROC2_ENABLE = 0x018,\n+ HEX_CAUSE_PRIV_USER_NO_GINSN = 0x01a,\n+ HEX_CAUSE_PRIV_USER_NO_SINSN = 0x01b,\n HEX_CAUSE_REG_WRITE_CONFLICT = 0x01d,\n- HEX_CAUSE_PC_NOT_ALIGNED = 0x01e,\n- HEX_CAUSE_PRIV_NO_UREAD = 0x024,\n- HEX_CAUSE_PRIV_NO_UWRITE = 0x025,\n+ HEX_CAUSE_PC_NOT_ALIGNED = 0x01e,\n+ HEX_CAUSE_MISALIGNED_LOAD = 0x020,\n+ HEX_CAUSE_MISALIGNED_STORE = 0x021,\n+ HEX_CAUSE_PRIV_NO_READ = 0x022,\n+ HEX_CAUSE_PRIV_NO_WRITE = 0x023,\n+ HEX_CAUSE_PRIV_NO_UREAD = 0x024,\n+ HEX_CAUSE_PRIV_NO_UWRITE = 0x025,\n+ HEX_CAUSE_COPROC_LDST = 0x026,\n+ HEX_CAUSE_STACK_LIMIT = 0x027,\n+ HEX_CAUSE_VWCTRL_WINDOW_MISS = 0x029,\n+ HEX_CAUSE_IMPRECISE_NMI = 0x043,\n+ HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH = 0x044,\n+ HEX_CAUSE_TLBMISSX_CAUSE_NORMAL = 0x060,\n+ HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE = 0x061,\n+ HEX_CAUSE_TLBMISSRW_CAUSE_READ = 0x070,\n+ HEX_CAUSE_TLBMISSRW_CAUSE_WRITE = 0x071,\n+ HEX_CAUSE_DEBUG_SINGLESTEP = 0x80,\n+ HEX_CAUSE_FPTRAP_CAUSE_BADFLOAT = 0x0bf,\n+ HEX_CAUSE_INT0 = 0x0c0,\n+ HEX_CAUSE_INT1 = 0x0c1,\n+ HEX_CAUSE_INT2 = 0x0c2,\n+ HEX_CAUSE_INT3 = 0x0c3,\n+ HEX_CAUSE_INT4 = 0x0c4,\n+ HEX_CAUSE_INT5 = 0x0c5,\n+ HEX_CAUSE_INT6 = 0x0c6,\n+ HEX_CAUSE_INT7 = 0x0c7,\n };\n \n #define PACKET_WORDS_MAX 4\ndiff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c\nindex 9464246e9e3..9f54c7b3f96 100644\n--- a/linux-user/hexagon/cpu_loop.c\n+++ b/linux-user/hexagon/cpu_loop.c\n@@ -22,6 +22,7 @@\n #include \"qemu.h\"\n #include \"user-internals.h\"\n #include \"user/cpu_loop.h\"\n+#include \"target/hexagon/internal.h\"\n #include \"signal-common.h\"\n #include \"internal.h\"\n \n@@ -60,6 +61,21 @@ void cpu_loop(CPUHexagonState *env)\n env->gpr[0] = ret;\n }\n break;\n+ case HEX_EVENT_PRECISE:\n+ switch (env->cause_code) {\n+ case HEX_CAUSE_PRIV_USER_NO_GINSN:\n+ case HEX_CAUSE_PRIV_USER_NO_SINSN:\n+ case HEX_CAUSE_INVALID_PACKET:\n+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC,\n+ env->gpr[HEX_REG_PC]);\n+ break;\n+ default:\n+ EXCP_DUMP(env, \"\\nqemu: unhandled CPU precise exception \"\n+ \"cause code 0x%x - aborting\\n\",\n+ env->cause_code);\n+ exit(EXIT_FAILURE);\n+ }\n+ break;\n case HEX_CAUSE_PC_NOT_ALIGNED:\n force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,\n env->gpr[HEX_REG_R31]);\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 4f72d4759cf..a4dcad5f7a5 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -306,6 +306,7 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);\n /* Default NaN value: sign bit set, all frac bits set */\n set_float_default_nan_pattern(0b11111111, &env->fp_status);\n+ env->cause_code = HEX_EVENT_NONE;\n }\n \n static void hexagon_cpu_disas_set_info(const CPUState *cs,\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 1f4ac2c3c84..c947db85ab7 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -65,6 +65,10 @@ TCGv hex_vstore_addr[VSTORES_MAX];\n TCGv hex_vstore_size[VSTORES_MAX];\n TCGv hex_vstore_pending[VSTORES_MAX];\n \n+#ifndef CONFIG_USER_ONLY\n+TCGv_i32 hex_cause_code;\n+#endif\n+\n static const char * const hexagon_prednames[] = {\n \"p0\", \"p1\", \"p2\", \"p3\"\n };\n@@ -1153,4 +1157,8 @@ void hexagon_translate_init(void)\n offsetof(CPUHexagonState, vstore_pending[i]),\n vstore_pending_names[i]);\n }\n+#ifndef CONFIG_USER_ONLY\n+ hex_cause_code = tcg_global_mem_new(tcg_env,\n+ offsetof(CPUHexagonState, cause_code), \"cause_code\");\n+#endif\n }\ndiff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py\nindex 87b7f10d7fd..d91bbcf1dc8 100755\n--- a/target/hexagon/gen_tcg_funcs.py\n+++ b/target/hexagon/gen_tcg_funcs.py\n@@ -21,7 +21,7 @@\n import re\n import string\n import hex_common\n-\n+from textwrap import dedent\n \n ##\n ## Generate the TCG code to call the helper\n@@ -49,6 +49,18 @@ def gen_tcg_func(f, tag, regs, imms):\n \n f.write(\" Insn *insn G_GNUC_UNUSED = ctx->insn;\\n\")\n \n+ if \"A_PRIV\" in hex_common.attribdict[tag]:\n+ f.write(dedent(\"\"\"\\\n+#ifdef CONFIG_USER_ONLY\n+ hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_SINSN);\n+#else\n+\"\"\"))\n+ if \"A_GUEST\" in hex_common.attribdict[tag]:\n+ f.write(dedent(\"\"\"\\\n+#ifdef CONFIG_USER_ONLY\n+ hex_gen_exception_end_tb(ctx, HEX_CAUSE_PRIV_USER_NO_GINSN);\n+#else\n+\"\"\"))\n if hex_common.need_ea(tag):\n f.write(\" TCGv EA G_GNUC_UNUSED = tcg_temp_new();\\n\")\n \n@@ -100,6 +112,11 @@ def gen_tcg_func(f, tag, regs, imms):\n if reg.is_written():\n reg.gen_write(f, tag)\n \n+ if (\n+ \"A_PRIV\" in hex_common.attribdict[tag]\n+ or \"A_GUEST\" in hex_common.attribdict[tag]\n+ ):\n+ f.write(\"#endif /* CONFIG_USER_ONLY */\\n\")\n f.write(\"}\\n\\n\")\n \n \n@@ -124,18 +141,10 @@ def main():\n f.write('#include \"idef-generated-emitter.h.inc\"\\n\\n')\n \n for tag in hex_common.tags:\n- ## Skip the priv instructions\n- if \"A_PRIV\" in hex_common.attribdict[tag]:\n- continue\n- ## Skip the guest instructions\n- if \"A_GUEST\" in hex_common.attribdict[tag]:\n- continue\n- ## Skip the diag instructions\n- if tag == \"Y6_diag\":\n- continue\n- if tag == \"Y6_diag0\":\n- continue\n- if tag == \"Y6_diag1\":\n+ if hex_common.tag_ignore(tag):\n+ f.write(f\"static void generate_{tag}\"\n+ f\"(DisasContext *ctx)\\n\")\n+ f.write(\"{\\n}\\n\\n\")\n continue\n \n gen_def_tcg_func(f, tag, tagregs, tagimms)\n", "prefixes": [ "v6", "09/37" ] }