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GET /api/patches/2218632/?format=api
{ "id": 2218632, "url": "http://patchwork.ozlabs.org/api/patches/2218632/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-35-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-35-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:54", "name": "[v6,34/37] hw/hexagon: Introduce hexagon TLB device", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f3e047a45cfa1b4701d312938c54e25cfd43f608", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-35-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218632/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218632/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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Introduce hexagon TLB device", "Date": "Wed, 1 Apr 2026 08:26:54 -0700", "Message-Id": "<20260401152657.314902-35-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "References": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Authority-Analysis": "v=2.4 cv=B+O0EetM c=1 sm=1 tr=0 ts=69cd3994 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22\n a=EUspDBNiAAAA:8 a=_ljVuOvC_GqhvFfVm74A:9 a=QEXdDO2ut3YA:10\n a=scEy_gLbYbu1JhEsrz4S:22", "X-Proofpoint-ORIG-GUID": "f6OxWdo39XfAGDzD8Uh1YxcJdtOugLdr", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfXwNHKDOgwJ0G3\n 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authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add the hexagon TLB QOM device model.\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n include/hw/hexagon/hexagon_tlb.h | 46 +++\n target/hexagon/cpu.h | 7 +\n hw/hexagon/hexagon_tlb.c | 466 +++++++++++++++++++++++++++++++\n target/hexagon/cpu.c | 3 +\n 4 files changed, 522 insertions(+)\n create mode 100644 include/hw/hexagon/hexagon_tlb.h\n create mode 100644 hw/hexagon/hexagon_tlb.c", "diff": "diff --git a/include/hw/hexagon/hexagon_tlb.h b/include/hw/hexagon/hexagon_tlb.h\nnew file mode 100644\nindex 00000000000..90d9ed84043\n--- /dev/null\n+++ b/include/hw/hexagon/hexagon_tlb.h\n@@ -0,0 +1,46 @@\n+/*\n+ * Hexagon TLB QOM Device\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_HEXAGON_TLB_H\n+#define HW_HEXAGON_TLB_H\n+\n+#include \"hw/core/sysbus.h\"\n+#include \"qom/object.h\"\n+#include \"exec/hwaddr.h\"\n+#include \"exec/mmu-access-type.h\"\n+#include \"monitor/monitor.h\"\n+#define TYPE_HEXAGON_TLB \"hexagon-tlb\"\n+OBJECT_DECLARE_SIMPLE_TYPE(HexagonTLBState, HEXAGON_TLB)\n+\n+struct HexagonTLBState {\n+ SysBusDevice parent_obj;\n+\n+ uint32_t num_entries;\n+ uint64_t *entries;\n+};\n+\n+uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index);\n+void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t value);\n+\n+bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid,\n+ uint32_t VA, MMUAccessType access_type,\n+ hwaddr *PA, int *prot, uint64_t *size,\n+ int32_t *excp, int *cause_code, int mmu_idx);\n+\n+uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid,\n+ uint32_t VA, int *cause_code);\n+\n+int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry,\n+ uint64_t index);\n+\n+void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb);\n+\n+bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry);\n+\n+uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb);\n+\n+#endif /* HW_HEXAGON_TLB_H */\ndiff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex d3361936d04..15dd99d2155 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -27,6 +27,9 @@\n #define SREG_WRITES_MAX 2\n #endif\n \n+typedef struct HexagonTLBState HexagonTLBState;\n+typedef struct HexagonGlobalRegState HexagonGlobalRegState;\n+\n #include \"cpu-qom.h\"\n #include \"exec/cpu-common.h\"\n #include \"exec/cpu-defs.h\"\n@@ -46,6 +49,7 @@\n #define REG_WRITES_MAX 32\n #define PRED_WRITES_MAX 5 /* 4 insns + endloop */\n #define VSTORES_MAX 2\n+#define MAX_TLB_ENTRIES 1024\n \n #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU\n #ifndef CONFIG_USER_ONLY\n@@ -175,6 +179,9 @@ struct ArchCPU {\n bool lldb_compat;\n target_ulong lldb_stack_adjust;\n bool short_circuit;\n+#ifndef CONFIG_USER_ONLY\n+ HexagonTLBState *tlb;\n+#endif\n };\n \n #include \"cpu_bits.h\"\ndiff --git a/hw/hexagon/hexagon_tlb.c b/hw/hexagon/hexagon_tlb.c\nnew file mode 100644\nindex 00000000000..d218e97446c\n--- /dev/null\n+++ b/hw/hexagon/hexagon_tlb.c\n@@ -0,0 +1,466 @@\n+/*\n+ * Hexagon TLB QOM Device\n+ *\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/hexagon/hexagon_tlb.h\"\n+#include \"hw/core/qdev-properties.h\"\n+#include \"hw/core/resettable.h\"\n+#include \"migration/vmstate.h\"\n+#include \"monitor/monitor.h\"\n+#include \"qapi/error.h\"\n+#include \"exec/target_page.h\"\n+#include \"target/hexagon/cpu.h\"\n+#include \"target/hexagon/cpu_bits.h\"\n+\n+/* PTE (TLB entry) field extraction */\n+#define GET_PTE_PPD(entry) extract64((entry), 0, 24)\n+#define GET_PTE_C(entry) extract64((entry), 24, 4)\n+#define GET_PTE_U(entry) extract64((entry), 28, 1)\n+#define GET_PTE_R(entry) extract64((entry), 29, 1)\n+#define GET_PTE_W(entry) extract64((entry), 30, 1)\n+#define GET_PTE_X(entry) extract64((entry), 31, 1)\n+#define GET_PTE_VPN(entry) extract64((entry), 32, 20)\n+#define GET_PTE_ASID(entry) extract64((entry), 52, 7)\n+#define GET_PTE_ATR0(entry) extract64((entry), 59, 1)\n+#define GET_PTE_ATR1(entry) extract64((entry), 60, 1)\n+#define GET_PTE_PA35(entry) extract64((entry), 61, 1)\n+#define GET_PTE_G(entry) extract64((entry), 62, 1)\n+#define GET_PTE_V(entry) extract64((entry), 63, 1)\n+\n+/* PPD (physical page descriptor) */\n+static inline uint64_t GET_PPD(uint64_t entry)\n+{\n+ return GET_PTE_PPD(entry) | (GET_PTE_PA35(entry) << 24);\n+}\n+\n+#define NO_ASID (1 << 8)\n+\n+typedef enum {\n+ PGSIZE_4K,\n+ PGSIZE_16K,\n+ PGSIZE_64K,\n+ PGSIZE_256K,\n+ PGSIZE_1M,\n+ PGSIZE_4M,\n+ PGSIZE_16M,\n+ PGSIZE_64M,\n+ PGSIZE_256M,\n+ PGSIZE_1G,\n+} tlb_pgsize_t;\n+\n+#define NUM_PGSIZE_TYPES (PGSIZE_1G + 1)\n+\n+static const char *pgsize_str[NUM_PGSIZE_TYPES] = {\n+ \"4K\",\n+ \"16K\",\n+ \"64K\",\n+ \"256K\",\n+ \"1M\",\n+ \"4M\",\n+ \"16M\",\n+ \"64M\",\n+ \"256M\",\n+ \"1G\",\n+};\n+\n+#define INVALID_MASK 0xffffffffLL\n+\n+static const uint64_t encmask_2_mask[] = {\n+ 0x0fffLL, /* 4k, 0000 */\n+ 0x3fffLL, /* 16k, 0001 */\n+ 0xffffLL, /* 64k, 0010 */\n+ 0x3ffffLL, /* 256k, 0011 */\n+ 0xfffffLL, /* 1m, 0100 */\n+ 0x3fffffLL, /* 4m, 0101 */\n+ 0xffffffLL, /* 16m, 0110 */\n+ 0x3ffffffLL, /* 64m, 0111 */\n+ 0xfffffffLL, /* 256m, 1000 */\n+ 0x3fffffffLL, /* 1g, 1001 */\n+ INVALID_MASK, /* RSVD, 1010 */\n+};\n+\n+static inline tlb_pgsize_t hex_tlb_pgsize_type(uint64_t entry)\n+{\n+ if (entry == 0) {\n+ qemu_log_mask(CPU_LOG_MMU, \"%s: Supplied TLB entry was 0!\\n\",\n+ __func__);\n+ return 0;\n+ }\n+ tlb_pgsize_t size = ctz64(entry);\n+ g_assert(size < NUM_PGSIZE_TYPES);\n+ return size;\n+}\n+\n+static inline uint64_t hex_tlb_page_size_bytes(uint64_t entry)\n+{\n+ return 1ull << (qemu_target_page_bits() + 2 * hex_tlb_pgsize_type(entry));\n+}\n+\n+static inline uint64_t hex_tlb_phys_page_num(uint64_t entry)\n+{\n+ uint32_t ppd = GET_PPD(entry);\n+ return ppd >> 1;\n+}\n+\n+static inline uint64_t hex_tlb_phys_addr(uint64_t entry)\n+{\n+ uint64_t pagemask = encmask_2_mask[hex_tlb_pgsize_type(entry)];\n+ uint64_t pagenum = hex_tlb_phys_page_num(entry);\n+ uint64_t PA = (pagenum << qemu_target_page_bits()) & (~pagemask);\n+ return PA;\n+}\n+\n+static inline uint64_t hex_tlb_virt_addr(uint64_t entry)\n+{\n+ return (uint64_t)GET_PTE_VPN(entry) << qemu_target_page_bits();\n+}\n+\n+bool hexagon_tlb_dump_entry(Monitor *mon, uint64_t entry)\n+{\n+ if (GET_PTE_V(entry)) {\n+ uint64_t PA = hex_tlb_phys_addr(entry);\n+ uint64_t VA = hex_tlb_virt_addr(entry);\n+ monitor_printf(mon, \"0x%016\" PRIx64 \": \", entry);\n+ monitor_printf(mon, \"V:%\" PRId64 \" G:%\" PRId64\n+ \" A1:%\" PRId64 \" A0:%\" PRId64,\n+ GET_PTE_V(entry),\n+ GET_PTE_G(entry),\n+ GET_PTE_ATR1(entry),\n+ GET_PTE_ATR0(entry));\n+ monitor_printf(mon, \" ASID:0x%02\" PRIx64 \" VA:0x%08\" PRIx64,\n+ GET_PTE_ASID(entry), VA);\n+ monitor_printf(mon,\n+ \" X:%\" PRId64 \" W:%\" PRId64 \" R:%\" PRId64\n+ \" U:%\" PRId64 \" C:%\" PRId64,\n+ GET_PTE_X(entry),\n+ GET_PTE_W(entry),\n+ GET_PTE_R(entry),\n+ GET_PTE_U(entry),\n+ GET_PTE_C(entry));\n+ monitor_printf(mon, \" PA:0x%09\" PRIx64 \" SZ:%s (0x%\" PRIx64 \")\",\n+ PA, pgsize_str[hex_tlb_pgsize_type(entry)],\n+ hex_tlb_page_size_bytes(entry));\n+ monitor_printf(mon, \"\\n\");\n+ return true;\n+ }\n+\n+ /* Not valid */\n+ return false;\n+}\n+\n+static inline bool hex_tlb_entry_match_noperm(uint64_t entry, uint32_t asid,\n+ uint64_t VA)\n+{\n+ if (GET_PTE_V(entry)) {\n+ if (GET_PTE_G(entry)) {\n+ /* Global entry - ignore ASID */\n+ } else if (asid != NO_ASID) {\n+ uint32_t tlb_asid = GET_PTE_ASID(entry);\n+ if (tlb_asid != asid) {\n+ return false;\n+ }\n+ }\n+\n+ uint64_t page_size = hex_tlb_page_size_bytes(entry);\n+ uint64_t page_start =\n+ ROUND_DOWN(hex_tlb_virt_addr(entry), page_size);\n+ if (page_start <= VA && VA < page_start + page_size) {\n+ return true;\n+ }\n+ }\n+ return false;\n+}\n+\n+static inline void hex_tlb_entry_get_perm(uint64_t entry,\n+ MMUAccessType access_type,\n+ int mmu_idx, int *prot,\n+ int32_t *excp, int *cause_code)\n+{\n+ bool perm_x = GET_PTE_X(entry);\n+ bool perm_w = GET_PTE_W(entry);\n+ bool perm_r = GET_PTE_R(entry);\n+ bool perm_u = GET_PTE_U(entry);\n+ bool user_idx = mmu_idx == MMU_USER_IDX;\n+\n+ if (mmu_idx == MMU_KERNEL_IDX) {\n+ *prot = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n+ return;\n+ }\n+\n+ *prot = PAGE_VALID;\n+ switch (access_type) {\n+ case MMU_INST_FETCH:\n+ if (user_idx && !perm_u) {\n+ *excp = HEX_EVENT_PRECISE;\n+ *cause_code = HEX_CAUSE_FETCH_NO_UPAGE;\n+ } else if (!perm_x) {\n+ *excp = HEX_EVENT_PRECISE;\n+ *cause_code = HEX_CAUSE_FETCH_NO_XPAGE;\n+ }\n+ break;\n+ case MMU_DATA_LOAD:\n+ if (user_idx && !perm_u) {\n+ *excp = HEX_EVENT_PRECISE;\n+ *cause_code = HEX_CAUSE_PRIV_NO_UREAD;\n+ } else if (!perm_r) {\n+ *excp = HEX_EVENT_PRECISE;\n+ *cause_code = HEX_CAUSE_PRIV_NO_READ;\n+ }\n+ break;\n+ case MMU_DATA_STORE:\n+ if (user_idx && !perm_u) {\n+ *excp = HEX_EVENT_PRECISE;\n+ *cause_code = HEX_CAUSE_PRIV_NO_UWRITE;\n+ } else if (!perm_w) {\n+ *excp = HEX_EVENT_PRECISE;\n+ *cause_code = HEX_CAUSE_PRIV_NO_WRITE;\n+ }\n+ break;\n+ }\n+\n+ if (!user_idx || perm_u) {\n+ if (perm_x) {\n+ *prot |= PAGE_EXEC;\n+ }\n+ if (perm_r) {\n+ *prot |= PAGE_READ;\n+ }\n+ if (perm_w) {\n+ *prot |= PAGE_WRITE;\n+ }\n+ }\n+}\n+\n+static inline bool hex_tlb_entry_match(uint64_t entry, uint8_t asid,\n+ uint32_t VA,\n+ MMUAccessType access_type, hwaddr *PA,\n+ int *prot, uint64_t *size,\n+ int32_t *excp, int *cause_code,\n+ int mmu_idx)\n+{\n+ if (hex_tlb_entry_match_noperm(entry, asid, VA)) {\n+ hex_tlb_entry_get_perm(entry, access_type, mmu_idx, prot, excp,\n+ cause_code);\n+ *PA = hex_tlb_phys_addr(entry);\n+ *size = hex_tlb_page_size_bytes(entry);\n+ return true;\n+ }\n+ return false;\n+}\n+\n+static bool hex_tlb_is_match(uint64_t entry1, uint64_t entry2,\n+ bool consider_gbit)\n+{\n+ bool valid1 = GET_PTE_V(entry1);\n+ bool valid2 = GET_PTE_V(entry2);\n+ uint64_t size1 = hex_tlb_page_size_bytes(entry1);\n+ uint64_t vaddr1 = ROUND_DOWN(hex_tlb_virt_addr(entry1), size1);\n+ uint64_t size2 = hex_tlb_page_size_bytes(entry2);\n+ uint64_t vaddr2 = ROUND_DOWN(hex_tlb_virt_addr(entry2), size2);\n+ int asid1 = GET_PTE_ASID(entry1);\n+ int asid2 = GET_PTE_ASID(entry2);\n+ bool gbit1 = GET_PTE_G(entry1);\n+ bool gbit2 = GET_PTE_G(entry2);\n+\n+ if (!valid1 || !valid2) {\n+ return false;\n+ }\n+\n+ if (((vaddr1 <= vaddr2) && (vaddr2 < (vaddr1 + size1))) ||\n+ ((vaddr2 <= vaddr1) && (vaddr1 < (vaddr2 + size2)))) {\n+ if (asid1 == asid2) {\n+ return true;\n+ }\n+ if ((consider_gbit && gbit1) || gbit2) {\n+ return true;\n+ }\n+ }\n+ return false;\n+}\n+\n+/* Public API */\n+\n+uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index)\n+{\n+ g_assert(index < tlb->num_entries);\n+ return tlb->entries[index];\n+}\n+\n+void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t value)\n+{\n+ g_assert(index < tlb->num_entries);\n+ tlb->entries[index] = value;\n+}\n+\n+bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid,\n+ uint32_t VA, MMUAccessType access_type,\n+ hwaddr *PA, int *prot, uint64_t *size,\n+ int32_t *excp, int *cause_code, int mmu_idx)\n+{\n+ *PA = 0;\n+ *prot = 0;\n+ *size = 0;\n+ *excp = 0;\n+ *cause_code = 0;\n+\n+ for (uint32_t i = 0; i < tlb->num_entries; i++) {\n+ if (hex_tlb_entry_match(tlb->entries[i], asid, VA, access_type,\n+ PA, prot, size, excp, cause_code, mmu_idx)) {\n+ return true;\n+ }\n+ }\n+ return false;\n+}\n+\n+uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid,\n+ uint32_t VA, int *cause_code)\n+{\n+ uint32_t not_found = 0x80000000;\n+ uint32_t idx = not_found;\n+\n+ for (uint32_t i = 0; i < tlb->num_entries; i++) {\n+ uint64_t entry = tlb->entries[i];\n+ if (hex_tlb_entry_match_noperm(entry, asid, VA)) {\n+ if (idx != not_found) {\n+ *cause_code = HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH;\n+ break;\n+ }\n+ idx = i;\n+ }\n+ }\n+\n+ if (idx == not_found) {\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"%s: 0x%\" PRIx32 \", 0x%08\" PRIx32 \" => NOT FOUND\\n\",\n+ __func__, asid, VA);\n+ } else {\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"%s: 0x%\" PRIx32 \", 0x%08\" PRIx32 \" => %d\\n\",\n+ __func__, asid, VA, idx);\n+ }\n+\n+ return idx;\n+}\n+\n+/*\n+ * Return codes:\n+ * 0 or positive index of match\n+ * -1 multiple matches\n+ * -2 no match\n+ */\n+int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry,\n+ uint64_t index)\n+{\n+ int matches = 0;\n+ int last_match = 0;\n+\n+ for (uint32_t i = 0; i < tlb->num_entries; i++) {\n+ if (hex_tlb_is_match(entry, tlb->entries[i], false)) {\n+ matches++;\n+ last_match = i;\n+ }\n+ }\n+\n+ if (matches == 1) {\n+ return last_match;\n+ }\n+ if (matches == 0) {\n+ return -2;\n+ }\n+ return -1;\n+}\n+\n+void hexagon_tlb_dump(Monitor *mon, HexagonTLBState *tlb)\n+{\n+ for (uint32_t i = 0; i < tlb->num_entries; i++) {\n+ hexagon_tlb_dump_entry(mon, tlb->entries[i]);\n+ }\n+}\n+\n+uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb)\n+{\n+ return tlb->num_entries;\n+}\n+\n+/* QOM lifecycle */\n+\n+static void hexagon_tlb_init(Object *obj)\n+{\n+}\n+\n+static void hexagon_tlb_realize(DeviceState *dev, Error **errp)\n+{\n+ HexagonTLBState *s = HEXAGON_TLB(dev);\n+\n+ if (s->num_entries == 0 || s->num_entries > MAX_TLB_ENTRIES) {\n+ error_setg(errp, \"Invalid TLB num-entries: %\" PRIu32,\n+ s->num_entries);\n+ return;\n+ }\n+ s->entries = g_new0(uint64_t, s->num_entries);\n+}\n+\n+static void hexagon_tlb_unrealize(DeviceState *dev)\n+{\n+ HexagonTLBState *s = HEXAGON_TLB(dev);\n+ g_free(s->entries);\n+ s->entries = NULL;\n+}\n+\n+static void hexagon_tlb_reset_hold(Object *obj, ResetType type)\n+{\n+ HexagonTLBState *s = HEXAGON_TLB(obj);\n+ if (s->entries) {\n+ memset(s->entries, 0, sizeof(uint64_t) * s->num_entries);\n+ }\n+}\n+\n+static const VMStateDescription vmstate_hexagon_tlb = {\n+ .name = \"hexagon-tlb\",\n+ .version_id = 0,\n+ .minimum_version_id = 0,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT32(num_entries, HexagonTLBState),\n+ VMSTATE_VARRAY_UINT32_ALLOC(entries, HexagonTLBState, num_entries,\n+ 0, vmstate_info_uint64, uint64_t),\n+ VMSTATE_END_OF_LIST()\n+ },\n+};\n+\n+static const Property hexagon_tlb_properties[] = {\n+ DEFINE_PROP_UINT32(\"num-entries\", HexagonTLBState, num_entries,\n+ MAX_TLB_ENTRIES),\n+};\n+\n+static void hexagon_tlb_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n+\n+ dc->realize = hexagon_tlb_realize;\n+ dc->unrealize = hexagon_tlb_unrealize;\n+ rc->phases.hold = hexagon_tlb_reset_hold;\n+ dc->vmsd = &vmstate_hexagon_tlb;\n+ dc->user_creatable = false;\n+ device_class_set_props(dc, hexagon_tlb_properties);\n+}\n+\n+static const TypeInfo hexagon_tlb_info = {\n+ .name = TYPE_HEXAGON_TLB,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(HexagonTLBState),\n+ .instance_init = hexagon_tlb_init,\n+ .class_init = hexagon_tlb_class_init,\n+};\n+\n+static void hexagon_tlb_register_types(void)\n+{\n+ type_register_static(&hexagon_tlb_info);\n+}\n+\n+type_init(hexagon_tlb_register_types)\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex ab5bfb0ed0e..4da1b01fcd1 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -23,6 +23,7 @@\n #include \"qapi/error.h\"\n #include \"hw/core/qdev-properties.h\"\n #include \"fpu/softfloat-helpers.h\"\n+#include \"hw/hexagon/hexagon_tlb.h\"\n #include \"tcg/tcg.h\"\n #include \"exec/gdbstub.h\"\n #include \"accel/tcg/cpu-ops.h\"\n@@ -50,6 +51,8 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n }\n \n static const Property hexagon_cpu_properties[] = {\n+#if !defined(CONFIG_USER_ONLY)\n+#endif\n DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n qdev_prop_uint32, target_ulong),\n", "prefixes": [ "v6", "34/37" ] }