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GET /api/patches/2218627/?format=api
{ "id": 2218627, "url": "http://patchwork.ozlabs.org/api/patches/2218627/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-17-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-17-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:36", "name": "[v6,16/37] target/hexagon: Add new macro definitions for sysemu", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8ef8c63dfe99d05a0efe5f9965d5298e6299a3f0", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-17-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218627/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218627/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=pv4aU4i8;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=GEn3/2VS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfXzP5hCGeUDCzp\n Rc4Ii/C8HLOX5gjSU9AohNw8c474vWWPsjZtqliVdc0g6AisvWPhapZ12EKnDqPCM9vJ3+tgSsc\n +ncys/IfQVrVkgE38n+M8tga2+wzcnzPM2xnGoBO8LFKr16WFTKspGAmVkToU1b2y8xZUZPBkgI\n AZ+xU+1ahkjcMI/G3OAKdF2VkB9tIcMlEi4+lasNBJ7Y7Ysgfz2c9rL/rkZKbT0k66MfPvi5oNm\n yRWFHFTUKD/jYKOUpamu6jGoo5afg9+wRGhRA3GeRTrrQJtGJQSdDnqbNACrKuCJrNAmJjkVDkt\n g9Mz2ttn3gEKycQLR59M4s1rybJp/JTY7TiJczBEu42Uc26QqgeNZgeUblVrPsyE16QZo2gCMB2\n jwA2ePfp4+eCyd0167u3rR3xBqehqDGlSl7NC3Y7Zrx8zTDz5Zq+0FTcd0nskREkWbIjTpvOk14\n Bcii1x9tdvQHhos8yAA==", "X-Authority-Analysis": "v=2.4 cv=QJJlhwLL c=1 sm=1 tr=0 ts=69cd39a9 cx=c_pps\n a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22\n a=COk6AnOGAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=VoFV4bgUeqxKQXHmsMYA:9\n a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-GUID": "msjf-4FBO6OSwQnHqt5NdUg4iyjaB_5A", "X-Proofpoint-ORIG-GUID": "msjf-4FBO6OSwQnHqt5NdUg4iyjaB_5A", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-01_04,2026-04-01_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 impostorscore=0 clxscore=1015 bulkscore=0 priorityscore=1501\n phishscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nAlso: add nop TCG overrides for break, unpause, fetchbo; add TCG\noverride for dczeroa_nt (non-temporal variant of dczeroa).\n\nbreak: this hardware breakpoint instruction is used with the in-silicon\ndebugger feature, this is not modeled.\n\nunpause: this instruction is used to resume hardware threads that are\nstalled by pause instructions. pause is modeled as a nop, or in RR\nmode as an EXCP_YIELD. This instruction is safe to ignore.\n\nSince prefetch functions are not modeled, fetchbo is safe to ignore.\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/gen_tcg.h | 9 ++\n target/hexagon/macros.h | 25 +++-\n target/hexagon/sys_macros.h | 237 ++++++++++++++++++++++++++++++++++++\n target/hexagon/op_helper.c | 4 +\n 4 files changed, 274 insertions(+), 1 deletion(-)\n create mode 100644 target/hexagon/sys_macros.h", "diff": "diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h\nindex 1e0cc3b29a8..86d74ed259c 100644\n--- a/target/hexagon/gen_tcg.h\n+++ b/target/hexagon/gen_tcg.h\n@@ -488,6 +488,7 @@\n \n /* dczeroa clears the 32 byte cache line at the address given */\n #define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE\n+#define fGEN_TCG_Y2_dczeroa_nt(SHORTCODE) SHORTCODE\n \n /* In linux-user mode, these are not modelled, suppress compiler warning */\n #define fGEN_TCG_Y2_dcinva(SHORTCODE) \\\n@@ -1112,6 +1113,9 @@\n RdV, tcg_constant_tl(0)); \\\n } while (0)\n \n+#define fGEN_TCG_Y2_break(SHORTCODE)\n+#define fGEN_TCG_J2_unpause(SHORTCODE)\n+\n #define fGEN_TCG_J2_pause(SHORTCODE) \\\n do { \\\n uiV = uiV; \\\n@@ -1321,6 +1325,11 @@\n RsV = RsV; \\\n uiV = uiV; \\\n } while (0)\n+#define fGEN_TCG_Y2_dcfetchbo_nt(SHORTCODE) \\\n+ do { \\\n+ RsV = RsV; \\\n+ uiV = uiV; \\\n+ } while (0)\n \n #define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE\n #define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE\ndiff --git a/target/hexagon/macros.h b/target/hexagon/macros.h\nindex 6c2862a2320..e4bfea4923f 100644\n--- a/target/hexagon/macros.h\n+++ b/target/hexagon/macros.h\n@@ -631,8 +631,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)\n #define fCONSTLL(A) A##LL\n #define fECHO(A) (A)\n \n-#define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)\n+#ifdef CONFIG_USER_ONLY\n+#define fTRAP(TRAPTYPE, IMM) \\\n+ do { \\\n+ hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC); \\\n+ } while (0)\n+#endif\n+\n+#define fDO_TRACE(SREG)\n+#define fBREAK()\n+#define fUNPAUSE()\n #define fPAUSE(IMM)\n+#define fDCFETCH(REG)\n \n #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \\\n ((VAL) << reg_field_info[FIELD].offset)\n@@ -654,5 +664,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)\n #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \\\n STRBITNUM) /* Nothing */\n \n+#ifdef CONFIG_USER_ONLY\n+/*\n+ * This macro can only be true in guest mode.\n+ * In user mode, the 4 VIRTINSN's can't be reached\n+ */\n+#define fTRAP1_VIRTINSN(IMM) (false)\n+#define fVIRTINSN_SPSWAP(IMM, REG) g_assert_not_reached()\n+#define fVIRTINSN_GETIE(IMM, REG) g_assert_not_reached()\n+#define fVIRTINSN_SETIE(IMM, REG) g_assert_not_reached()\n+#define fVIRTINSN_RTE(IMM, REG) g_assert_not_reached()\n+#endif\n+\n+#define fPREDUSE_TIMING()\n \n #endif\ndiff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h\nnew file mode 100644\nindex 00000000000..f497d55bb81\n--- /dev/null\n+++ b/target/hexagon/sys_macros.h\n@@ -0,0 +1,237 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXAGON_SYS_MACROS_H\n+#define HEXAGON_SYS_MACROS_H\n+\n+/*\n+ * Macro definitions for Hexagon system mode\n+ */\n+\n+#ifndef CONFIG_USER_ONLY\n+\n+#ifdef QEMU_GENERATE\n+#define GET_SSR_FIELD(RES, FIELD) \\\n+ GET_FIELD(RES, FIELD, hex_t_sreg[HEX_SREG_SSR])\n+#else\n+\n+#define GET_SSR_FIELD(FIELD, REGIN) \\\n+ (uint32_t)GET_FIELD(FIELD, REGIN)\n+#define GET_SYSCFG_FIELD(FIELD, REGIN) \\\n+ (uint32_t)GET_FIELD(FIELD, REGIN)\n+#define SET_SYSTEM_FIELD(ENV, REG, FIELD, VAL) \\\n+ do { \\\n+ HexagonCPU *_sf_cpu = env_archcpu(ENV); \\\n+ uint32_t regval; \\\n+ if ((REG) < HEX_SREG_GLB_START) { \\\n+ regval = (ENV)->t_sreg[(REG)]; \\\n+ } else { \\\n+ regval = _sf_cpu->globalregs ? \\\n+ hexagon_globalreg_read(_sf_cpu->globalregs, (REG), \\\n+ (ENV)->threadId) : 0; \\\n+ } \\\n+ fINSERT_BITS(regval, reg_field_info[FIELD].width, \\\n+ reg_field_info[FIELD].offset, (VAL)); \\\n+ if ((REG) < HEX_SREG_GLB_START) { \\\n+ (ENV)->t_sreg[(REG)] = regval; \\\n+ } else if (_sf_cpu->globalregs) { \\\n+ hexagon_globalreg_write(_sf_cpu->globalregs, (REG), regval, \\\n+ (ENV)->threadId); \\\n+ } \\\n+ } while (0)\n+#define SET_SSR_FIELD(ENV, FIELD, VAL) \\\n+ SET_SYSTEM_FIELD(ENV, HEX_SREG_SSR, FIELD, VAL)\n+#define SET_SYSCFG_FIELD(ENV, FIELD, VAL) \\\n+ SET_SYSTEM_FIELD(ENV, HEX_SREG_SYSCFG, FIELD, VAL)\n+\n+#define CCR_FIELD_SET(ENV, FIELD) \\\n+ (!!GET_FIELD(FIELD, (ENV)->t_sreg[HEX_SREG_CCR]))\n+\n+/*\n+ * Direct-to-guest is not implemented yet, continuing would cause unexpected\n+ * behavior, so we abort.\n+ */\n+#define ASSERT_DIRECT_TO_GUEST_UNSET(ENV, EXCP) \\\n+ do { \\\n+ switch (EXCP) { \\\n+ case HEX_EVENT_TRAP0: \\\n+ g_assert(!CCR_FIELD_SET(ENV, CCR_GTE)); \\\n+ break; \\\n+ case HEX_EVENT_IMPRECISE: \\\n+ case HEX_EVENT_PRECISE: \\\n+ case HEX_EVENT_FPTRAP: \\\n+ g_assert(!CCR_FIELD_SET(ENV, CCR_GEE)); \\\n+ break; \\\n+ default: \\\n+ if ((EXCP) >= HEX_EVENT_INT0) { \\\n+ g_assert(!CCR_FIELD_SET(ENV, CCR_GIE)); \\\n+ } \\\n+ break; \\\n+ } \\\n+ } while (0)\n+#endif\n+\n+#define fREAD_ELR() (env->t_sreg[HEX_SREG_ELR])\n+\n+#define fLOAD_PHYS(NUM, SIZE, SIGN, SRC1, SRC2, DST) { \\\n+ const uintptr_t rs = ((unsigned long)(unsigned)(SRC1)) & 0x7ff; \\\n+ const uintptr_t rt = ((unsigned long)(unsigned)(SRC2)) << 11; \\\n+ const uintptr_t addr = rs + rt; \\\n+ cpu_physical_memory_read(addr, &DST, sizeof(uint32_t)); \\\n+}\n+\n+#define fPOW2_HELP_ROUNDUP(VAL) \\\n+ ((VAL) | \\\n+ ((VAL) >> 1) | \\\n+ ((VAL) >> 2) | \\\n+ ((VAL) >> 4) | \\\n+ ((VAL) >> 8) | \\\n+ ((VAL) >> 16))\n+#define fPOW2_ROUNDUP(VAL) (fPOW2_HELP_ROUNDUP((VAL) - 1) + 1)\n+\n+#define fTRAP(TRAPTYPE, IMM) \\\n+ register_trap_exception(env, TRAPTYPE, IMM, PC)\n+\n+#define fVIRTINSN_SPSWAP(IMM, REG)\n+#define fVIRTINSN_GETIE(IMM, REG) { REG = 0xdeafbeef; }\n+#define fVIRTINSN_SETIE(IMM, REG)\n+#define fVIRTINSN_RTE(IMM, REG)\n+#define fGRE_ENABLED() \\\n+ GET_FIELD(CCR_GRE, env->t_sreg[HEX_SREG_CCR])\n+#define fTRAP1_VIRTINSN(IMM) \\\n+ (fGRE_ENABLED() && \\\n+ (((IMM) == 1) || ((IMM) == 3) || ((IMM) == 4) || ((IMM) == 6)))\n+\n+/* Not modeled in qemu */\n+\n+#define MARK_LATE_PRED_WRITE(RNUM)\n+#define fICINVIDX(REG)\n+#define fICKILL()\n+#define fDCKILL()\n+#define fL2KILL()\n+#define fL2UNLOCK()\n+#define fL2CLEAN()\n+#define fL2CLEANINV()\n+#define fL2CLEANPA(REG)\n+#define fL2CLEANINVPA(REG)\n+#define fL2CLEANINVIDX(REG)\n+#define fL2CLEANIDX(REG)\n+#define fL2INVIDX(REG)\n+#define fL2TAGR(INDEX, DST, DSTREG)\n+#define fL2UNLOCKA(VA) ((void) VA)\n+#define fL2TAGW(INDEX, PART2)\n+#define fDCCLEANIDX(REG)\n+#define fDCCLEANINVIDX(REG)\n+\n+/* Always succeed: */\n+#define fL2LOCKA(EA, PDV, PDN) ((void) EA, PDV = 0xFF)\n+#define fCLEAR_RTE_EX() \\\n+ do { \\\n+ uint32_t tmp = env->t_sreg[HEX_SREG_SSR]; \\\n+ fINSERT_BITS(tmp, reg_field_info[SSR_EX].width, \\\n+ reg_field_info[SSR_EX].offset, 0); \\\n+ log_sreg_write(env, HEX_SREG_SSR, tmp, slot); \\\n+ } while (0)\n+\n+#define fDCINVIDX(REG)\n+#define fDCINVA(REG) do { REG = REG; } while (0) /* Nothing to do in qemu */\n+\n+#define fTLB_IDXMASK(INDEX) \\\n+ ((INDEX) & (fPOW2_ROUNDUP( \\\n+ fCAST4u(hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))) - 1))\n+\n+#define fTLB_NONPOW2WRAP(INDEX) \\\n+ (((INDEX) >= hexagon_tlb_get_num_entries(env_archcpu(env)->tlb)) ? \\\n+ ((INDEX) - hexagon_tlb_get_num_entries(env_archcpu(env)->tlb)) : \\\n+ (INDEX))\n+\n+\n+#define fTLBW(INDEX, VALUE) \\\n+ hex_tlbw(env, (INDEX), (VALUE))\n+#define fTLBW_EXTENDED(INDEX, VALUE) \\\n+ hex_tlbw(env, (INDEX), (VALUE))\n+#define fTLB_ENTRY_OVERLAP(VALUE) \\\n+ (hex_tlb_check_overlap(env, VALUE, -1) != -2)\n+#define fTLB_ENTRY_OVERLAP_IDX(VALUE) \\\n+ hex_tlb_check_overlap(env, VALUE, -1)\n+#define fTLBR(INDEX) \\\n+ hexagon_tlb_read(env_archcpu(env)->tlb, \\\n+ fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX)))\n+#define fTLBR_EXTENDED(INDEX) \\\n+ hexagon_tlb_read(env_archcpu(env)->tlb, \\\n+ fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX)))\n+#define fTLBP(TLBHI) \\\n+ hex_tlb_lookup(env, ((TLBHI) >> 12), ((TLBHI) << 12))\n+#define iic_flush_cache(p)\n+\n+#define fIN_DEBUG_MODE(TNUM) ({ \\\n+ HexagonCPU *_cpu = env_archcpu(env); \\\n+ uint32_t _isdbst = _cpu->globalregs ? \\\n+ hexagon_globalreg_read(_cpu->globalregs, \\\n+ HEX_SREG_ISDBST, env->threadId) : 0; \\\n+ (GET_FIELD(ISDBST_DEBUGMODE, _isdbst) \\\n+ & (0x1 << (TNUM))) != 0; })\n+\n+#define fIN_DEBUG_MODE_NO_ISDB(TNUM) false\n+#define fIN_DEBUG_MODE_WARN(TNUM) false\n+\n+#ifdef QEMU_GENERATE\n+\n+/*\n+ * Read tags back as zero for now:\n+ *\n+ * tag value in RD[31:10] for 32k, RD[31:9] for 16k\n+ */\n+#define fICTAGR(RS, RD, RD2) \\\n+ do { \\\n+ RD = ctx->zero; \\\n+ } while (0)\n+#define fICTAGW(RS, RD)\n+#define fICDATAR(RS, RD) \\\n+ do { \\\n+ RD = ctx->zero; \\\n+ } while (0)\n+#define fICDATAW(RS, RD)\n+\n+#define fDCTAGW(RS, RT)\n+/* tag: RD[23:0], state: RD[30:29] */\n+#define fDCTAGR(INDEX, DST, DST_REG_NUM) \\\n+ do { \\\n+ DST = ctx->zero; \\\n+ } while (0)\n+#else\n+\n+/*\n+ * Read tags back as zero for now:\n+ *\n+ * tag value in RD[31:10] for 32k, RD[31:9] for 16k\n+ */\n+#define fICTAGR(RS, RD, RD2) \\\n+ do { \\\n+ RD = 0x00; \\\n+ } while (0)\n+#define fICTAGW(RS, RD)\n+#define fICDATAR(RS, RD) \\\n+ do { \\\n+ RD = 0x00; \\\n+ } while (0)\n+#define fICDATAW(RS, RD)\n+\n+#define fDCTAGW(RS, RT)\n+/* tag: RD[23:0], state: RD[30:29] */\n+#define fDCTAGR(INDEX, DST, DST_REG_NUM) \\\n+ do { \\\n+ DST = 0; \\\n+ } while (0)\n+#endif\n+\n+#else\n+#define ASSERT_DIRECT_TO_GUEST_UNSET(ENV, EXCP) do { } while (0)\n+#endif\n+\n+#define NUM_TLB_REGS(x) (hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))\n+\n+#endif\ndiff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c\nindex 368391bb846..53898db815b 100644\n--- a/target/hexagon/op_helper.c\n+++ b/target/hexagon/op_helper.c\n@@ -24,6 +24,7 @@\n #include \"cpu.h\"\n #include \"internal.h\"\n #include \"macros.h\"\n+#include \"sys_macros.h\"\n #include \"arch.h\"\n #include \"hex_arch_types.h\"\n #include \"fma_emu.h\"\n@@ -31,6 +32,9 @@\n #include \"mmvec/macros.h\"\n #include \"op_helper.h\"\n #include \"translate.h\"\n+#ifndef CONFIG_USER_ONLY\n+#include \"hexswi.h\"\n+#endif\n \n #define SF_BIAS 127\n #define SF_MANTBITS 23\n", "prefixes": [ "v6", "16/37" ] }