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GET /api/patches/2218623/?format=api
{ "id": 2218623, "url": "http://patchwork.ozlabs.org/api/patches/2218623/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-36-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401152657.314902-36-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T15:26:55", "name": "[v6,35/37] target/hexagon: Add stubs for modify_ssr/get_exe_mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "881121cf4c35f67187463b1f92e5a4507904c143", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401152657.314902-36-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 498350, "url": "http://patchwork.ozlabs.org/api/series/498350/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498350", "date": "2026-04-01T15:26:45", "name": "Hexagon system emulation - Part 1/3", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498350/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218623/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218623/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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stubs for\n modify_ssr/get_exe_mode", "Date": "Wed, 1 Apr 2026 08:26:55 -0700", "Message-Id": "<20260401152657.314902-36-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "References": "<20260401152657.314902-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDE0NCBTYWx0ZWRfX2+jgdIrdQg28\n aLkySTFgTup2KQvQeDpvuGPwiOUOH4A4ZNpLaTMnVs92sVyhrO3kz5fRv5QmIZivOxD9YqjJC3C\n umC84k3yphFaXMC7Y21bg8CBY42AZ6Xnx7eBam0J3VVwpEkUFB9rDqzaTuZ1G7J6YOzfnp3Q1Cd\n iE5xrSH+ioN4XgrebPCgQv1g9PdAwxblkwzTKy4nL+hl1Hoj6eEEv6GDw21alhe3LDVK/rR21E5\n fI5RhAQQJQwO3ut7YSDYyDw4qpcCm/rarhQyUCsdWYaIYBd8LXYX6yyKCwweqg7XcpvH04IgfVD\n mV/HmtwRlMHNld5gc4TSE7Ltfj/6OH0v6jzV+4ELZ0TmMIslO4cdpDqzfGCVY1V3nwh0filfHHS\n tmzokAi8C8vWP/Wwm+p0PnAnjaYO29wjlkl1SLVpV8mCTtdifaqKvVZh/fghiG/1N8QXuJqbLzD\n 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reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010144", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=1, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add hex_mmu.[ch], cpu mode helpers, and additional includes/stubs\nthat integrate the TLB device with the CPU model.\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu-param.h | 4 +\n target/hexagon/cpu.h | 17 +++\n target/hexagon/hex_mmu.h | 26 ++++\n target/hexagon/internal.h | 9 ++\n target/hexagon/sys_macros.h | 3 +\n target/hexagon/cpu.c | 24 ++++\n target/hexagon/hex_mmu.c | 268 ++++++++++++++++++++++++++++++++++++\n target/hexagon/translate.c | 2 +-\n 8 files changed, 352 insertions(+), 1 deletion(-)\n create mode 100644 target/hexagon/hex_mmu.h\n create mode 100644 target/hexagon/hex_mmu.c", "diff": "diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h\nindex 1f0f22a7968..9eae7d2361c 100644\n--- a/target/hexagon/cpu-param.h\n+++ b/target/hexagon/cpu-param.h\n@@ -18,7 +18,11 @@\n #ifndef HEXAGON_CPU_PARAM_H\n #define HEXAGON_CPU_PARAM_H\n \n+#ifdef CONFIG_USER_ONLY\n #define TARGET_PAGE_BITS 16 /* 64K pages */\n+#else\n+#define TARGET_PAGE_BITS 12 /* 4K pages */\n+#endif\n \n #define TARGET_VIRT_ADDR_SPACE_BITS 32\n \ndiff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h\nindex 15dd99d2155..c4fac9c2d38 100644\n--- a/target/hexagon/cpu.h\n+++ b/target/hexagon/cpu.h\n@@ -41,6 +41,9 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegState;\n #error \"Hexagon does not support system emulation\"\n #endif\n \n+#ifndef CONFIG_USER_ONLY\n+#endif\n+\n #define NUM_PREGS 4\n #define TOTAL_PER_THREAD_REGS 64\n \n@@ -54,6 +57,8 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegState;\n #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU\n #ifndef CONFIG_USER_ONLY\n #define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0\n+#define CPU_INTERRUPT_K0_UNLOCK CPU_INTERRUPT_TGT_INT_1\n+#define CPU_INTERRUPT_TLB_UNLOCK CPU_INTERRUPT_TGT_INT_2\n \n #define HEX_CPU_MODE_USER 1\n #define HEX_CPU_MODE_GUEST 2\n@@ -70,6 +75,12 @@ typedef struct HexagonGlobalRegState HexagonGlobalRegState;\n #define MMU_GUEST_IDX 1\n #define MMU_KERNEL_IDX 2\n \n+typedef enum {\n+ HEX_LOCK_UNLOCKED = 0,\n+ HEX_LOCK_WAITING = 1,\n+ HEX_LOCK_OWNER = 2,\n+ HEX_LOCK_QUEUED = 3\n+} hex_lock_state_t;\n #endif\n \n \n@@ -131,6 +142,10 @@ typedef struct CPUArchState {\n \n /* This alias of CPUState.cpu_index is used by imported sources: */\n uint32_t threadId;\n+ hex_lock_state_t tlb_lock_state;\n+ hex_lock_state_t k0_lock_state;\n+ uint32_t tlb_lock_count;\n+ uint32_t k0_lock_count;\n uint64_t t_cycle_count;\n #endif\n uint32_t next_PC;\n@@ -181,12 +196,14 @@ struct ArchCPU {\n bool short_circuit;\n #ifndef CONFIG_USER_ONLY\n HexagonTLBState *tlb;\n+ uint32_t htid;\n #endif\n };\n \n #include \"cpu_bits.h\"\n \n FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)\n+FIELD(TB_FLAGS, MMU_INDEX, 1, 3)\n FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1)\n \n G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,\ndiff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h\nnew file mode 100644\nindex 00000000000..4f556c715a9\n--- /dev/null\n+++ b/target/hexagon/hex_mmu.h\n@@ -0,0 +1,26 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXAGON_MMU_H\n+#define HEXAGON_MMU_H\n+\n+#include \"cpu.h\"\n+#include \"monitor/monitor.h\"\n+\n+extern void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value);\n+extern uint32_t hex_tlb_lookup(CPUHexagonState *env, uint32_t ssr, uint32_t VA);\n+extern void hex_mmu_on(CPUHexagonState *env);\n+extern void hex_mmu_off(CPUHexagonState *env);\n+extern void hex_mmu_mode_change(CPUHexagonState *env);\n+extern bool hex_tlb_find_match(CPUHexagonState *env, uint32_t VA,\n+ MMUAccessType access_type, hwaddr *PA, int *prot,\n+ uint64_t *size, int32_t *excp, int mmu_idx);\n+extern int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry,\n+ uint64_t index);\n+extern void hex_tlb_lock(CPUHexagonState *env);\n+extern void hex_tlb_unlock(CPUHexagonState *env);\n+void dump_mmu(Monitor *mon, CPUHexagonState *env);\n+#endif\ndiff --git a/target/hexagon/internal.h b/target/hexagon/internal.h\nindex 33d73ed18d1..4338914efb5 100644\n--- a/target/hexagon/internal.h\n+++ b/target/hexagon/internal.h\n@@ -36,6 +36,15 @@ void G_NORETURN do_raise_exception(CPUHexagonState *env,\n uint32_t PC,\n uintptr_t retaddr);\n \n+#define hexagon_cpu_mmu_enabled(env) ({ \\\n+ HexagonCPU *cpu = env_archcpu(env); \\\n+ cpu->globalregs ? \\\n+ GET_SYSCFG_FIELD(SYSCFG_MMUEN, \\\n+ hexagon_globalreg_read(cpu->globalregs, \\\n+ HEX_SREG_SYSCFG, (env)->threadId)) : \\\n+ 0; \\\n+})\n+\n #ifndef CONFIG_USER_ONLY\n extern const VMStateDescription vmstate_hexagon_cpu;\n #endif\ndiff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h\nindex f497d55bb81..364fcde7383 100644\n--- a/target/hexagon/sys_macros.h\n+++ b/target/hexagon/sys_macros.h\n@@ -139,6 +139,9 @@\n #define fDCINVIDX(REG)\n #define fDCINVA(REG) do { REG = REG; } while (0) /* Nothing to do in qemu */\n \n+#define fSET_TLB_LOCK() hex_tlb_lock(env);\n+#define fCLEAR_TLB_LOCK() hex_tlb_unlock(env);\n+\n #define fTLB_IDXMASK(INDEX) \\\n ((INDEX) & (fPOW2_ROUNDUP( \\\n fCAST4u(hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))) - 1))\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 4da1b01fcd1..4e9c65f785a 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -27,6 +27,13 @@\n #include \"tcg/tcg.h\"\n #include \"exec/gdbstub.h\"\n #include \"accel/tcg/cpu-ops.h\"\n+#include \"cpu_helper.h\"\n+#include \"hex_mmu.h\"\n+\n+#ifndef CONFIG_USER_ONLY\n+#include \"sys_macros.h\"\n+#include \"accel/tcg/cpu-ldst.h\"\n+#endif\n \n static void hexagon_v66_cpu_init(Object *obj) { }\n static void hexagon_v67_cpu_init(Object *obj) { }\n@@ -52,6 +59,7 @@ static ObjectClass *hexagon_cpu_class_by_name(const char *cpu_model)\n \n static const Property hexagon_cpu_properties[] = {\n #if !defined(CONFIG_USER_ONLY)\n+ DEFINE_PROP_UINT32(\"htid\", HexagonCPU, htid, 0),\n #endif\n DEFINE_PROP_BOOL(\"lldb-compat\", HexagonCPU, lldb_compat, false),\n DEFINE_PROP_UNSIGNED(\"lldb-stack-adjust\", HexagonCPU, lldb_stack_adjust, 0,\n@@ -279,7 +287,11 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)\n }\n \n #ifndef CONFIG_USER_ONLY\n+ hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX,\n+ cpu_mmu_index(env_cpu(env), false));\n hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1);\n+#else\n+ hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX);\n #endif\n \n return (TCGTBCPUState){ .pc = pc, .flags = hex_flags };\n@@ -299,11 +311,15 @@ static void hexagon_restore_state_to_opc(CPUState *cs,\n cpu_env(cs)->gpr[HEX_REG_PC] = data[0];\n }\n \n+\n static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n {\n CPUState *cs = CPU(obj);\n HexagonCPUClass *mcc = HEXAGON_CPU_GET_CLASS(obj);\n CPUHexagonState *env = cpu_env(cs);\n+#ifndef CONFIG_USER_ONLY\n+ HexagonCPU *cpu = HEXAGON_CPU(cs);\n+#endif\n \n if (mcc->parent_phases.hold) {\n mcc->parent_phases.hold(obj, type);\n@@ -317,7 +333,14 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)\n memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS);\n memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS);\n env->wait_next_pc = 0;\n+ env->tlb_lock_state = HEX_LOCK_UNLOCKED;\n+ env->k0_lock_state = HEX_LOCK_UNLOCKED;\n+ env->tlb_lock_count = 0;\n+ env->k0_lock_count = 0;\n env->next_PC = 0;\n+\n+ env->t_sreg[HEX_SREG_HTID] = cpu->htid;\n+ env->threadId = cpu->htid;\n #endif\n env->cause_code = HEX_EVENT_NONE;\n }\n@@ -346,6 +369,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)\n gdb_find_static_feature(\"hexagon-hvx.xml\"));\n \n qemu_init_vcpu(cs);\n+\n cpu_reset(cs);\n mcc->parent_realize(dev, errp);\n }\ndiff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c\nnew file mode 100644\nindex 00000000000..c921e82b377\n--- /dev/null\n+++ b/target/hexagon/hex_mmu.c\n@@ -0,0 +1,268 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"qemu/qemu-print.h\"\n+#include \"cpu.h\"\n+#include \"system/cpus.h\"\n+#include \"internal.h\"\n+#include \"exec/cpu-interrupt.h\"\n+#include \"cpu_helper.h\"\n+#include \"exec/cputlb.h\"\n+#include \"hex_mmu.h\"\n+#include \"macros.h\"\n+#include \"sys_macros.h\"\n+#include \"hw/hexagon/hexagon_tlb.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n+\n+static inline void hex_log_tlbw(uint32_t index, uint64_t entry)\n+{\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"tlbw[%03\" PRIu32 \"]: 0x%016\" PRIx64 \"\\n\",\n+ index, entry);\n+}\n+\n+void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value)\n+{\n+ uint32_t myidx = fTLB_NONPOW2WRAP(fTLB_IDXMASK(index));\n+ HexagonTLBState *tlb = env_archcpu(env)->tlb;\n+ uint64_t old_entry = hexagon_tlb_read(tlb, myidx);\n+\n+ bool old_entry_valid = extract64(old_entry, 63, 1);\n+ if (old_entry_valid && hexagon_cpu_mmu_enabled(env)) {\n+ CPUState *cs = env_cpu(env);\n+ tlb_flush(cs);\n+ }\n+ hexagon_tlb_write(tlb, myidx, value);\n+ hex_log_tlbw(myidx, value);\n+}\n+\n+void hex_mmu_on(CPUHexagonState *env)\n+{\n+ CPUState *cs = env_cpu(env);\n+ qemu_log_mask(CPU_LOG_MMU, \"Hexagon MMU turned on!\\n\");\n+ tlb_flush(cs);\n+}\n+\n+void hex_mmu_off(CPUHexagonState *env)\n+{\n+ CPUState *cs = env_cpu(env);\n+ qemu_log_mask(CPU_LOG_MMU, \"Hexagon MMU turned off!\\n\");\n+ tlb_flush(cs);\n+}\n+\n+void hex_mmu_mode_change(CPUHexagonState *env)\n+{\n+ qemu_log_mask(CPU_LOG_MMU, \"Hexagon mode change!\\n\");\n+ CPUState *cs = env_cpu(env);\n+ tlb_flush(cs);\n+}\n+\n+bool hex_tlb_find_match(CPUHexagonState *env, uint32_t VA,\n+ MMUAccessType access_type, hwaddr *PA, int *prot,\n+ uint64_t *size, int32_t *excp, int mmu_idx)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t ssr = env->t_sreg[HEX_SREG_SSR];\n+ uint8_t asid = GET_SSR_FIELD(SSR_ASID, ssr);\n+ int cause_code = 0;\n+\n+ bool found = hexagon_tlb_find_match(cpu->tlb, asid, VA, access_type,\n+ PA, prot, size, excp, &cause_code,\n+ mmu_idx);\n+ if (cause_code) {\n+ env->cause_code = cause_code;\n+ }\n+ return found;\n+}\n+\n+/* Called from tlbp instruction */\n+uint32_t hex_tlb_lookup(CPUHexagonState *env, uint32_t ssr, uint32_t VA)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint8_t asid = GET_SSR_FIELD(SSR_ASID, ssr);\n+ int cause_code = 0;\n+\n+ uint32_t result = hexagon_tlb_lookup(cpu->tlb, asid, VA, &cause_code);\n+ if (cause_code) {\n+ env->cause_code = cause_code;\n+ }\n+ return result;\n+}\n+\n+/*\n+ * Return codes:\n+ * 0 or positive index of match\n+ * -1 multiple matches\n+ * -2 no match\n+ */\n+int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry, uint64_t index)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ return hexagon_tlb_check_overlap(cpu->tlb, entry, index);\n+}\n+\n+void dump_mmu(Monitor *mon, CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ hexagon_tlb_dump(mon, cpu->tlb);\n+}\n+\n+static inline void print_thread(const char *str, CPUState *cs)\n+{\n+ g_assert(bql_locked());\n+ CPUHexagonState *thread = cpu_env(cs);\n+ bool is_stopped = cpu_is_stopped(cs);\n+ int exe_mode = get_exe_mode(thread);\n+ hex_lock_state_t lock_state = thread->tlb_lock_state;\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"%s: threadId = %\" PRIu32 \": %s, exe_mode = %s, tlb_lock_state = %s\\n\",\n+ str,\n+ thread->threadId,\n+ is_stopped ? \"stopped\" : \"running\",\n+ exe_mode == HEX_EXE_MODE_OFF ? \"off\" :\n+ exe_mode == HEX_EXE_MODE_RUN ? \"run\" :\n+ exe_mode == HEX_EXE_MODE_WAIT ? \"wait\" :\n+ exe_mode == HEX_EXE_MODE_DEBUG ? \"debug\" :\n+ \"unknown\",\n+ lock_state == HEX_LOCK_UNLOCKED ? \"unlocked\" :\n+ lock_state == HEX_LOCK_WAITING ? \"waiting\" :\n+ lock_state == HEX_LOCK_OWNER ? \"owner\" :\n+ \"unknown\");\n+}\n+\n+static inline void print_thread_states(const char *str)\n+{\n+ CPUState *cs;\n+ CPU_FOREACH(cs) {\n+ print_thread(str, cs);\n+ }\n+}\n+\n+void hex_tlb_lock(CPUHexagonState *env)\n+{\n+ qemu_log_mask(CPU_LOG_MMU, \"hex_tlb_lock: \" TARGET_FMT_ld \"\\n\",\n+ env->threadId);\n+ BQL_LOCK_GUARD();\n+ g_assert((env->tlb_lock_count == 0) || (env->tlb_lock_count == 1));\n+\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t syscfg = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG,\n+ env->threadId) : 0;\n+ uint8_t tlb_lock = GET_SYSCFG_FIELD(SYSCFG_TLBLOCK, syscfg);\n+ if (tlb_lock) {\n+ if (env->tlb_lock_state == HEX_LOCK_QUEUED) {\n+ env->next_PC += 4;\n+ env->tlb_lock_count++;\n+ env->tlb_lock_state = HEX_LOCK_OWNER;\n+ SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 1);\n+ return;\n+ }\n+ if (env->tlb_lock_state == HEX_LOCK_OWNER) {\n+ qemu_log_mask(CPU_LOG_MMU | LOG_GUEST_ERROR,\n+ \"Double tlblock at PC: 0x%\" PRIx32 \", thread may hang\\n\",\n+ env->next_PC);\n+ env->next_PC += 4;\n+ CPUState *cs = env_cpu(env);\n+ cpu_interrupt(cs, CPU_INTERRUPT_HALT);\n+ return;\n+ }\n+ env->tlb_lock_state = HEX_LOCK_WAITING;\n+ CPUState *cs = env_cpu(env);\n+ cpu_interrupt(cs, CPU_INTERRUPT_HALT);\n+ } else {\n+ env->next_PC += 4;\n+ env->tlb_lock_count++;\n+ env->tlb_lock_state = HEX_LOCK_OWNER;\n+ SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 1);\n+ }\n+\n+ if (qemu_loglevel_mask(CPU_LOG_MMU)) {\n+ qemu_log_mask(CPU_LOG_MMU, \"Threads after hex_tlb_lock:\\n\");\n+ print_thread_states(\"\\tThread\");\n+ }\n+}\n+\n+void hex_tlb_unlock(CPUHexagonState *env)\n+{\n+ BQL_LOCK_GUARD();\n+ g_assert((env->tlb_lock_count == 0) || (env->tlb_lock_count == 1));\n+\n+ /* Nothing to do if the TLB isn't locked by this thread */\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t syscfg = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG,\n+ env->threadId) : 0;\n+ uint8_t tlb_lock = GET_SYSCFG_FIELD(SYSCFG_TLBLOCK, syscfg);\n+ if ((tlb_lock == 0) ||\n+ (env->tlb_lock_state != HEX_LOCK_OWNER)) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"thread %\" PRIu32 \" attempted to tlbunlock without having the \"\n+ \"lock, tlb_lock state = %d\\n\",\n+ env->threadId, env->tlb_lock_state);\n+ g_assert(env->tlb_lock_state != HEX_LOCK_WAITING);\n+ return;\n+ }\n+\n+ env->tlb_lock_count--;\n+ env->tlb_lock_state = HEX_LOCK_UNLOCKED;\n+ SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 0);\n+\n+ /* Look for a thread to unlock */\n+ unsigned int this_threadId = env->threadId;\n+ CPUHexagonState *unlock_thread = NULL;\n+ CPUState *cs;\n+ CPU_FOREACH(cs) {\n+ CPUHexagonState *thread = cpu_env(cs);\n+\n+ /*\n+ * The hardware implements round-robin fairness, so we look for threads\n+ * starting at env->threadId + 1 and incrementing modulo the number of\n+ * threads.\n+ *\n+ * To implement this, we check if thread is a earlier in the modulo\n+ * sequence than unlock_thread.\n+ * if unlock thread is higher than this thread\n+ * thread must be between this thread and unlock_thread\n+ * else\n+ * thread higher than this thread is ahead of unlock_thread\n+ * thread must be lower then unlock thread\n+ */\n+ if (thread->tlb_lock_state == HEX_LOCK_WAITING) {\n+ if (!unlock_thread) {\n+ unlock_thread = thread;\n+ } else if (unlock_thread->threadId > this_threadId) {\n+ if (this_threadId < thread->threadId &&\n+ thread->threadId < unlock_thread->threadId) {\n+ unlock_thread = thread;\n+ }\n+ } else {\n+ if (thread->threadId > this_threadId) {\n+ unlock_thread = thread;\n+ }\n+ if (thread->threadId < unlock_thread->threadId) {\n+ unlock_thread = thread;\n+ }\n+ }\n+ }\n+ }\n+ if (unlock_thread) {\n+ cs = env_cpu(unlock_thread);\n+ print_thread(\"\\tWaiting thread found\", cs);\n+ unlock_thread->tlb_lock_state = HEX_LOCK_QUEUED;\n+ SET_SYSCFG_FIELD(unlock_thread, SYSCFG_TLBLOCK, 1);\n+ cpu_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK);\n+ }\n+\n+ if (qemu_loglevel_mask(CPU_LOG_MMU)) {\n+ qemu_log_mask(CPU_LOG_MMU, \"Threads after hex_tlb_unlock:\\n\");\n+ print_thread_states(\"\\tThread\");\n+ }\n+\n+}\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 91dff442c80..07829063868 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -1005,7 +1005,7 @@ static void hexagon_tr_init_disas_context(DisasContextBase *dcbase,\n HexagonCPU *hex_cpu = env_archcpu(cpu_env(cs));\n uint32_t hex_flags = dcbase->tb->flags;\n \n- ctx->mem_idx = MMU_USER_IDX;\n+ ctx->mem_idx = FIELD_EX32(hex_flags, TB_FLAGS, MMU_INDEX);\n ctx->num_packets = 0;\n ctx->num_insns = 0;\n ctx->num_hvx_insns = 0;\n", "prefixes": [ "v6", "35/37" ] }