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GET /api/patches/2218617/?format=api
{ "id": 2218617, "url": "http://patchwork.ozlabs.org/api/patches/2218617/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401144503.80510-2-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401144503.80510-2-philmd@linaro.org>", "list_archive_url": null, "date": "2026-04-01T14:45:01", "name": "[PATCH-for-11.1,1/2] target/mips: Expand TCGv type as 32-bit for XBurst MXU", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "243a57c50676ff5182f8f1405650ed19fa495cb8", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401144503.80510-2-philmd@linaro.org/mbox/", "series": [ { "id": 498345, "url": "http://patchwork.ozlabs.org/api/series/498345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498345", "date": "2026-04-01T14:45:00", "name": "target/mips: Expand TCGv for fixed wordsize extensions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218617/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218617/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Xi91Q6jW;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32d;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The MXU extension is only built as 32-bit, so TCGv expands\nto TCGv_i32. Use the latter which is more explicit.\n\nIn gen_mxu_s32madd_sub() directly expand:\n\n - tcg_gen_ext[u]_tl_i64 -> tcg_gen_ext[u]_i32_i64\n - tcg_gen_concat_tl_i64 -> tcg_gen_concat_i32_i64\n\nthe rest being mechanical changes.\n\nCc: Siarhei Volkau <lis8215@gmail.com>\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/mxu_translate.c | 1954 +++++++++++++++----------------\n 1 file changed, 977 insertions(+), 977 deletions(-)", "diff": "diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c\nindex 35ebb0397da..7961b073144 100644\n--- a/target/mips/tcg/mxu_translate.c\n+++ b/target/mips/tcg/mxu_translate.c\n@@ -606,8 +606,8 @@ enum {\n #define MXU_OPTN3_PTN7 7\n \n /* MXU registers */\n-static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];\n-static TCGv mxu_CR;\n+static TCGv_i32 mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];\n+static TCGv_i32 mxu_CR;\n \n static const char mxuregnames[NUMBER_OF_MXU_REGISTERS][4] = {\n \"XR1\", \"XR2\", \"XR3\", \"XR4\", \"XR5\", \"XR6\", \"XR7\", \"XR8\",\n@@ -628,42 +628,42 @@ void mxu_translate_init(void)\n }\n \n /* MXU General purpose registers moves. */\n-static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg)\n+static inline void gen_load_mxu_gpr(TCGv_i32 t, unsigned int reg)\n {\n if (reg == 0) {\n- tcg_gen_movi_tl(t, 0);\n+ tcg_gen_movi_i32(t, 0);\n } else if (reg <= 15) {\n- tcg_gen_mov_tl(t, mxu_gpr[reg - 1]);\n+ tcg_gen_mov_i32(t, mxu_gpr[reg - 1]);\n }\n }\n \n-static inline void gen_store_mxu_gpr(TCGv t, unsigned int reg)\n+static inline void gen_store_mxu_gpr(TCGv_i32 t, unsigned int reg)\n {\n if (reg > 0 && reg <= 15) {\n- tcg_gen_mov_tl(mxu_gpr[reg - 1], t);\n+ tcg_gen_mov_i32(mxu_gpr[reg - 1], t);\n }\n }\n \n-static inline void gen_extract_mxu_gpr(TCGv t, unsigned int reg,\n+static inline void gen_extract_mxu_gpr(TCGv_i32 t, unsigned int reg,\n unsigned int ofs, unsigned int len)\n {\n if (reg == 0) {\n- tcg_gen_movi_tl(t, 0);\n+ tcg_gen_movi_i32(t, 0);\n } else if (reg <= 15) {\n- tcg_gen_extract_tl(t, mxu_gpr[reg - 1], ofs, len);\n+ tcg_gen_extract_i32(t, mxu_gpr[reg - 1], ofs, len);\n }\n }\n \n /* MXU control register moves. */\n-static inline void gen_load_mxu_cr(TCGv t)\n+static inline void gen_load_mxu_cr(TCGv_i32 t)\n {\n- tcg_gen_mov_tl(t, mxu_CR);\n+ tcg_gen_mov_i32(t, mxu_CR);\n }\n \n-static inline void gen_store_mxu_cr(TCGv t)\n+static inline void gen_store_mxu_cr(TCGv_i32 t)\n {\n /* TODO: Add handling of RW rules for MXU_CR. */\n- tcg_gen_mov_tl(mxu_CR, t);\n+ tcg_gen_mov_i32(mxu_CR, t);\n }\n \n /*\n@@ -671,10 +671,10 @@ static inline void gen_store_mxu_cr(TCGv t)\n */\n static void gen_mxu_s32i2m(DisasContext *ctx)\n {\n- TCGv t0;\n+ TCGv_i32 t0;\n uint32_t XRa, Rb;\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 5);\n Rb = extract32(ctx->opcode, 16, 5);\n@@ -692,10 +692,10 @@ static void gen_mxu_s32i2m(DisasContext *ctx)\n */\n static void gen_mxu_s32m2i(DisasContext *ctx)\n {\n- TCGv t0;\n+ TCGv_i32 t0;\n uint32_t XRa, Rb;\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 5);\n Rb = extract32(ctx->opcode, 16, 5);\n@@ -717,11 +717,11 @@ static void gen_mxu_s32m2i(DisasContext *ctx)\n */\n static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, s8, optn3;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n s8 = extract32(ctx->opcode, 10, 8);\n@@ -729,7 +729,7 @@ static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)\n Rb = extract32(ctx->opcode, 21, 5);\n \n gen_load_gpr(t0, Rb);\n- tcg_gen_addi_tl(t0, t0, (int8_t)s8);\n+ tcg_gen_addi_i32(t0, t0, (int8_t)s8);\n if (postmodify) {\n gen_store_gpr(t0, Rb);\n }\n@@ -737,52 +737,52 @@ static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)\n switch (optn3) {\n /* XRa[7:0] = tmp8 */\n case MXU_OPTN3_PTN0:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n gen_load_mxu_gpr(t0, XRa);\n- tcg_gen_deposit_tl(t0, t0, t1, 0, 8);\n+ tcg_gen_deposit_i32(t0, t0, t1, 0, 8);\n break;\n /* XRa[15:8] = tmp8 */\n case MXU_OPTN3_PTN1:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n gen_load_mxu_gpr(t0, XRa);\n- tcg_gen_deposit_tl(t0, t0, t1, 8, 8);\n+ tcg_gen_deposit_i32(t0, t0, t1, 8, 8);\n break;\n /* XRa[23:16] = tmp8 */\n case MXU_OPTN3_PTN2:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n gen_load_mxu_gpr(t0, XRa);\n- tcg_gen_deposit_tl(t0, t0, t1, 16, 8);\n+ tcg_gen_deposit_i32(t0, t0, t1, 16, 8);\n break;\n /* XRa[31:24] = tmp8 */\n case MXU_OPTN3_PTN3:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n gen_load_mxu_gpr(t0, XRa);\n- tcg_gen_deposit_tl(t0, t0, t1, 24, 8);\n+ tcg_gen_deposit_i32(t0, t0, t1, 24, 8);\n break;\n /* XRa = {8'b0, tmp8, 8'b0, tmp8} */\n case MXU_OPTN3_PTN4:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n- tcg_gen_deposit_tl(t0, t1, t1, 16, 16);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_deposit_i32(t0, t1, t1, 16, 16);\n break;\n /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */\n case MXU_OPTN3_PTN5:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n- tcg_gen_shli_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t0, t1, t1, 16, 16);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_shli_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t0, t1, t1, 16, 16);\n break;\n /* XRa = {{8{sign of tmp8}}, tmp8, {8{sign of tmp8}}, tmp8} */\n case MXU_OPTN3_PTN6:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);\n- tcg_gen_mov_tl(t0, t1);\n- tcg_gen_andi_tl(t0, t0, 0xFF00FFFF);\n- tcg_gen_shli_tl(t1, t1, 16);\n- tcg_gen_or_tl(t0, t0, t1);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_SB);\n+ tcg_gen_mov_i32(t0, t1);\n+ tcg_gen_andi_i32(t0, t0, 0xFF00FFFF);\n+ tcg_gen_shli_i32(t1, t1, 16);\n+ tcg_gen_or_i32(t0, t0, t1);\n break;\n /* XRa = {tmp8, tmp8, tmp8, tmp8} */\n case MXU_OPTN3_PTN7:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);\n- tcg_gen_deposit_tl(t1, t1, t1, 8, 8);\n- tcg_gen_deposit_tl(t0, t1, t1, 16, 16);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_deposit_i32(t1, t1, t1, 8, 8);\n+ tcg_gen_deposit_i32(t0, t1, t1, 16, 16);\n break;\n }\n \n@@ -797,11 +797,11 @@ static void gen_mxu_s8ldd(DisasContext *ctx, bool postmodify)\n */\n static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, s8, optn3;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n s8 = extract32(ctx->opcode, 10, 8);\n@@ -814,7 +814,7 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)\n }\n \n gen_load_gpr(t0, Rb);\n- tcg_gen_addi_tl(t0, t0, (int8_t)s8);\n+ tcg_gen_addi_i32(t0, t0, (int8_t)s8);\n if (postmodify) {\n gen_store_gpr(t0, Rb);\n }\n@@ -823,23 +823,23 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)\n switch (optn3) {\n /* XRa[7:0] => tmp8 */\n case MXU_OPTN3_PTN0:\n- tcg_gen_extract_tl(t1, t1, 0, 8);\n+ tcg_gen_extract_i32(t1, t1, 0, 8);\n break;\n /* XRa[15:8] => tmp8 */\n case MXU_OPTN3_PTN1:\n- tcg_gen_extract_tl(t1, t1, 8, 8);\n+ tcg_gen_extract_i32(t1, t1, 8, 8);\n break;\n /* XRa[23:16] => tmp8 */\n case MXU_OPTN3_PTN2:\n- tcg_gen_extract_tl(t1, t1, 16, 8);\n+ tcg_gen_extract_i32(t1, t1, 16, 8);\n break;\n /* XRa[31:24] => tmp8 */\n case MXU_OPTN3_PTN3:\n- tcg_gen_extract_tl(t1, t1, 24, 8);\n+ tcg_gen_extract_i32(t1, t1, 24, 8);\n break;\n }\n \n- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UB);\n+ tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx, MO_UB);\n }\n \n /*\n@@ -850,12 +850,12 @@ static void gen_mxu_s8std(DisasContext *ctx, bool postmodify)\n */\n static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, optn2;\n int32_t s10;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n s10 = sextract32(ctx->opcode, 10, 9) * 2;\n@@ -863,7 +863,7 @@ static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)\n Rb = extract32(ctx->opcode, 21, 5);\n \n gen_load_gpr(t0, Rb);\n- tcg_gen_addi_tl(t0, t0, s10);\n+ tcg_gen_addi_i32(t0, t0, s10);\n if (postmodify) {\n gen_store_gpr(t0, Rb);\n }\n@@ -871,25 +871,25 @@ static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)\n switch (optn2) {\n /* XRa[15:0] = tmp16 */\n case MXU_OPTN2_PTN0:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UW);\n gen_load_mxu_gpr(t0, XRa);\n- tcg_gen_deposit_tl(t0, t0, t1, 0, 16);\n+ tcg_gen_deposit_i32(t0, t0, t1, 0, 16);\n break;\n /* XRa[31:16] = tmp16 */\n case MXU_OPTN2_PTN1:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UW);\n gen_load_mxu_gpr(t0, XRa);\n- tcg_gen_deposit_tl(t0, t0, t1, 16, 16);\n+ tcg_gen_deposit_i32(t0, t0, t1, 16, 16);\n break;\n /* XRa = sign_extend(tmp16) */\n case MXU_OPTN2_PTN2:\n- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SW);\n+ tcg_gen_qemu_ld_i32(t0, t0, ctx->mem_idx, MO_SW);\n break;\n /* XRa = {tmp16, tmp16} */\n case MXU_OPTN2_PTN3:\n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UW);\n- tcg_gen_deposit_tl(t0, t1, t1, 0, 16);\n- tcg_gen_deposit_tl(t0, t1, t1, 16, 16);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, MO_UW);\n+ tcg_gen_deposit_i32(t0, t1, t1, 0, 16);\n+ tcg_gen_deposit_i32(t0, t1, t1, 16, 16);\n break;\n }\n \n@@ -904,12 +904,12 @@ static void gen_mxu_s16ldd(DisasContext *ctx, bool postmodify)\n */\n static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, optn2;\n int32_t s10;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n s10 = sextract32(ctx->opcode, 10, 9) * 2;\n@@ -922,7 +922,7 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)\n }\n \n gen_load_gpr(t0, Rb);\n- tcg_gen_addi_tl(t0, t0, s10);\n+ tcg_gen_addi_i32(t0, t0, s10);\n if (postmodify) {\n gen_store_gpr(t0, Rb);\n }\n@@ -931,15 +931,15 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)\n switch (optn2) {\n /* XRa[15:0] => tmp16 */\n case MXU_OPTN2_PTN0:\n- tcg_gen_extract_tl(t1, t1, 0, 16);\n+ tcg_gen_extract_i32(t1, t1, 0, 16);\n break;\n /* XRa[31:16] => tmp16 */\n case MXU_OPTN2_PTN1:\n- tcg_gen_extract_tl(t1, t1, 16, 16);\n+ tcg_gen_extract_i32(t1, t1, 16, 16);\n break;\n }\n \n- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UW);\n+ tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx, MO_UW);\n }\n \n /*\n@@ -953,11 +953,11 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)\n */\n static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, XRd, rs, rt;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRd = extract32(ctx->opcode, 10, 4);\n@@ -965,20 +965,20 @@ static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)\n rt = extract32(ctx->opcode, 21, 5);\n \n if (unlikely(rs == 0 || rt == 0)) {\n- tcg_gen_movi_tl(t0, 0);\n- tcg_gen_movi_tl(t1, 0);\n+ tcg_gen_movi_i32(t0, 0);\n+ tcg_gen_movi_i32(t1, 0);\n } else {\n gen_load_gpr(t0, rs);\n gen_load_gpr(t1, rt);\n \n if (mulu) {\n- tcg_gen_mulu2_tl(t0, t1, t0, t1);\n+ tcg_gen_mulu2_i32(t0, t1, t0, t1);\n } else {\n- tcg_gen_muls2_tl(t0, t1, t0, t1);\n+ tcg_gen_muls2_i32(t0, t1, t0, t1);\n }\n }\n- tcg_gen_mov_tl(cpu_HI[0], t1);\n- tcg_gen_mov_tl(cpu_LO[0], t0);\n+ tcg_gen_mov_i32(cpu_HI[0], t1);\n+ tcg_gen_mov_i32(cpu_LO[0], t0);\n gen_store_mxu_gpr(t1, XRa);\n gen_store_mxu_gpr(t0, XRd);\n }\n@@ -993,13 +993,13 @@ static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)\n static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,\n bool packed_result)\n {\n- TCGv t0, t1, t2, t3;\n+ TCGv_i32 t0, t1, t2, t3;\n uint32_t XRa, XRb, XRc, XRd, optn2;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRb = extract32(ctx->opcode, 10, 4);\n@@ -1014,64 +1014,64 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,\n */\n \n gen_load_mxu_gpr(t1, XRb);\n- tcg_gen_sextract_tl(t0, t1, 0, 16);\n- tcg_gen_sextract_tl(t1, t1, 16, 16);\n+ tcg_gen_sextract_i32(t0, t1, 0, 16);\n+ tcg_gen_sextract_i32(t1, t1, 16, 16);\n gen_load_mxu_gpr(t3, XRc);\n- tcg_gen_sextract_tl(t2, t3, 0, 16);\n- tcg_gen_sextract_tl(t3, t3, 16, 16);\n+ tcg_gen_sextract_i32(t2, t3, 0, 16);\n+ tcg_gen_sextract_i32(t3, t3, 16, 16);\n \n switch (optn2) {\n case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t1, t3);\n- tcg_gen_mul_tl(t2, t0, t2);\n+ tcg_gen_mul_i32(t3, t1, t3);\n+ tcg_gen_mul_i32(t2, t0, t2);\n break;\n case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t0, t3);\n- tcg_gen_mul_tl(t2, t0, t2);\n+ tcg_gen_mul_i32(t3, t0, t3);\n+ tcg_gen_mul_i32(t2, t0, t2);\n break;\n case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t1, t3);\n- tcg_gen_mul_tl(t2, t1, t2);\n+ tcg_gen_mul_i32(t3, t1, t3);\n+ tcg_gen_mul_i32(t2, t1, t2);\n break;\n case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t0, t3);\n- tcg_gen_mul_tl(t2, t1, t2);\n+ tcg_gen_mul_i32(t3, t0, t3);\n+ tcg_gen_mul_i32(t2, t1, t2);\n break;\n }\n if (fractional) {\n TCGLabel *l_done = gen_new_label();\n- TCGv rounding = tcg_temp_new();\n+ TCGv_i32 rounding = tcg_temp_new_i32();\n \n- tcg_gen_shli_tl(t3, t3, 1);\n- tcg_gen_shli_tl(t2, t2, 1);\n- tcg_gen_andi_tl(rounding, mxu_CR, 0x2);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, rounding, 0, l_done);\n+ tcg_gen_shli_i32(t3, t3, 1);\n+ tcg_gen_shli_i32(t2, t2, 1);\n+ tcg_gen_andi_i32(rounding, mxu_CR, 0x2);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, rounding, 0, l_done);\n if (packed_result) {\n TCGLabel *l_apply_bias_l = gen_new_label();\n TCGLabel *l_apply_bias_r = gen_new_label();\n TCGLabel *l_half_done = gen_new_label();\n- TCGv bias = tcg_temp_new();\n+ TCGv_i32 bias = tcg_temp_new_i32();\n \n /*\n * D16MULF supports unbiased rounding aka \"bankers rounding\",\n * \"round to even\", \"convergent rounding\"\n */\n- tcg_gen_andi_tl(bias, mxu_CR, 0x4);\n- tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_l);\n- tcg_gen_andi_tl(t0, t3, 0x1ffff);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_half_done);\n+ tcg_gen_andi_i32(bias, mxu_CR, 0x4);\n+ tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_l);\n+ tcg_gen_andi_i32(t0, t3, 0x1ffff);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_half_done);\n gen_set_label(l_apply_bias_l);\n- tcg_gen_addi_tl(t3, t3, 0x8000);\n+ tcg_gen_addi_i32(t3, t3, 0x8000);\n gen_set_label(l_half_done);\n- tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_r);\n- tcg_gen_andi_tl(t0, t2, 0x1ffff);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_done);\n+ tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_r);\n+ tcg_gen_andi_i32(t0, t2, 0x1ffff);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_done);\n gen_set_label(l_apply_bias_r);\n- tcg_gen_addi_tl(t2, t2, 0x8000);\n+ tcg_gen_addi_i32(t2, t2, 0x8000);\n } else {\n /* D16MULE doesn't support unbiased rounding */\n- tcg_gen_addi_tl(t3, t3, 0x8000);\n- tcg_gen_addi_tl(t2, t2, 0x8000);\n+ tcg_gen_addi_i32(t3, t3, 0x8000);\n+ tcg_gen_addi_i32(t2, t2, 0x8000);\n }\n gen_set_label(l_done);\n }\n@@ -1079,9 +1079,9 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,\n gen_store_mxu_gpr(t3, XRa);\n gen_store_mxu_gpr(t2, XRd);\n } else {\n- tcg_gen_andi_tl(t3, t3, 0xffff0000);\n- tcg_gen_shri_tl(t2, t2, 16);\n- tcg_gen_or_tl(t3, t3, t2);\n+ tcg_gen_andi_i32(t3, t3, 0xffff0000);\n+ tcg_gen_shri_i32(t2, t2, 16);\n+ tcg_gen_or_i32(t3, t3, t2);\n gen_store_mxu_gpr(t3, XRa);\n }\n }\n@@ -1097,13 +1097,13 @@ static void gen_mxu_d16mul(DisasContext *ctx, bool fractional,\n static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,\n bool packed_result)\n {\n- TCGv t0, t1, t2, t3;\n+ TCGv_i32 t0, t1, t2, t3;\n uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRb = extract32(ctx->opcode, 10, 4);\n@@ -1113,90 +1113,90 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,\n aptn2 = extract32(ctx->opcode, 24, 2);\n \n gen_load_mxu_gpr(t1, XRb);\n- tcg_gen_sextract_tl(t0, t1, 0, 16);\n- tcg_gen_sextract_tl(t1, t1, 16, 16);\n+ tcg_gen_sextract_i32(t0, t1, 0, 16);\n+ tcg_gen_sextract_i32(t1, t1, 16, 16);\n \n gen_load_mxu_gpr(t3, XRc);\n- tcg_gen_sextract_tl(t2, t3, 0, 16);\n- tcg_gen_sextract_tl(t3, t3, 16, 16);\n+ tcg_gen_sextract_i32(t2, t3, 0, 16);\n+ tcg_gen_sextract_i32(t3, t3, 16, 16);\n \n switch (optn2) {\n case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t1, t3);\n- tcg_gen_mul_tl(t2, t0, t2);\n+ tcg_gen_mul_i32(t3, t1, t3);\n+ tcg_gen_mul_i32(t2, t0, t2);\n break;\n case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t0, t3);\n- tcg_gen_mul_tl(t2, t0, t2);\n+ tcg_gen_mul_i32(t3, t0, t3);\n+ tcg_gen_mul_i32(t2, t0, t2);\n break;\n case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t1, t3);\n- tcg_gen_mul_tl(t2, t1, t2);\n+ tcg_gen_mul_i32(t3, t1, t3);\n+ tcg_gen_mul_i32(t2, t1, t2);\n break;\n case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t0, t3);\n- tcg_gen_mul_tl(t2, t1, t2);\n+ tcg_gen_mul_i32(t3, t0, t3);\n+ tcg_gen_mul_i32(t2, t1, t2);\n break;\n }\n \n if (fractional) {\n- tcg_gen_shli_tl(t3, t3, 1);\n- tcg_gen_shli_tl(t2, t2, 1);\n+ tcg_gen_shli_i32(t3, t3, 1);\n+ tcg_gen_shli_i32(t2, t2, 1);\n }\n gen_load_mxu_gpr(t0, XRa);\n gen_load_mxu_gpr(t1, XRd);\n \n switch (aptn2) {\n case MXU_APTN2_AA:\n- tcg_gen_add_tl(t3, t0, t3);\n- tcg_gen_add_tl(t2, t1, t2);\n+ tcg_gen_add_i32(t3, t0, t3);\n+ tcg_gen_add_i32(t2, t1, t2);\n break;\n case MXU_APTN2_AS:\n- tcg_gen_add_tl(t3, t0, t3);\n- tcg_gen_sub_tl(t2, t1, t2);\n+ tcg_gen_add_i32(t3, t0, t3);\n+ tcg_gen_sub_i32(t2, t1, t2);\n break;\n case MXU_APTN2_SA:\n- tcg_gen_sub_tl(t3, t0, t3);\n- tcg_gen_add_tl(t2, t1, t2);\n+ tcg_gen_sub_i32(t3, t0, t3);\n+ tcg_gen_add_i32(t2, t1, t2);\n break;\n case MXU_APTN2_SS:\n- tcg_gen_sub_tl(t3, t0, t3);\n- tcg_gen_sub_tl(t2, t1, t2);\n+ tcg_gen_sub_i32(t3, t0, t3);\n+ tcg_gen_sub_i32(t2, t1, t2);\n break;\n }\n \n if (fractional) {\n TCGLabel *l_done = gen_new_label();\n- TCGv rounding = tcg_temp_new();\n+ TCGv_i32 rounding = tcg_temp_new_i32();\n \n- tcg_gen_andi_tl(rounding, mxu_CR, 0x2);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, rounding, 0, l_done);\n+ tcg_gen_andi_i32(rounding, mxu_CR, 0x2);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, rounding, 0, l_done);\n if (packed_result) {\n TCGLabel *l_apply_bias_l = gen_new_label();\n TCGLabel *l_apply_bias_r = gen_new_label();\n TCGLabel *l_half_done = gen_new_label();\n- TCGv bias = tcg_temp_new();\n+ TCGv_i32 bias = tcg_temp_new_i32();\n \n /*\n * D16MACF supports unbiased rounding aka \"bankers rounding\",\n * \"round to even\", \"convergent rounding\"\n */\n- tcg_gen_andi_tl(bias, mxu_CR, 0x4);\n- tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_l);\n- tcg_gen_andi_tl(t0, t3, 0x1ffff);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_half_done);\n+ tcg_gen_andi_i32(bias, mxu_CR, 0x4);\n+ tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_l);\n+ tcg_gen_andi_i32(t0, t3, 0x1ffff);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_half_done);\n gen_set_label(l_apply_bias_l);\n- tcg_gen_addi_tl(t3, t3, 0x8000);\n+ tcg_gen_addi_i32(t3, t3, 0x8000);\n gen_set_label(l_half_done);\n- tcg_gen_brcondi_tl(TCG_COND_NE, bias, 0, l_apply_bias_r);\n- tcg_gen_andi_tl(t0, t2, 0x1ffff);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0x8000, l_done);\n+ tcg_gen_brcondi_i32(TCG_COND_NE, bias, 0, l_apply_bias_r);\n+ tcg_gen_andi_i32(t0, t2, 0x1ffff);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0x8000, l_done);\n gen_set_label(l_apply_bias_r);\n- tcg_gen_addi_tl(t2, t2, 0x8000);\n+ tcg_gen_addi_i32(t2, t2, 0x8000);\n } else {\n /* D16MACE doesn't support unbiased rounding */\n- tcg_gen_addi_tl(t3, t3, 0x8000);\n- tcg_gen_addi_tl(t2, t2, 0x8000);\n+ tcg_gen_addi_i32(t3, t3, 0x8000);\n+ tcg_gen_addi_i32(t2, t2, 0x8000);\n }\n gen_set_label(l_done);\n }\n@@ -1205,9 +1205,9 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,\n gen_store_mxu_gpr(t3, XRa);\n gen_store_mxu_gpr(t2, XRd);\n } else {\n- tcg_gen_andi_tl(t3, t3, 0xffff0000);\n- tcg_gen_shri_tl(t2, t2, 16);\n- tcg_gen_or_tl(t3, t3, t2);\n+ tcg_gen_andi_i32(t3, t3, 0xffff0000);\n+ tcg_gen_shri_i32(t2, t2, 16);\n+ tcg_gen_or_i32(t3, t3, t2);\n gen_store_mxu_gpr(t3, XRa);\n }\n }\n@@ -1218,13 +1218,13 @@ static void gen_mxu_d16mac(DisasContext *ctx, bool fractional,\n */\n static void gen_mxu_d16madl(DisasContext *ctx)\n {\n- TCGv t0, t1, t2, t3;\n+ TCGv_i32 t0, t1, t2, t3;\n uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRb = extract32(ctx->opcode, 10, 4);\n@@ -1234,60 +1234,60 @@ static void gen_mxu_d16madl(DisasContext *ctx)\n aptn2 = extract32(ctx->opcode, 24, 2);\n \n gen_load_mxu_gpr(t1, XRb);\n- tcg_gen_sextract_tl(t0, t1, 0, 16);\n- tcg_gen_sextract_tl(t1, t1, 16, 16);\n+ tcg_gen_sextract_i32(t0, t1, 0, 16);\n+ tcg_gen_sextract_i32(t1, t1, 16, 16);\n \n gen_load_mxu_gpr(t3, XRc);\n- tcg_gen_sextract_tl(t2, t3, 0, 16);\n- tcg_gen_sextract_tl(t3, t3, 16, 16);\n+ tcg_gen_sextract_i32(t2, t3, 0, 16);\n+ tcg_gen_sextract_i32(t3, t3, 16, 16);\n \n switch (optn2) {\n case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t1, t3);\n- tcg_gen_mul_tl(t2, t0, t2);\n+ tcg_gen_mul_i32(t3, t1, t3);\n+ tcg_gen_mul_i32(t2, t0, t2);\n break;\n case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t0, t3);\n- tcg_gen_mul_tl(t2, t0, t2);\n+ tcg_gen_mul_i32(t3, t0, t3);\n+ tcg_gen_mul_i32(t2, t0, t2);\n break;\n case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t1, t3);\n- tcg_gen_mul_tl(t2, t1, t2);\n+ tcg_gen_mul_i32(t3, t1, t3);\n+ tcg_gen_mul_i32(t2, t1, t2);\n break;\n case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */\n- tcg_gen_mul_tl(t3, t0, t3);\n- tcg_gen_mul_tl(t2, t1, t2);\n+ tcg_gen_mul_i32(t3, t0, t3);\n+ tcg_gen_mul_i32(t2, t1, t2);\n break;\n }\n- tcg_gen_extract_tl(t2, t2, 0, 16);\n- tcg_gen_extract_tl(t3, t3, 0, 16);\n+ tcg_gen_extract_i32(t2, t2, 0, 16);\n+ tcg_gen_extract_i32(t3, t3, 0, 16);\n \n gen_load_mxu_gpr(t1, XRa);\n- tcg_gen_extract_tl(t0, t1, 0, 16);\n- tcg_gen_extract_tl(t1, t1, 16, 16);\n+ tcg_gen_extract_i32(t0, t1, 0, 16);\n+ tcg_gen_extract_i32(t1, t1, 16, 16);\n \n switch (aptn2) {\n case MXU_APTN2_AA:\n- tcg_gen_add_tl(t3, t1, t3);\n- tcg_gen_add_tl(t2, t0, t2);\n+ tcg_gen_add_i32(t3, t1, t3);\n+ tcg_gen_add_i32(t2, t0, t2);\n break;\n case MXU_APTN2_AS:\n- tcg_gen_add_tl(t3, t1, t3);\n- tcg_gen_sub_tl(t2, t0, t2);\n+ tcg_gen_add_i32(t3, t1, t3);\n+ tcg_gen_sub_i32(t2, t0, t2);\n break;\n case MXU_APTN2_SA:\n- tcg_gen_sub_tl(t3, t1, t3);\n- tcg_gen_add_tl(t2, t0, t2);\n+ tcg_gen_sub_i32(t3, t1, t3);\n+ tcg_gen_add_i32(t2, t0, t2);\n break;\n case MXU_APTN2_SS:\n- tcg_gen_sub_tl(t3, t1, t3);\n- tcg_gen_sub_tl(t2, t0, t2);\n+ tcg_gen_sub_i32(t3, t1, t3);\n+ tcg_gen_sub_i32(t2, t0, t2);\n break;\n }\n \n- tcg_gen_andi_tl(t2, t2, 0xffff);\n- tcg_gen_shli_tl(t3, t3, 16);\n- tcg_gen_or_tl(mxu_gpr[XRd - 1], t3, t2);\n+ tcg_gen_andi_i32(t2, t2, 0xffff);\n+ tcg_gen_shli_i32(t3, t3, 16);\n+ tcg_gen_or_i32(mxu_gpr[XRd - 1], t3, t2);\n }\n \n /*\n@@ -1296,11 +1296,11 @@ static void gen_mxu_d16madl(DisasContext *ctx)\n */\n static void gen_mxu_s16mad(DisasContext *ctx)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, XRb, XRc, XRd, optn2, aptn1, pad;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRb = extract32(ctx->opcode, 10, 4);\n@@ -1319,32 +1319,32 @@ static void gen_mxu_s16mad(DisasContext *ctx)\n \n switch (optn2) {\n case MXU_OPTN2_WW: /* XRB.H*XRC.H */\n- tcg_gen_sextract_tl(t0, t0, 16, 16);\n- tcg_gen_sextract_tl(t1, t1, 16, 16);\n+ tcg_gen_sextract_i32(t0, t0, 16, 16);\n+ tcg_gen_sextract_i32(t1, t1, 16, 16);\n break;\n case MXU_OPTN2_LW: /* XRB.L*XRC.L */\n- tcg_gen_sextract_tl(t0, t0, 0, 16);\n- tcg_gen_sextract_tl(t1, t1, 0, 16);\n+ tcg_gen_sextract_i32(t0, t0, 0, 16);\n+ tcg_gen_sextract_i32(t1, t1, 0, 16);\n break;\n case MXU_OPTN2_HW: /* XRB.H*XRC.L */\n- tcg_gen_sextract_tl(t0, t0, 16, 16);\n- tcg_gen_sextract_tl(t1, t1, 0, 16);\n+ tcg_gen_sextract_i32(t0, t0, 16, 16);\n+ tcg_gen_sextract_i32(t1, t1, 0, 16);\n break;\n case MXU_OPTN2_XW: /* XRB.L*XRC.H */\n- tcg_gen_sextract_tl(t0, t0, 0, 16);\n- tcg_gen_sextract_tl(t1, t1, 16, 16);\n+ tcg_gen_sextract_i32(t0, t0, 0, 16);\n+ tcg_gen_sextract_i32(t1, t1, 16, 16);\n break;\n }\n- tcg_gen_mul_tl(t0, t0, t1);\n+ tcg_gen_mul_i32(t0, t0, t1);\n \n gen_load_mxu_gpr(t1, XRa);\n \n switch (aptn1) {\n case MXU_APTN1_A:\n- tcg_gen_add_tl(t1, t1, t0);\n+ tcg_gen_add_i32(t1, t1, t0);\n break;\n case MXU_APTN1_S:\n- tcg_gen_sub_tl(t1, t1, t0);\n+ tcg_gen_sub_i32(t1, t1, t0);\n break;\n }\n \n@@ -1361,17 +1361,17 @@ static void gen_mxu_s16mad(DisasContext *ctx)\n */\n static void gen_mxu_q8mul_mac(DisasContext *ctx, bool su, bool mac)\n {\n- TCGv t0, t1, t2, t3, t4, t5, t6, t7;\n+ TCGv_i32 t0, t1, t2, t3, t4, t5, t6, t7;\n uint32_t XRa, XRb, XRc, XRd, aptn2;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n- t4 = tcg_temp_new();\n- t5 = tcg_temp_new();\n- t6 = tcg_temp_new();\n- t7 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n+ t4 = tcg_temp_new_i32();\n+ t5 = tcg_temp_new_i32();\n+ t6 = tcg_temp_new_i32();\n+ t7 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRb = extract32(ctx->opcode, 10, 4);\n@@ -1384,53 +1384,53 @@ static void gen_mxu_q8mul_mac(DisasContext *ctx, bool su, bool mac)\n \n if (su) {\n /* Q8MULSU / Q8MACSU */\n- tcg_gen_sextract_tl(t0, t3, 0, 8);\n- tcg_gen_sextract_tl(t1, t3, 8, 8);\n- tcg_gen_sextract_tl(t2, t3, 16, 8);\n- tcg_gen_sextract_tl(t3, t3, 24, 8);\n+ tcg_gen_sextract_i32(t0, t3, 0, 8);\n+ tcg_gen_sextract_i32(t1, t3, 8, 8);\n+ tcg_gen_sextract_i32(t2, t3, 16, 8);\n+ tcg_gen_sextract_i32(t3, t3, 24, 8);\n } else {\n /* Q8MUL / Q8MAC */\n- tcg_gen_extract_tl(t0, t3, 0, 8);\n- tcg_gen_extract_tl(t1, t3, 8, 8);\n- tcg_gen_extract_tl(t2, t3, 16, 8);\n- tcg_gen_extract_tl(t3, t3, 24, 8);\n+ tcg_gen_extract_i32(t0, t3, 0, 8);\n+ tcg_gen_extract_i32(t1, t3, 8, 8);\n+ tcg_gen_extract_i32(t2, t3, 16, 8);\n+ tcg_gen_extract_i32(t3, t3, 24, 8);\n }\n \n- tcg_gen_extract_tl(t4, t7, 0, 8);\n- tcg_gen_extract_tl(t5, t7, 8, 8);\n- tcg_gen_extract_tl(t6, t7, 16, 8);\n- tcg_gen_extract_tl(t7, t7, 24, 8);\n+ tcg_gen_extract_i32(t4, t7, 0, 8);\n+ tcg_gen_extract_i32(t5, t7, 8, 8);\n+ tcg_gen_extract_i32(t6, t7, 16, 8);\n+ tcg_gen_extract_i32(t7, t7, 24, 8);\n \n- tcg_gen_mul_tl(t0, t0, t4);\n- tcg_gen_mul_tl(t1, t1, t5);\n- tcg_gen_mul_tl(t2, t2, t6);\n- tcg_gen_mul_tl(t3, t3, t7);\n+ tcg_gen_mul_i32(t0, t0, t4);\n+ tcg_gen_mul_i32(t1, t1, t5);\n+ tcg_gen_mul_i32(t2, t2, t6);\n+ tcg_gen_mul_i32(t3, t3, t7);\n \n if (mac) {\n gen_load_mxu_gpr(t4, XRd);\n gen_load_mxu_gpr(t5, XRa);\n- tcg_gen_extract_tl(t6, t4, 0, 16);\n- tcg_gen_extract_tl(t7, t4, 16, 16);\n+ tcg_gen_extract_i32(t6, t4, 0, 16);\n+ tcg_gen_extract_i32(t7, t4, 16, 16);\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(t0, t6, t0);\n- tcg_gen_sub_tl(t1, t7, t1);\n+ tcg_gen_sub_i32(t0, t6, t0);\n+ tcg_gen_sub_i32(t1, t7, t1);\n } else {\n- tcg_gen_add_tl(t0, t6, t0);\n- tcg_gen_add_tl(t1, t7, t1);\n+ tcg_gen_add_i32(t0, t6, t0);\n+ tcg_gen_add_i32(t1, t7, t1);\n }\n- tcg_gen_extract_tl(t6, t5, 0, 16);\n- tcg_gen_extract_tl(t7, t5, 16, 16);\n+ tcg_gen_extract_i32(t6, t5, 0, 16);\n+ tcg_gen_extract_i32(t7, t5, 16, 16);\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(t2, t6, t2);\n- tcg_gen_sub_tl(t3, t7, t3);\n+ tcg_gen_sub_i32(t2, t6, t2);\n+ tcg_gen_sub_i32(t3, t7, t3);\n } else {\n- tcg_gen_add_tl(t2, t6, t2);\n- tcg_gen_add_tl(t3, t7, t3);\n+ tcg_gen_add_i32(t2, t6, t2);\n+ tcg_gen_add_i32(t3, t7, t3);\n }\n }\n \n- tcg_gen_deposit_tl(t0, t0, t1, 16, 16);\n- tcg_gen_deposit_tl(t1, t2, t3, 16, 16);\n+ tcg_gen_deposit_i32(t0, t0, t1, 16, 16);\n+ tcg_gen_deposit_i32(t1, t2, t3, 16, 16);\n \n gen_store_mxu_gpr(t0, XRd);\n gen_store_mxu_gpr(t1, XRa);\n@@ -1443,17 +1443,17 @@ static void gen_mxu_q8mul_mac(DisasContext *ctx, bool su, bool mac)\n */\n static void gen_mxu_q8madl(DisasContext *ctx)\n {\n- TCGv t0, t1, t2, t3, t4, t5, t6, t7;\n+ TCGv_i32 t0, t1, t2, t3, t4, t5, t6, t7;\n uint32_t XRa, XRb, XRc, XRd, aptn2;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n- t4 = tcg_temp_new();\n- t5 = tcg_temp_new();\n- t6 = tcg_temp_new();\n- t7 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n+ t4 = tcg_temp_new_i32();\n+ t5 = tcg_temp_new_i32();\n+ t6 = tcg_temp_new_i32();\n+ t7 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRb = extract32(ctx->opcode, 10, 4);\n@@ -1464,45 +1464,45 @@ static void gen_mxu_q8madl(DisasContext *ctx)\n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t7, XRc);\n \n- tcg_gen_extract_tl(t0, t3, 0, 8);\n- tcg_gen_extract_tl(t1, t3, 8, 8);\n- tcg_gen_extract_tl(t2, t3, 16, 8);\n- tcg_gen_extract_tl(t3, t3, 24, 8);\n+ tcg_gen_extract_i32(t0, t3, 0, 8);\n+ tcg_gen_extract_i32(t1, t3, 8, 8);\n+ tcg_gen_extract_i32(t2, t3, 16, 8);\n+ tcg_gen_extract_i32(t3, t3, 24, 8);\n \n- tcg_gen_extract_tl(t4, t7, 0, 8);\n- tcg_gen_extract_tl(t5, t7, 8, 8);\n- tcg_gen_extract_tl(t6, t7, 16, 8);\n- tcg_gen_extract_tl(t7, t7, 24, 8);\n+ tcg_gen_extract_i32(t4, t7, 0, 8);\n+ tcg_gen_extract_i32(t5, t7, 8, 8);\n+ tcg_gen_extract_i32(t6, t7, 16, 8);\n+ tcg_gen_extract_i32(t7, t7, 24, 8);\n \n- tcg_gen_mul_tl(t0, t0, t4);\n- tcg_gen_mul_tl(t1, t1, t5);\n- tcg_gen_mul_tl(t2, t2, t6);\n- tcg_gen_mul_tl(t3, t3, t7);\n+ tcg_gen_mul_i32(t0, t0, t4);\n+ tcg_gen_mul_i32(t1, t1, t5);\n+ tcg_gen_mul_i32(t2, t2, t6);\n+ tcg_gen_mul_i32(t3, t3, t7);\n \n gen_load_mxu_gpr(t4, XRa);\n- tcg_gen_extract_tl(t6, t4, 0, 8);\n- tcg_gen_extract_tl(t7, t4, 8, 8);\n+ tcg_gen_extract_i32(t6, t4, 0, 8);\n+ tcg_gen_extract_i32(t7, t4, 8, 8);\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(t0, t6, t0);\n- tcg_gen_sub_tl(t1, t7, t1);\n+ tcg_gen_sub_i32(t0, t6, t0);\n+ tcg_gen_sub_i32(t1, t7, t1);\n } else {\n- tcg_gen_add_tl(t0, t6, t0);\n- tcg_gen_add_tl(t1, t7, t1);\n+ tcg_gen_add_i32(t0, t6, t0);\n+ tcg_gen_add_i32(t1, t7, t1);\n }\n- tcg_gen_extract_tl(t6, t4, 16, 8);\n- tcg_gen_extract_tl(t7, t4, 24, 8);\n+ tcg_gen_extract_i32(t6, t4, 16, 8);\n+ tcg_gen_extract_i32(t7, t4, 24, 8);\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(t2, t6, t2);\n- tcg_gen_sub_tl(t3, t7, t3);\n+ tcg_gen_sub_i32(t2, t6, t2);\n+ tcg_gen_sub_i32(t3, t7, t3);\n } else {\n- tcg_gen_add_tl(t2, t6, t2);\n- tcg_gen_add_tl(t3, t7, t3);\n+ tcg_gen_add_i32(t2, t6, t2);\n+ tcg_gen_add_i32(t3, t7, t3);\n }\n \n- tcg_gen_andi_tl(t5, t0, 0xff);\n- tcg_gen_deposit_tl(t5, t5, t1, 8, 8);\n- tcg_gen_deposit_tl(t5, t5, t2, 16, 8);\n- tcg_gen_deposit_tl(t5, t5, t3, 24, 8);\n+ tcg_gen_andi_i32(t5, t0, 0xff);\n+ tcg_gen_deposit_i32(t5, t5, t1, 8, 8);\n+ tcg_gen_deposit_i32(t5, t5, t2, 16, 8);\n+ tcg_gen_deposit_i32(t5, t5, t3, 24, 8);\n \n gen_store_mxu_gpr(t5, XRd);\n }\n@@ -1518,21 +1518,21 @@ static void gen_mxu_q8madl(DisasContext *ctx)\n */\n static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, s12;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n s12 = sextract32(ctx->opcode, 10, 10);\n Rb = extract32(ctx->opcode, 21, 5);\n \n gen_load_gpr(t0, Rb);\n- tcg_gen_movi_tl(t1, s12 * 4);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_movi_i32(t1, s12 * 4);\n+ tcg_gen_add_i32(t0, t0, t1);\n \n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx,\n MO_SL | mo_endian_rev(ctx, reversed) |\n ctx->default_tcg_memop_mask);\n gen_store_mxu_gpr(t1, XRa);\n@@ -1553,22 +1553,22 @@ static void gen_mxu_s32ldxx(DisasContext *ctx, bool reversed, bool postinc)\n */\n static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, s12;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n s12 = sextract32(ctx->opcode, 10, 10);\n Rb = extract32(ctx->opcode, 21, 5);\n \n gen_load_gpr(t0, Rb);\n- tcg_gen_movi_tl(t1, s12 * 4);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_movi_i32(t1, s12 * 4);\n+ tcg_gen_add_i32(t0, t0, t1);\n \n gen_load_mxu_gpr(t1, XRa);\n- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,\n+ tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx,\n MO_SL | mo_endian_rev(ctx, reversed) |\n ctx->default_tcg_memop_mask);\n \n@@ -1589,11 +1589,11 @@ static void gen_mxu_s32stxx(DisasContext *ctx, bool reversed, bool postinc)\n static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,\n bool postinc, uint32_t strd2)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, Rc;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n Rc = extract32(ctx->opcode, 16, 5);\n@@ -1601,10 +1601,10 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,\n \n gen_load_gpr(t0, Rb);\n gen_load_gpr(t1, Rc);\n- tcg_gen_shli_tl(t1, t1, strd2);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_shli_i32(t1, t1, strd2);\n+ tcg_gen_add_i32(t0, t0, t1);\n \n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx,\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx,\n MO_SL | mo_endian_rev(ctx, reversed) |\n ctx->default_tcg_memop_mask);\n gen_store_mxu_gpr(t1, XRa);\n@@ -1627,11 +1627,11 @@ static void gen_mxu_s32ldxvx(DisasContext *ctx, bool reversed,\n */\n static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t Ra, Rb, Rc;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n Ra = extract32(ctx->opcode, 11, 5);\n Rc = extract32(ctx->opcode, 16, 5);\n@@ -1639,10 +1639,10 @@ static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)\n \n gen_load_gpr(t0, Rb);\n gen_load_gpr(t1, Rc);\n- tcg_gen_shli_tl(t1, t1, strd2);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_shli_i32(t1, t1, strd2);\n+ tcg_gen_add_i32(t0, t0, t1);\n \n- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop | ctx->default_tcg_memop_mask);\n+ tcg_gen_qemu_ld_i32(t1, t0, ctx->mem_idx, mop | ctx->default_tcg_memop_mask);\n gen_store_gpr(t1, Ra);\n }\n \n@@ -1658,11 +1658,11 @@ static void gen_mxu_lxx(DisasContext *ctx, uint32_t strd2, MemOp mop)\n static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,\n bool postinc, uint32_t strd2)\n {\n- TCGv t0, t1;\n+ TCGv_i32 t0, t1;\n uint32_t XRa, Rb, Rc;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n Rc = extract32(ctx->opcode, 16, 5);\n@@ -1670,11 +1670,11 @@ static void gen_mxu_s32stxvx(DisasContext *ctx, bool reversed,\n \n gen_load_gpr(t0, Rb);\n gen_load_gpr(t1, Rc);\n- tcg_gen_shli_tl(t1, t1, strd2);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_shli_i32(t1, t1, strd2);\n+ tcg_gen_add_i32(t0, t0, t1);\n \n gen_load_mxu_gpr(t1, XRa);\n- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,\n+ tcg_gen_qemu_st_i32(t1, t0, ctx->mem_idx,\n MO_SL | mo_endian_rev(ctx, reversed) |\n ctx->default_tcg_memop_mask);\n \n@@ -1859,23 +1859,23 @@ static void gen_mxu_d32sxx(DisasContext *ctx, bool right, bool arithmetic)\n XRd = extract32(ctx->opcode, 18, 4);\n sft4 = extract32(ctx->opcode, 22, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n \n if (right) {\n if (arithmetic) {\n- tcg_gen_sari_tl(t0, t0, sft4);\n- tcg_gen_sari_tl(t1, t1, sft4);\n+ tcg_gen_sari_i32(t0, t0, sft4);\n+ tcg_gen_sari_i32(t1, t1, sft4);\n } else {\n- tcg_gen_shri_tl(t0, t0, sft4);\n- tcg_gen_shri_tl(t1, t1, sft4);\n+ tcg_gen_shri_i32(t0, t0, sft4);\n+ tcg_gen_shri_i32(t1, t1, sft4);\n }\n } else {\n- tcg_gen_shli_tl(t0, t0, sft4);\n- tcg_gen_shli_tl(t1, t1, sft4);\n+ tcg_gen_shli_i32(t0, t0, sft4);\n+ tcg_gen_shli_i32(t1, t1, sft4);\n }\n gen_store_mxu_gpr(t0, XRa);\n gen_store_mxu_gpr(t1, XRd);\n@@ -1900,26 +1900,26 @@ static void gen_mxu_d32sxxv(DisasContext *ctx, bool right, bool arithmetic)\n XRd = extract32(ctx->opcode, 14, 4);\n rs = extract32(ctx->opcode, 21, 5);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRa);\n gen_load_mxu_gpr(t1, XRd);\n gen_load_gpr(t2, rs);\n- tcg_gen_andi_tl(t2, t2, 0x0f);\n+ tcg_gen_andi_i32(t2, t2, 0x0f);\n \n if (right) {\n if (arithmetic) {\n- tcg_gen_sar_tl(t0, t0, t2);\n- tcg_gen_sar_tl(t1, t1, t2);\n+ tcg_gen_sar_i32(t0, t0, t2);\n+ tcg_gen_sar_i32(t1, t1, t2);\n } else {\n- tcg_gen_shr_tl(t0, t0, t2);\n- tcg_gen_shr_tl(t1, t1, t2);\n+ tcg_gen_shr_i32(t0, t0, t2);\n+ tcg_gen_shr_i32(t1, t1, t2);\n }\n } else {\n- tcg_gen_shl_tl(t0, t0, t2);\n- tcg_gen_shl_tl(t1, t1, t2);\n+ tcg_gen_shl_i32(t0, t0, t2);\n+ tcg_gen_shl_i32(t1, t1, t2);\n }\n gen_store_mxu_gpr(t0, XRa);\n gen_store_mxu_gpr(t1, XRd);\n@@ -1946,23 +1946,23 @@ static void gen_mxu_d32sarl(DisasContext *ctx, bool sarw)\n if (unlikely(XRa == 0)) {\n /* destination is zero register -> do nothing */\n } else {\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n if (!sarw) {\n /* Make SFT4 from rb field */\n- tcg_gen_movi_tl(t2, rb >> 1);\n+ tcg_gen_movi_i32(t2, rb >> 1);\n } else {\n gen_load_gpr(t2, rb);\n- tcg_gen_andi_tl(t2, t2, 0x0f);\n+ tcg_gen_andi_i32(t2, t2, 0x0f);\n }\n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n- tcg_gen_sar_tl(t0, t0, t2);\n- tcg_gen_sar_tl(t1, t1, t2);\n- tcg_gen_extract_tl(t2, t1, 0, 16);\n- tcg_gen_deposit_tl(t2, t2, t0, 16, 16);\n+ tcg_gen_sar_i32(t0, t0, t2);\n+ tcg_gen_sar_i32(t1, t1, t2);\n+ tcg_gen_extract_i32(t2, t1, 0, 16);\n+ tcg_gen_deposit_i32(t2, t2, t0, 16, 16);\n gen_store_mxu_gpr(t2, XRa);\n }\n }\n@@ -1988,46 +1988,46 @@ static void gen_mxu_q16sxx(DisasContext *ctx, bool right, bool arithmetic)\n XRd = extract32(ctx->opcode, 18, 4);\n sft4 = extract32(ctx->opcode, 22, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t2, XRc);\n \n if (arithmetic) {\n- tcg_gen_sextract_tl(t1, t0, 16, 16);\n- tcg_gen_sextract_tl(t0, t0, 0, 16);\n- tcg_gen_sextract_tl(t3, t2, 16, 16);\n- tcg_gen_sextract_tl(t2, t2, 0, 16);\n+ tcg_gen_sextract_i32(t1, t0, 16, 16);\n+ tcg_gen_sextract_i32(t0, t0, 0, 16);\n+ tcg_gen_sextract_i32(t3, t2, 16, 16);\n+ tcg_gen_sextract_i32(t2, t2, 0, 16);\n } else {\n- tcg_gen_extract_tl(t1, t0, 16, 16);\n- tcg_gen_extract_tl(t0, t0, 0, 16);\n- tcg_gen_extract_tl(t3, t2, 16, 16);\n- tcg_gen_extract_tl(t2, t2, 0, 16);\n+ tcg_gen_extract_i32(t1, t0, 16, 16);\n+ tcg_gen_extract_i32(t0, t0, 0, 16);\n+ tcg_gen_extract_i32(t3, t2, 16, 16);\n+ tcg_gen_extract_i32(t2, t2, 0, 16);\n }\n \n if (right) {\n if (arithmetic) {\n- tcg_gen_sari_tl(t0, t0, sft4);\n- tcg_gen_sari_tl(t1, t1, sft4);\n- tcg_gen_sari_tl(t2, t2, sft4);\n- tcg_gen_sari_tl(t3, t3, sft4);\n+ tcg_gen_sari_i32(t0, t0, sft4);\n+ tcg_gen_sari_i32(t1, t1, sft4);\n+ tcg_gen_sari_i32(t2, t2, sft4);\n+ tcg_gen_sari_i32(t3, t3, sft4);\n } else {\n- tcg_gen_shri_tl(t0, t0, sft4);\n- tcg_gen_shri_tl(t1, t1, sft4);\n- tcg_gen_shri_tl(t2, t2, sft4);\n- tcg_gen_shri_tl(t3, t3, sft4);\n+ tcg_gen_shri_i32(t0, t0, sft4);\n+ tcg_gen_shri_i32(t1, t1, sft4);\n+ tcg_gen_shri_i32(t2, t2, sft4);\n+ tcg_gen_shri_i32(t3, t3, sft4);\n }\n } else {\n- tcg_gen_shli_tl(t0, t0, sft4);\n- tcg_gen_shli_tl(t1, t1, sft4);\n- tcg_gen_shli_tl(t2, t2, sft4);\n- tcg_gen_shli_tl(t3, t3, sft4);\n+ tcg_gen_shli_i32(t0, t0, sft4);\n+ tcg_gen_shli_i32(t1, t1, sft4);\n+ tcg_gen_shli_i32(t2, t2, sft4);\n+ tcg_gen_shli_i32(t3, t3, sft4);\n }\n- tcg_gen_deposit_tl(t0, t0, t1, 16, 16);\n- tcg_gen_deposit_tl(t2, t2, t3, 16, 16);\n+ tcg_gen_deposit_i32(t0, t0, t1, 16, 16);\n+ tcg_gen_deposit_i32(t2, t2, t3, 16, 16);\n \n gen_store_mxu_gpr(t0, XRa);\n gen_store_mxu_gpr(t2, XRd);\n@@ -2052,50 +2052,50 @@ static void gen_mxu_q16sxxv(DisasContext *ctx, bool right, bool arithmetic)\n XRd = extract32(ctx->opcode, 14, 4);\n rs = extract32(ctx->opcode, 21, 5);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t5 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t5 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRa);\n gen_load_mxu_gpr(t2, XRd);\n gen_load_gpr(t5, rs);\n- tcg_gen_andi_tl(t5, t5, 0x0f);\n+ tcg_gen_andi_i32(t5, t5, 0x0f);\n \n \n if (arithmetic) {\n- tcg_gen_sextract_tl(t1, t0, 16, 16);\n- tcg_gen_sextract_tl(t0, t0, 0, 16);\n- tcg_gen_sextract_tl(t3, t2, 16, 16);\n- tcg_gen_sextract_tl(t2, t2, 0, 16);\n+ tcg_gen_sextract_i32(t1, t0, 16, 16);\n+ tcg_gen_sextract_i32(t0, t0, 0, 16);\n+ tcg_gen_sextract_i32(t3, t2, 16, 16);\n+ tcg_gen_sextract_i32(t2, t2, 0, 16);\n } else {\n- tcg_gen_extract_tl(t1, t0, 16, 16);\n- tcg_gen_extract_tl(t0, t0, 0, 16);\n- tcg_gen_extract_tl(t3, t2, 16, 16);\n- tcg_gen_extract_tl(t2, t2, 0, 16);\n+ tcg_gen_extract_i32(t1, t0, 16, 16);\n+ tcg_gen_extract_i32(t0, t0, 0, 16);\n+ tcg_gen_extract_i32(t3, t2, 16, 16);\n+ tcg_gen_extract_i32(t2, t2, 0, 16);\n }\n \n if (right) {\n if (arithmetic) {\n- tcg_gen_sar_tl(t0, t0, t5);\n- tcg_gen_sar_tl(t1, t1, t5);\n- tcg_gen_sar_tl(t2, t2, t5);\n- tcg_gen_sar_tl(t3, t3, t5);\n+ tcg_gen_sar_i32(t0, t0, t5);\n+ tcg_gen_sar_i32(t1, t1, t5);\n+ tcg_gen_sar_i32(t2, t2, t5);\n+ tcg_gen_sar_i32(t3, t3, t5);\n } else {\n- tcg_gen_shr_tl(t0, t0, t5);\n- tcg_gen_shr_tl(t1, t1, t5);\n- tcg_gen_shr_tl(t2, t2, t5);\n- tcg_gen_shr_tl(t3, t3, t5);\n+ tcg_gen_shr_i32(t0, t0, t5);\n+ tcg_gen_shr_i32(t1, t1, t5);\n+ tcg_gen_shr_i32(t2, t2, t5);\n+ tcg_gen_shr_i32(t3, t3, t5);\n }\n } else {\n- tcg_gen_shl_tl(t0, t0, t5);\n- tcg_gen_shl_tl(t1, t1, t5);\n- tcg_gen_shl_tl(t2, t2, t5);\n- tcg_gen_shl_tl(t3, t3, t5);\n+ tcg_gen_shl_i32(t0, t0, t5);\n+ tcg_gen_shl_i32(t1, t1, t5);\n+ tcg_gen_shl_i32(t2, t2, t5);\n+ tcg_gen_shl_i32(t3, t3, t5);\n }\n- tcg_gen_deposit_tl(t0, t0, t1, 16, 16);\n- tcg_gen_deposit_tl(t2, t2, t3, 16, 16);\n+ tcg_gen_deposit_i32(t0, t0, t1, 16, 16);\n+ tcg_gen_deposit_i32(t2, t2, t3, 16, 16);\n \n gen_store_mxu_gpr(t0, XRa);\n gen_store_mxu_gpr(t2, XRd);\n@@ -2195,9 +2195,9 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)\n /* exactly one operand is zero register - find which one is not...*/\n uint32_t XRx = XRb ? XRb : XRc;\n /* ...and do half-word-wise max/min with one operand 0 */\n- TCGv_i32 t0 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n TCGv_i32 t1 = tcg_constant_i32(0);\n- TCGv_i32 t2 = tcg_temp_new();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n /* the left half-word first */\n tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000);\n@@ -2226,9 +2226,9 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx)\n tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n } else {\n /* the most general case */\n- TCGv_i32 t0 = tcg_temp_new();\n- TCGv_i32 t1 = tcg_temp_new();\n- TCGv_i32 t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n /* the left half-word first */\n tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000);\n@@ -2288,9 +2288,9 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)\n /* exactly one operand is zero register - make it be the first...*/\n uint32_t XRx = XRb ? XRb : XRc;\n /* ...and do byte-wise max/min with one operand 0 */\n- TCGv_i32 t0 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n TCGv_i32 t1 = tcg_constant_i32(0);\n- TCGv_i32 t2 = tcg_temp_new();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n int32_t i;\n \n /* the leftmost byte (byte 3) first */\n@@ -2324,9 +2324,9 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx)\n tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n } else {\n /* the most general case */\n- TCGv_i32 t0 = tcg_temp_new();\n- TCGv_i32 t1 = tcg_temp_new();\n- TCGv_i32 t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n int32_t i;\n \n /* the leftmost bytes (bytes 3) first */\n@@ -2387,32 +2387,32 @@ static void gen_mxu_q8slt(DisasContext *ctx, bool sltu)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRb == XRc)) {\n /* both operands same registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t4, XRc);\n- tcg_gen_movi_tl(t2, 0);\n+ tcg_gen_movi_i32(t2, 0);\n \n for (int i = 0; i < 4; i++) {\n if (sltu) {\n- tcg_gen_extract_tl(t0, t3, 8 * i, 8);\n- tcg_gen_extract_tl(t1, t4, 8 * i, 8);\n+ tcg_gen_extract_i32(t0, t3, 8 * i, 8);\n+ tcg_gen_extract_i32(t1, t4, 8 * i, 8);\n } else {\n- tcg_gen_sextract_tl(t0, t3, 8 * i, 8);\n- tcg_gen_sextract_tl(t1, t4, 8 * i, 8);\n+ tcg_gen_sextract_i32(t0, t3, 8 * i, 8);\n+ tcg_gen_sextract_i32(t1, t4, 8 * i, 8);\n }\n- tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);\n- tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);\n+ tcg_gen_setcond_i32(TCG_COND_LT, t0, t0, t1);\n+ tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);\n }\n gen_store_mxu_gpr(t2, XRa);\n }\n@@ -2438,18 +2438,18 @@ static void gen_mxu_S32SLT(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRb == XRc)) {\n /* both operands same registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n- tcg_gen_setcond_tl(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1);\n+ tcg_gen_setcond_i32(TCG_COND_LT, mxu_gpr[XRa - 1], t0, t1);\n }\n }\n \n@@ -2474,28 +2474,28 @@ static void gen_mxu_D16SLT(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRb == XRc)) {\n /* both operands same registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t4, XRc);\n- tcg_gen_sextract_tl(t0, t3, 16, 16);\n- tcg_gen_sextract_tl(t1, t4, 16, 16);\n- tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);\n- tcg_gen_shli_tl(t2, t0, 16);\n- tcg_gen_sextract_tl(t0, t3, 0, 16);\n- tcg_gen_sextract_tl(t1, t4, 0, 16);\n- tcg_gen_setcond_tl(TCG_COND_LT, t0, t0, t1);\n- tcg_gen_or_tl(mxu_gpr[XRa - 1], t2, t0);\n+ tcg_gen_sextract_i32(t0, t3, 16, 16);\n+ tcg_gen_sextract_i32(t1, t4, 16, 16);\n+ tcg_gen_setcond_i32(TCG_COND_LT, t0, t0, t1);\n+ tcg_gen_shli_i32(t2, t0, 16);\n+ tcg_gen_sextract_i32(t0, t3, 0, 16);\n+ tcg_gen_sextract_i32(t1, t4, 0, 16);\n+ tcg_gen_setcond_i32(TCG_COND_LT, t0, t0, t1);\n+ tcg_gen_or_i32(mxu_gpr[XRa - 1], t2, t0);\n }\n }\n \n@@ -2525,36 +2525,36 @@ static void gen_mxu_d16avg(DisasContext *ctx, bool round45)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRb == XRc)) {\n /* both operands same registers -> just set destination to same */\n- tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n+ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t4, XRc);\n- tcg_gen_sextract_tl(t0, t3, 16, 16);\n- tcg_gen_sextract_tl(t1, t4, 16, 16);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_sextract_i32(t0, t3, 16, 16);\n+ tcg_gen_sextract_i32(t1, t4, 16, 16);\n+ tcg_gen_add_i32(t0, t0, t1);\n if (round45) {\n- tcg_gen_addi_tl(t0, t0, 1);\n+ tcg_gen_addi_i32(t0, t0, 1);\n }\n- tcg_gen_shli_tl(t2, t0, 15);\n- tcg_gen_andi_tl(t2, t2, 0xffff0000);\n- tcg_gen_sextract_tl(t0, t3, 0, 16);\n- tcg_gen_sextract_tl(t1, t4, 0, 16);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_shli_i32(t2, t0, 15);\n+ tcg_gen_andi_i32(t2, t2, 0xffff0000);\n+ tcg_gen_sextract_i32(t0, t3, 0, 16);\n+ tcg_gen_sextract_i32(t1, t4, 0, 16);\n+ tcg_gen_add_i32(t0, t0, t1);\n if (round45) {\n- tcg_gen_addi_tl(t0, t0, 1);\n+ tcg_gen_addi_i32(t0, t0, 1);\n }\n- tcg_gen_shri_tl(t0, t0, 1);\n- tcg_gen_deposit_tl(t2, t2, t0, 0, 16);\n+ tcg_gen_shri_i32(t0, t0, 1);\n+ tcg_gen_deposit_i32(t2, t2, t0, 0, 16);\n gen_store_mxu_gpr(t2, XRa);\n }\n }\n@@ -2585,31 +2585,31 @@ static void gen_mxu_q8avg(DisasContext *ctx, bool round45)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRb == XRc)) {\n /* both operands same registers -> just set destination to same */\n- tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n+ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t4, XRc);\n- tcg_gen_movi_tl(t2, 0);\n+ tcg_gen_movi_i32(t2, 0);\n \n for (int i = 0; i < 4; i++) {\n- tcg_gen_extract_tl(t0, t3, 8 * i, 8);\n- tcg_gen_extract_tl(t1, t4, 8 * i, 8);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_extract_i32(t0, t3, 8 * i, 8);\n+ tcg_gen_extract_i32(t1, t4, 8 * i, 8);\n+ tcg_gen_add_i32(t0, t0, t1);\n if (round45) {\n- tcg_gen_addi_tl(t0, t0, 1);\n+ tcg_gen_addi_i32(t0, t0, 1);\n }\n- tcg_gen_shri_tl(t0, t0, 1);\n- tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);\n+ tcg_gen_shri_i32(t0, t0, 1);\n+ tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);\n }\n gen_store_mxu_gpr(t2, XRa);\n }\n@@ -2636,10 +2636,10 @@ static void gen_mxu_q8movzn(DisasContext *ctx, TCGCond cond)\n XRb = extract32(ctx->opcode, 10, 4);\n XRc = extract32(ctx->opcode, 14, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n TCGLabel *l_quarterdone = gen_new_label();\n TCGLabel *l_halfdone = gen_new_label();\n TCGLabel *l_quarterrest = gen_new_label();\n@@ -2649,28 +2649,28 @@ static void gen_mxu_q8movzn(DisasContext *ctx, TCGCond cond)\n gen_load_mxu_gpr(t1, XRb);\n gen_load_mxu_gpr(t2, XRa);\n \n- tcg_gen_extract_tl(t3, t1, 24, 8);\n- tcg_gen_brcondi_tl(cond, t3, 0, l_quarterdone);\n- tcg_gen_extract_tl(t3, t0, 24, 8);\n- tcg_gen_deposit_tl(t2, t2, t3, 24, 8);\n+ tcg_gen_extract_i32(t3, t1, 24, 8);\n+ tcg_gen_brcondi_i32(cond, t3, 0, l_quarterdone);\n+ tcg_gen_extract_i32(t3, t0, 24, 8);\n+ tcg_gen_deposit_i32(t2, t2, t3, 24, 8);\n \n gen_set_label(l_quarterdone);\n- tcg_gen_extract_tl(t3, t1, 16, 8);\n- tcg_gen_brcondi_tl(cond, t3, 0, l_halfdone);\n- tcg_gen_extract_tl(t3, t0, 16, 8);\n- tcg_gen_deposit_tl(t2, t2, t3, 16, 8);\n+ tcg_gen_extract_i32(t3, t1, 16, 8);\n+ tcg_gen_brcondi_i32(cond, t3, 0, l_halfdone);\n+ tcg_gen_extract_i32(t3, t0, 16, 8);\n+ tcg_gen_deposit_i32(t2, t2, t3, 16, 8);\n \n gen_set_label(l_halfdone);\n- tcg_gen_extract_tl(t3, t1, 8, 8);\n- tcg_gen_brcondi_tl(cond, t3, 0, l_quarterrest);\n- tcg_gen_extract_tl(t3, t0, 8, 8);\n- tcg_gen_deposit_tl(t2, t2, t3, 8, 8);\n+ tcg_gen_extract_i32(t3, t1, 8, 8);\n+ tcg_gen_brcondi_i32(cond, t3, 0, l_quarterrest);\n+ tcg_gen_extract_i32(t3, t0, 8, 8);\n+ tcg_gen_deposit_i32(t2, t2, t3, 8, 8);\n \n gen_set_label(l_quarterrest);\n- tcg_gen_extract_tl(t3, t1, 0, 8);\n- tcg_gen_brcondi_tl(cond, t3, 0, l_done);\n- tcg_gen_extract_tl(t3, t0, 0, 8);\n- tcg_gen_deposit_tl(t2, t2, t3, 0, 8);\n+ tcg_gen_extract_i32(t3, t1, 0, 8);\n+ tcg_gen_brcondi_i32(cond, t3, 0, l_done);\n+ tcg_gen_extract_i32(t3, t0, 0, 8);\n+ tcg_gen_deposit_i32(t2, t2, t3, 0, 8);\n \n gen_set_label(l_done);\n gen_store_mxu_gpr(t2, XRa);\n@@ -2697,10 +2697,10 @@ static void gen_mxu_d16movzn(DisasContext *ctx, TCGCond cond)\n XRb = extract32(ctx->opcode, 10, 4);\n XRc = extract32(ctx->opcode, 14, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n TCGLabel *l_halfdone = gen_new_label();\n TCGLabel *l_done = gen_new_label();\n \n@@ -2708,16 +2708,16 @@ static void gen_mxu_d16movzn(DisasContext *ctx, TCGCond cond)\n gen_load_mxu_gpr(t1, XRb);\n gen_load_mxu_gpr(t2, XRa);\n \n- tcg_gen_extract_tl(t3, t1, 16, 16);\n- tcg_gen_brcondi_tl(cond, t3, 0, l_halfdone);\n- tcg_gen_extract_tl(t3, t0, 16, 16);\n- tcg_gen_deposit_tl(t2, t2, t3, 16, 16);\n+ tcg_gen_extract_i32(t3, t1, 16, 16);\n+ tcg_gen_brcondi_i32(cond, t3, 0, l_halfdone);\n+ tcg_gen_extract_i32(t3, t0, 16, 16);\n+ tcg_gen_deposit_i32(t2, t2, t3, 16, 16);\n \n gen_set_label(l_halfdone);\n- tcg_gen_extract_tl(t3, t1, 0, 16);\n- tcg_gen_brcondi_tl(cond, t3, 0, l_done);\n- tcg_gen_extract_tl(t3, t0, 0, 16);\n- tcg_gen_deposit_tl(t2, t2, t3, 0, 16);\n+ tcg_gen_extract_i32(t3, t1, 0, 16);\n+ tcg_gen_brcondi_i32(cond, t3, 0, l_done);\n+ tcg_gen_extract_i32(t3, t0, 0, 16);\n+ tcg_gen_deposit_i32(t2, t2, t3, 0, 16);\n \n gen_set_label(l_done);\n gen_store_mxu_gpr(t2, XRa);\n@@ -2744,14 +2744,14 @@ static void gen_mxu_s32movzn(DisasContext *ctx, TCGCond cond)\n XRb = extract32(ctx->opcode, 10, 4);\n XRc = extract32(ctx->opcode, 14, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n TCGLabel *l_done = gen_new_label();\n \n gen_load_mxu_gpr(t0, XRc);\n gen_load_mxu_gpr(t1, XRb);\n \n- tcg_gen_brcondi_tl(cond, t1, 0, l_done);\n+ tcg_gen_brcondi_i32(cond, t1, 0, l_done);\n gen_store_mxu_gpr(t0, XRa);\n gen_set_label(l_done);\n }\n@@ -2784,18 +2784,18 @@ static void gen_mxu_S32CPS(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else if (unlikely(XRb == 0)) {\n /* XRc make no sense 0 - 0 = 0 -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRc == 0)) {\n /* condition always false -> just move XRb to XRa */\n- tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n+ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n TCGLabel *l_not_less = gen_new_label();\n TCGLabel *l_done = gen_new_label();\n \n- tcg_gen_brcondi_tl(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less);\n- tcg_gen_neg_tl(t0, mxu_gpr[XRb - 1]);\n+ tcg_gen_brcondi_i32(TCG_COND_GE, mxu_gpr[XRc - 1], 0, l_not_less);\n+ tcg_gen_neg_i32(t0, mxu_gpr[XRb - 1]);\n tcg_gen_br(l_done);\n gen_set_label(l_not_less);\n gen_load_mxu_gpr(t0, XRb);\n@@ -2824,37 +2824,37 @@ static void gen_mxu_D16CPS(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else if (unlikely(XRb == 0)) {\n /* XRc make no sense 0 - 0 = 0 -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else if (unlikely(XRc == 0)) {\n /* condition always false -> just move XRb to XRa */\n- tcg_gen_mov_tl(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n+ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n TCGLabel *l_done_hi = gen_new_label();\n TCGLabel *l_not_less_lo = gen_new_label();\n TCGLabel *l_done_lo = gen_new_label();\n \n- tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 16, 16);\n- tcg_gen_sextract_tl(t1, mxu_gpr[XRb - 1], 16, 16);\n- tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_done_hi);\n- tcg_gen_subfi_tl(t1, 0, t1);\n+ tcg_gen_sextract_i32(t0, mxu_gpr[XRc - 1], 16, 16);\n+ tcg_gen_sextract_i32(t1, mxu_gpr[XRb - 1], 16, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_GE, t0, 0, l_done_hi);\n+ tcg_gen_subfi_i32(t1, 0, t1);\n \n gen_set_label(l_done_hi);\n tcg_gen_shli_i32(t1, t1, 16);\n \n- tcg_gen_sextract_tl(t0, mxu_gpr[XRc - 1], 0, 16);\n- tcg_gen_brcondi_tl(TCG_COND_GE, t0, 0, l_not_less_lo);\n- tcg_gen_sextract_tl(t0, mxu_gpr[XRb - 1], 0, 16);\n- tcg_gen_subfi_tl(t0, 0, t0);\n+ tcg_gen_sextract_i32(t0, mxu_gpr[XRc - 1], 0, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_GE, t0, 0, l_not_less_lo);\n+ tcg_gen_sextract_i32(t0, mxu_gpr[XRb - 1], 0, 16);\n+ tcg_gen_subfi_i32(t0, 0, t0);\n tcg_gen_br(l_done_lo);\n \n gen_set_label(l_not_less_lo);\n- tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 16);\n+ tcg_gen_extract_i32(t0, mxu_gpr[XRb - 1], 0, 16);\n \n gen_set_label(l_done_lo);\n- tcg_gen_deposit_tl(mxu_gpr[XRa - 1], t1, t0, 0, 16);\n+ tcg_gen_deposit_i32(mxu_gpr[XRa - 1], t1, t0, 0, 16);\n }\n }\n \n@@ -2880,27 +2880,27 @@ static void gen_mxu_Q8ABD(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t4, XRc);\n- tcg_gen_movi_tl(t2, 0);\n+ tcg_gen_movi_i32(t2, 0);\n \n for (int i = 0; i < 4; i++) {\n- tcg_gen_extract_tl(t0, t3, 8 * i, 8);\n- tcg_gen_extract_tl(t1, t4, 8 * i, 8);\n+ tcg_gen_extract_i32(t0, t3, 8 * i, 8);\n+ tcg_gen_extract_i32(t1, t4, 8 * i, 8);\n \n- tcg_gen_sub_tl(t0, t0, t1);\n- tcg_gen_abs_tl(t0, t0);\n+ tcg_gen_sub_i32(t0, t0, t1);\n+ tcg_gen_abs_i32(t0, t0);\n \n- tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);\n+ tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);\n }\n gen_store_mxu_gpr(t2, XRa);\n }\n@@ -2930,41 +2930,41 @@ static void gen_mxu_Q8ADD(DisasContext *ctx)\n tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t3, XRb);\n gen_load_mxu_gpr(t4, XRc);\n \n for (int i = 0; i < 4; i++) {\n- tcg_gen_andi_tl(t0, t3, 0xff);\n- tcg_gen_andi_tl(t1, t4, 0xff);\n+ tcg_gen_andi_i32(t0, t3, 0xff);\n+ tcg_gen_andi_i32(t1, t4, 0xff);\n \n if (i < 2) {\n if (aptn2 & 0x01) {\n- tcg_gen_sub_tl(t0, t0, t1);\n+ tcg_gen_sub_i32(t0, t0, t1);\n } else {\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_add_i32(t0, t0, t1);\n }\n } else {\n if (aptn2 & 0x02) {\n- tcg_gen_sub_tl(t0, t0, t1);\n+ tcg_gen_sub_i32(t0, t0, t1);\n } else {\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_add_i32(t0, t0, t1);\n }\n }\n if (i < 3) {\n- tcg_gen_shri_tl(t3, t3, 8);\n- tcg_gen_shri_tl(t4, t4, 8);\n+ tcg_gen_shri_i32(t3, t3, 8);\n+ tcg_gen_shri_i32(t4, t4, 8);\n }\n if (i > 0) {\n- tcg_gen_deposit_tl(t2, t2, t0, 8 * i, 8);\n+ tcg_gen_deposit_i32(t2, t2, t0, 8 * i, 8);\n } else {\n- tcg_gen_andi_tl(t0, t0, 0xff);\n- tcg_gen_mov_tl(t2, t0);\n+ tcg_gen_andi_i32(t0, t0, 0xff);\n+ tcg_gen_mov_i32(t2, t0);\n }\n }\n gen_store_mxu_gpr(t2, XRa);\n@@ -2999,19 +2999,19 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)\n if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n if (XRa != 0) {\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n }\n if (XRd != 0) {\n- tcg_gen_movi_tl(mxu_gpr[XRd - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRd - 1], 0);\n }\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n- TCGv t5 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n+ TCGv_i32 t5 = tcg_temp_new_i32();\n \n if (XRa != 0) {\n gen_extract_mxu_gpr(t0, XRb, 16, 8);\n@@ -3019,22 +3019,22 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)\n gen_extract_mxu_gpr(t2, XRb, 24, 8);\n gen_extract_mxu_gpr(t3, XRc, 24, 8);\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(t0, t0, t1);\n- tcg_gen_sub_tl(t2, t2, t3);\n+ tcg_gen_sub_i32(t0, t0, t1);\n+ tcg_gen_sub_i32(t2, t2, t3);\n } else {\n- tcg_gen_add_tl(t0, t0, t1);\n- tcg_gen_add_tl(t2, t2, t3);\n+ tcg_gen_add_i32(t0, t0, t1);\n+ tcg_gen_add_i32(t2, t2, t3);\n }\n if (accumulate) {\n gen_load_mxu_gpr(t5, XRa);\n- tcg_gen_extract_tl(t1, t5, 0, 16);\n- tcg_gen_extract_tl(t3, t5, 16, 16);\n- tcg_gen_add_tl(t0, t0, t1);\n- tcg_gen_add_tl(t2, t2, t3);\n+ tcg_gen_extract_i32(t1, t5, 0, 16);\n+ tcg_gen_extract_i32(t3, t5, 16, 16);\n+ tcg_gen_add_i32(t0, t0, t1);\n+ tcg_gen_add_i32(t2, t2, t3);\n }\n- tcg_gen_shli_tl(t2, t2, 16);\n- tcg_gen_extract_tl(t0, t0, 0, 16);\n- tcg_gen_or_tl(t4, t2, t0);\n+ tcg_gen_shli_i32(t2, t2, 16);\n+ tcg_gen_extract_i32(t0, t0, 0, 16);\n+ tcg_gen_or_i32(t4, t2, t0);\n }\n if (XRd != 0) {\n gen_extract_mxu_gpr(t0, XRb, 0, 8);\n@@ -3042,22 +3042,22 @@ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate)\n gen_extract_mxu_gpr(t2, XRb, 8, 8);\n gen_extract_mxu_gpr(t3, XRc, 8, 8);\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(t0, t0, t1);\n- tcg_gen_sub_tl(t2, t2, t3);\n+ tcg_gen_sub_i32(t0, t0, t1);\n+ tcg_gen_sub_i32(t2, t2, t3);\n } else {\n- tcg_gen_add_tl(t0, t0, t1);\n- tcg_gen_add_tl(t2, t2, t3);\n+ tcg_gen_add_i32(t0, t0, t1);\n+ tcg_gen_add_i32(t2, t2, t3);\n }\n if (accumulate) {\n gen_load_mxu_gpr(t5, XRd);\n- tcg_gen_extract_tl(t1, t5, 0, 16);\n- tcg_gen_extract_tl(t3, t5, 16, 16);\n- tcg_gen_add_tl(t0, t0, t1);\n- tcg_gen_add_tl(t2, t2, t3);\n+ tcg_gen_extract_i32(t1, t5, 0, 16);\n+ tcg_gen_extract_i32(t3, t5, 16, 16);\n+ tcg_gen_add_i32(t0, t0, t1);\n+ tcg_gen_add_i32(t2, t2, t3);\n }\n- tcg_gen_shli_tl(t2, t2, 16);\n- tcg_gen_extract_tl(t0, t0, 0, 16);\n- tcg_gen_or_tl(t5, t2, t0);\n+ tcg_gen_shli_i32(t2, t2, 16);\n+ tcg_gen_extract_i32(t0, t0, 0, 16);\n+ tcg_gen_or_i32(t5, t2, t0);\n }\n \n gen_store_mxu_gpr(t4, XRa);\n@@ -3090,46 +3090,46 @@ static void gen_mxu_d8sum(DisasContext *ctx, bool sumc)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to zero */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n- TCGv t5 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n+ TCGv_i32 t5 = tcg_temp_new_i32();\n \n if (XRb != 0) {\n- tcg_gen_extract_tl(t0, mxu_gpr[XRb - 1], 0, 8);\n- tcg_gen_extract_tl(t1, mxu_gpr[XRb - 1], 8, 8);\n- tcg_gen_extract_tl(t2, mxu_gpr[XRb - 1], 16, 8);\n- tcg_gen_extract_tl(t3, mxu_gpr[XRb - 1], 24, 8);\n- tcg_gen_add_tl(t4, t0, t1);\n- tcg_gen_add_tl(t4, t4, t2);\n- tcg_gen_add_tl(t4, t4, t3);\n+ tcg_gen_extract_i32(t0, mxu_gpr[XRb - 1], 0, 8);\n+ tcg_gen_extract_i32(t1, mxu_gpr[XRb - 1], 8, 8);\n+ tcg_gen_extract_i32(t2, mxu_gpr[XRb - 1], 16, 8);\n+ tcg_gen_extract_i32(t3, mxu_gpr[XRb - 1], 24, 8);\n+ tcg_gen_add_i32(t4, t0, t1);\n+ tcg_gen_add_i32(t4, t4, t2);\n+ tcg_gen_add_i32(t4, t4, t3);\n } else {\n- tcg_gen_mov_tl(t4, 0);\n+ tcg_gen_mov_i32(t4, 0);\n }\n if (XRc != 0) {\n- tcg_gen_extract_tl(t0, mxu_gpr[XRc - 1], 0, 8);\n- tcg_gen_extract_tl(t1, mxu_gpr[XRc - 1], 8, 8);\n- tcg_gen_extract_tl(t2, mxu_gpr[XRc - 1], 16, 8);\n- tcg_gen_extract_tl(t3, mxu_gpr[XRc - 1], 24, 8);\n- tcg_gen_add_tl(t5, t0, t1);\n- tcg_gen_add_tl(t5, t5, t2);\n- tcg_gen_add_tl(t5, t5, t3);\n+ tcg_gen_extract_i32(t0, mxu_gpr[XRc - 1], 0, 8);\n+ tcg_gen_extract_i32(t1, mxu_gpr[XRc - 1], 8, 8);\n+ tcg_gen_extract_i32(t2, mxu_gpr[XRc - 1], 16, 8);\n+ tcg_gen_extract_i32(t3, mxu_gpr[XRc - 1], 24, 8);\n+ tcg_gen_add_i32(t5, t0, t1);\n+ tcg_gen_add_i32(t5, t5, t2);\n+ tcg_gen_add_i32(t5, t5, t3);\n } else {\n- tcg_gen_mov_tl(t5, 0);\n+ tcg_gen_mov_i32(t5, 0);\n }\n \n if (sumc) {\n- tcg_gen_addi_tl(t4, t4, 2);\n- tcg_gen_addi_tl(t5, t5, 2);\n+ tcg_gen_addi_i32(t4, t4, 2);\n+ tcg_gen_addi_i32(t5, t5, 2);\n }\n- tcg_gen_shli_tl(t4, t4, 16);\n+ tcg_gen_shli_i32(t4, t4, 16);\n \n- tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5);\n+ tcg_gen_or_i32(mxu_gpr[XRa - 1], t4, t5);\n }\n }\n \n@@ -3148,74 +3148,74 @@ static void gen_mxu_q16add(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n- TCGv t5 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n+ TCGv_i32 t5 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t1, XRb);\n- tcg_gen_extract_tl(t0, t1, 0, 16);\n- tcg_gen_extract_tl(t1, t1, 16, 16);\n+ tcg_gen_extract_i32(t0, t1, 0, 16);\n+ tcg_gen_extract_i32(t1, t1, 16, 16);\n \n gen_load_mxu_gpr(t3, XRc);\n- tcg_gen_extract_tl(t2, t3, 0, 16);\n- tcg_gen_extract_tl(t3, t3, 16, 16);\n+ tcg_gen_extract_i32(t2, t3, 0, 16);\n+ tcg_gen_extract_i32(t3, t3, 16, 16);\n \n switch (optn2) {\n case MXU_OPTN2_WW: /* XRB.H+XRC.H == lop, XRB.L+XRC.L == rop */\n- tcg_gen_mov_tl(t4, t1);\n- tcg_gen_mov_tl(t5, t0);\n+ tcg_gen_mov_i32(t4, t1);\n+ tcg_gen_mov_i32(t5, t0);\n break;\n case MXU_OPTN2_LW: /* XRB.L+XRC.H == lop, XRB.L+XRC.L == rop */\n- tcg_gen_mov_tl(t4, t0);\n- tcg_gen_mov_tl(t5, t0);\n+ tcg_gen_mov_i32(t4, t0);\n+ tcg_gen_mov_i32(t5, t0);\n break;\n case MXU_OPTN2_HW: /* XRB.H+XRC.H == lop, XRB.H+XRC.L == rop */\n- tcg_gen_mov_tl(t4, t1);\n- tcg_gen_mov_tl(t5, t1);\n+ tcg_gen_mov_i32(t4, t1);\n+ tcg_gen_mov_i32(t5, t1);\n break;\n case MXU_OPTN2_XW: /* XRB.L+XRC.H == lop, XRB.H+XRC.L == rop */\n- tcg_gen_mov_tl(t4, t0);\n- tcg_gen_mov_tl(t5, t1);\n+ tcg_gen_mov_i32(t4, t0);\n+ tcg_gen_mov_i32(t5, t1);\n break;\n }\n \n switch (aptn2) {\n case MXU_APTN2_AA: /* lop +, rop + */\n- tcg_gen_add_tl(t0, t4, t3);\n- tcg_gen_add_tl(t1, t5, t2);\n- tcg_gen_add_tl(t4, t4, t3);\n- tcg_gen_add_tl(t5, t5, t2);\n+ tcg_gen_add_i32(t0, t4, t3);\n+ tcg_gen_add_i32(t1, t5, t2);\n+ tcg_gen_add_i32(t4, t4, t3);\n+ tcg_gen_add_i32(t5, t5, t2);\n break;\n case MXU_APTN2_AS: /* lop +, rop + */\n- tcg_gen_sub_tl(t0, t4, t3);\n- tcg_gen_sub_tl(t1, t5, t2);\n- tcg_gen_add_tl(t4, t4, t3);\n- tcg_gen_add_tl(t5, t5, t2);\n+ tcg_gen_sub_i32(t0, t4, t3);\n+ tcg_gen_sub_i32(t1, t5, t2);\n+ tcg_gen_add_i32(t4, t4, t3);\n+ tcg_gen_add_i32(t5, t5, t2);\n break;\n case MXU_APTN2_SA: /* lop +, rop + */\n- tcg_gen_add_tl(t0, t4, t3);\n- tcg_gen_add_tl(t1, t5, t2);\n- tcg_gen_sub_tl(t4, t4, t3);\n- tcg_gen_sub_tl(t5, t5, t2);\n+ tcg_gen_add_i32(t0, t4, t3);\n+ tcg_gen_add_i32(t1, t5, t2);\n+ tcg_gen_sub_i32(t4, t4, t3);\n+ tcg_gen_sub_i32(t5, t5, t2);\n break;\n case MXU_APTN2_SS: /* lop +, rop + */\n- tcg_gen_sub_tl(t0, t4, t3);\n- tcg_gen_sub_tl(t1, t5, t2);\n- tcg_gen_sub_tl(t4, t4, t3);\n- tcg_gen_sub_tl(t5, t5, t2);\n+ tcg_gen_sub_i32(t0, t4, t3);\n+ tcg_gen_sub_i32(t1, t5, t2);\n+ tcg_gen_sub_i32(t4, t4, t3);\n+ tcg_gen_sub_i32(t5, t5, t2);\n break;\n }\n \n- tcg_gen_shli_tl(t0, t0, 16);\n- tcg_gen_extract_tl(t1, t1, 0, 16);\n- tcg_gen_shli_tl(t4, t4, 16);\n- tcg_gen_extract_tl(t5, t5, 0, 16);\n+ tcg_gen_shli_i32(t0, t0, 16);\n+ tcg_gen_extract_i32(t1, t1, 0, 16);\n+ tcg_gen_shli_i32(t4, t4, 16);\n+ tcg_gen_extract_i32(t5, t5, 0, 16);\n \n- tcg_gen_or_tl(mxu_gpr[XRa - 1], t4, t5);\n- tcg_gen_or_tl(mxu_gpr[XRd - 1], t0, t1);\n+ tcg_gen_or_i32(mxu_gpr[XRa - 1], t4, t5);\n+ tcg_gen_or_i32(mxu_gpr[XRd - 1], t0, t1);\n }\n \n /*\n@@ -3232,66 +3232,66 @@ static void gen_mxu_q16acc(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv s3 = tcg_temp_new();\n- TCGv s2 = tcg_temp_new();\n- TCGv s1 = tcg_temp_new();\n- TCGv s0 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 s3 = tcg_temp_new_i32();\n+ TCGv_i32 s2 = tcg_temp_new_i32();\n+ TCGv_i32 s1 = tcg_temp_new_i32();\n+ TCGv_i32 s0 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t1, XRb);\n- tcg_gen_extract_tl(t0, t1, 0, 16);\n- tcg_gen_extract_tl(t1, t1, 16, 16);\n+ tcg_gen_extract_i32(t0, t1, 0, 16);\n+ tcg_gen_extract_i32(t1, t1, 16, 16);\n \n gen_load_mxu_gpr(t3, XRc);\n- tcg_gen_extract_tl(t2, t3, 0, 16);\n- tcg_gen_extract_tl(t3, t3, 16, 16);\n+ tcg_gen_extract_i32(t2, t3, 0, 16);\n+ tcg_gen_extract_i32(t3, t3, 16, 16);\n \n switch (aptn2) {\n case MXU_APTN2_AA: /* lop +, rop + */\n- tcg_gen_add_tl(s3, t1, t3);\n- tcg_gen_add_tl(s2, t0, t2);\n- tcg_gen_add_tl(s1, t1, t3);\n- tcg_gen_add_tl(s0, t0, t2);\n+ tcg_gen_add_i32(s3, t1, t3);\n+ tcg_gen_add_i32(s2, t0, t2);\n+ tcg_gen_add_i32(s1, t1, t3);\n+ tcg_gen_add_i32(s0, t0, t2);\n break;\n case MXU_APTN2_AS: /* lop +, rop - */\n- tcg_gen_sub_tl(s3, t1, t3);\n- tcg_gen_sub_tl(s2, t0, t2);\n- tcg_gen_add_tl(s1, t1, t3);\n- tcg_gen_add_tl(s0, t0, t2);\n+ tcg_gen_sub_i32(s3, t1, t3);\n+ tcg_gen_sub_i32(s2, t0, t2);\n+ tcg_gen_add_i32(s1, t1, t3);\n+ tcg_gen_add_i32(s0, t0, t2);\n break;\n case MXU_APTN2_SA: /* lop -, rop + */\n- tcg_gen_add_tl(s3, t1, t3);\n- tcg_gen_add_tl(s2, t0, t2);\n- tcg_gen_sub_tl(s1, t1, t3);\n- tcg_gen_sub_tl(s0, t0, t2);\n+ tcg_gen_add_i32(s3, t1, t3);\n+ tcg_gen_add_i32(s2, t0, t2);\n+ tcg_gen_sub_i32(s1, t1, t3);\n+ tcg_gen_sub_i32(s0, t0, t2);\n break;\n case MXU_APTN2_SS: /* lop -, rop - */\n- tcg_gen_sub_tl(s3, t1, t3);\n- tcg_gen_sub_tl(s2, t0, t2);\n- tcg_gen_sub_tl(s1, t1, t3);\n- tcg_gen_sub_tl(s0, t0, t2);\n+ tcg_gen_sub_i32(s3, t1, t3);\n+ tcg_gen_sub_i32(s2, t0, t2);\n+ tcg_gen_sub_i32(s1, t1, t3);\n+ tcg_gen_sub_i32(s0, t0, t2);\n break;\n }\n \n if (XRa != 0) {\n- tcg_gen_add_tl(t0, mxu_gpr[XRa - 1], s0);\n- tcg_gen_extract_tl(t0, t0, 0, 16);\n- tcg_gen_extract_tl(t1, mxu_gpr[XRa - 1], 16, 16);\n- tcg_gen_add_tl(t1, t1, s1);\n- tcg_gen_shli_tl(t1, t1, 16);\n- tcg_gen_or_tl(mxu_gpr[XRa - 1], t1, t0);\n+ tcg_gen_add_i32(t0, mxu_gpr[XRa - 1], s0);\n+ tcg_gen_extract_i32(t0, t0, 0, 16);\n+ tcg_gen_extract_i32(t1, mxu_gpr[XRa - 1], 16, 16);\n+ tcg_gen_add_i32(t1, t1, s1);\n+ tcg_gen_shli_i32(t1, t1, 16);\n+ tcg_gen_or_i32(mxu_gpr[XRa - 1], t1, t0);\n }\n \n if (XRd != 0) {\n- tcg_gen_add_tl(t0, mxu_gpr[XRd - 1], s2);\n- tcg_gen_extract_tl(t0, t0, 0, 16);\n- tcg_gen_extract_tl(t1, mxu_gpr[XRd - 1], 16, 16);\n- tcg_gen_add_tl(t1, t1, s3);\n- tcg_gen_shli_tl(t1, t1, 16);\n- tcg_gen_or_tl(mxu_gpr[XRd - 1], t1, t0);\n+ tcg_gen_add_i32(t0, mxu_gpr[XRd - 1], s2);\n+ tcg_gen_extract_i32(t0, t0, 0, 16);\n+ tcg_gen_extract_i32(t1, mxu_gpr[XRd - 1], 16, 16);\n+ tcg_gen_add_i32(t1, t1, s3);\n+ tcg_gen_shli_i32(t1, t1, 16);\n+ tcg_gen_or_i32(mxu_gpr[XRd - 1], t1, t0);\n }\n }\n \n@@ -3309,58 +3309,58 @@ static void gen_mxu_q16accm(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t2, XRb);\n gen_load_mxu_gpr(t3, XRc);\n \n if (XRa != 0) {\n- TCGv a0 = tcg_temp_new();\n- TCGv a1 = tcg_temp_new();\n+ TCGv_i32 a0 = tcg_temp_new_i32();\n+ TCGv_i32 a1 = tcg_temp_new_i32();\n \n- tcg_gen_extract_tl(t0, t2, 0, 16);\n- tcg_gen_extract_tl(t1, t2, 16, 16);\n+ tcg_gen_extract_i32(t0, t2, 0, 16);\n+ tcg_gen_extract_i32(t1, t2, 16, 16);\n \n gen_load_mxu_gpr(a1, XRa);\n- tcg_gen_extract_tl(a0, a1, 0, 16);\n- tcg_gen_extract_tl(a1, a1, 16, 16);\n+ tcg_gen_extract_i32(a0, a1, 0, 16);\n+ tcg_gen_extract_i32(a1, a1, 16, 16);\n \n if (aptn2 & 2) {\n- tcg_gen_sub_tl(a0, a0, t0);\n- tcg_gen_sub_tl(a1, a1, t1);\n+ tcg_gen_sub_i32(a0, a0, t0);\n+ tcg_gen_sub_i32(a1, a1, t1);\n } else {\n- tcg_gen_add_tl(a0, a0, t0);\n- tcg_gen_add_tl(a1, a1, t1);\n+ tcg_gen_add_i32(a0, a0, t0);\n+ tcg_gen_add_i32(a1, a1, t1);\n }\n- tcg_gen_extract_tl(a0, a0, 0, 16);\n- tcg_gen_shli_tl(a1, a1, 16);\n- tcg_gen_or_tl(mxu_gpr[XRa - 1], a1, a0);\n+ tcg_gen_extract_i32(a0, a0, 0, 16);\n+ tcg_gen_shli_i32(a1, a1, 16);\n+ tcg_gen_or_i32(mxu_gpr[XRa - 1], a1, a0);\n }\n \n if (XRd != 0) {\n- TCGv a0 = tcg_temp_new();\n- TCGv a1 = tcg_temp_new();\n+ TCGv_i32 a0 = tcg_temp_new_i32();\n+ TCGv_i32 a1 = tcg_temp_new_i32();\n \n- tcg_gen_extract_tl(t0, t3, 0, 16);\n- tcg_gen_extract_tl(t1, t3, 16, 16);\n+ tcg_gen_extract_i32(t0, t3, 0, 16);\n+ tcg_gen_extract_i32(t1, t3, 16, 16);\n \n gen_load_mxu_gpr(a1, XRd);\n- tcg_gen_extract_tl(a0, a1, 0, 16);\n- tcg_gen_extract_tl(a1, a1, 16, 16);\n+ tcg_gen_extract_i32(a0, a1, 0, 16);\n+ tcg_gen_extract_i32(a1, a1, 16, 16);\n \n if (aptn2 & 1) {\n- tcg_gen_sub_tl(a0, a0, t0);\n- tcg_gen_sub_tl(a1, a1, t1);\n+ tcg_gen_sub_i32(a0, a0, t0);\n+ tcg_gen_sub_i32(a1, a1, t1);\n } else {\n- tcg_gen_add_tl(a0, a0, t0);\n- tcg_gen_add_tl(a1, a1, t1);\n+ tcg_gen_add_i32(a0, a0, t0);\n+ tcg_gen_add_i32(a1, a1, t1);\n }\n- tcg_gen_extract_tl(a0, a0, 0, 16);\n- tcg_gen_shli_tl(a1, a1, 16);\n- tcg_gen_or_tl(mxu_gpr[XRd - 1], a1, a0);\n+ tcg_gen_extract_i32(a0, a0, 0, 16);\n+ tcg_gen_shli_i32(a1, a1, 16);\n+ tcg_gen_or_i32(mxu_gpr[XRd - 1], a1, a0);\n }\n }\n \n@@ -3379,33 +3379,33 @@ static void gen_mxu_d16asum(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t2, XRb);\n gen_load_mxu_gpr(t3, XRc);\n \n if (XRa != 0) {\n- tcg_gen_sextract_tl(t0, t2, 0, 16);\n- tcg_gen_sextract_tl(t1, t2, 16, 16);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_sextract_i32(t0, t2, 0, 16);\n+ tcg_gen_sextract_i32(t1, t2, 16, 16);\n+ tcg_gen_add_i32(t0, t0, t1);\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n+ tcg_gen_sub_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n } else {\n- tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n+ tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n }\n }\n \n if (XRd != 0) {\n- tcg_gen_sextract_tl(t0, t3, 0, 16);\n- tcg_gen_sextract_tl(t1, t3, 16, 16);\n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_sextract_i32(t0, t3, 0, 16);\n+ tcg_gen_sextract_i32(t1, t3, 16, 16);\n+ tcg_gen_add_i32(t0, t0, t1);\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);\n+ tcg_gen_sub_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);\n } else {\n- tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);\n+ tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t0);\n }\n }\n }\n@@ -3428,10 +3428,10 @@ static void gen_mxu_d32add(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv cr = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 cr = tcg_temp_new_i32();\n \n if (unlikely(addc > 1)) {\n /* opcode incorrect -> do nothing */\n@@ -3445,14 +3445,14 @@ static void gen_mxu_d32add(DisasContext *ctx)\n gen_load_mxu_gpr(t1, XRc);\n gen_load_mxu_cr(cr);\n if (XRa != 0) {\n- tcg_gen_extract_tl(t2, cr, 31, 1);\n- tcg_gen_add_tl(t0, t0, t2);\n- tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n+ tcg_gen_extract_i32(t2, cr, 31, 1);\n+ tcg_gen_add_i32(t0, t0, t2);\n+ tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n }\n if (XRd != 0) {\n- tcg_gen_extract_tl(t2, cr, 30, 1);\n- tcg_gen_add_tl(t1, t1, t2);\n- tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);\n+ tcg_gen_extract_i32(t2, cr, 30, 1);\n+ tcg_gen_add_i32(t1, t1, t2);\n+ tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);\n }\n }\n } else if (unlikely(XRa == 0 && XRd == 0)) {\n@@ -3460,7 +3460,7 @@ static void gen_mxu_d32add(DisasContext *ctx)\n } else {\n /* common case */\n /* FIXME ??? What if XRa == XRd ??? */\n- TCGv carry = tcg_temp_new();\n+ TCGv_i32 carry = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n@@ -3468,27 +3468,27 @@ static void gen_mxu_d32add(DisasContext *ctx)\n if (XRa != 0) {\n if (aptn2 & 2) {\n tcg_gen_sub_i32(t2, t0, t1);\n- tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t1);\n+ tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t1);\n } else {\n tcg_gen_add_i32(t2, t0, t1);\n- tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t2);\n+ tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t2);\n }\n- tcg_gen_andi_tl(cr, cr, 0x7fffffff);\n- tcg_gen_shli_tl(carry, carry, 31);\n- tcg_gen_or_tl(cr, cr, carry);\n+ tcg_gen_andi_i32(cr, cr, 0x7fffffff);\n+ tcg_gen_shli_i32(carry, carry, 31);\n+ tcg_gen_or_i32(cr, cr, carry);\n gen_store_mxu_gpr(t2, XRa);\n }\n if (XRd != 0) {\n if (aptn2 & 1) {\n tcg_gen_sub_i32(t2, t0, t1);\n- tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t1);\n+ tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t1);\n } else {\n tcg_gen_add_i32(t2, t0, t1);\n- tcg_gen_setcond_tl(TCG_COND_GTU, carry, t0, t2);\n+ tcg_gen_setcond_i32(TCG_COND_GTU, carry, t0, t2);\n }\n- tcg_gen_andi_tl(cr, cr, 0xbfffffff);\n- tcg_gen_shli_tl(carry, carry, 30);\n- tcg_gen_or_tl(cr, cr, carry);\n+ tcg_gen_andi_i32(cr, cr, 0xbfffffff);\n+ tcg_gen_shli_i32(carry, carry, 30);\n+ tcg_gen_or_i32(cr, cr, carry);\n gen_store_mxu_gpr(t2, XRd);\n }\n gen_store_mxu_cr(cr);\n@@ -3509,9 +3509,9 @@ static void gen_mxu_d32acc(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n if (unlikely(XRa == 0 && XRd == 0)) {\n /* destinations are zero register -> do nothing */\n@@ -3521,19 +3521,19 @@ static void gen_mxu_d32acc(DisasContext *ctx)\n gen_load_mxu_gpr(t1, XRc);\n if (XRa != 0) {\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(t2, t0, t1);\n+ tcg_gen_sub_i32(t2, t0, t1);\n } else {\n- tcg_gen_add_tl(t2, t0, t1);\n+ tcg_gen_add_i32(t2, t0, t1);\n }\n- tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);\n+ tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);\n }\n if (XRd != 0) {\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(t2, t0, t1);\n+ tcg_gen_sub_i32(t2, t0, t1);\n } else {\n- tcg_gen_add_tl(t2, t0, t1);\n+ tcg_gen_add_i32(t2, t0, t1);\n }\n- tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);\n+ tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);\n }\n }\n }\n@@ -3552,9 +3552,9 @@ static void gen_mxu_d32accm(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n if (unlikely(XRa == 0 && XRd == 0)) {\n /* destinations are zero register -> do nothing */\n@@ -3563,19 +3563,19 @@ static void gen_mxu_d32accm(DisasContext *ctx)\n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n if (XRa != 0) {\n- tcg_gen_add_tl(t2, t0, t1);\n+ tcg_gen_add_i32(t2, t0, t1);\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);\n+ tcg_gen_sub_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);\n } else {\n- tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);\n+ tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t2);\n }\n }\n if (XRd != 0) {\n- tcg_gen_sub_tl(t2, t0, t1);\n+ tcg_gen_sub_i32(t2, t0, t1);\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);\n+ tcg_gen_sub_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);\n } else {\n- tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);\n+ tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t2);\n }\n }\n }\n@@ -3595,8 +3595,8 @@ static void gen_mxu_d32asum(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n \n if (unlikely(XRa == 0 && XRd == 0)) {\n /* destinations are zero register -> do nothing */\n@@ -3606,16 +3606,16 @@ static void gen_mxu_d32asum(DisasContext *ctx)\n gen_load_mxu_gpr(t1, XRc);\n if (XRa != 0) {\n if (aptn2 & 2) {\n- tcg_gen_sub_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n+ tcg_gen_sub_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n } else {\n- tcg_gen_add_tl(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n+ tcg_gen_add_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0);\n }\n }\n if (XRd != 0) {\n if (aptn2 & 1) {\n- tcg_gen_sub_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);\n+ tcg_gen_sub_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);\n } else {\n- tcg_gen_add_tl(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);\n+ tcg_gen_add_i32(mxu_gpr[XRd - 1], mxu_gpr[XRd - 1], t1);\n }\n }\n }\n@@ -3638,13 +3638,13 @@ static void gen_mxu_d32asum(DisasContext *ctx)\n */\n static void gen_mxu_s32extr(DisasContext *ctx)\n {\n- TCGv t0, t1, t2, t3;\n+ TCGv_i32 t0, t1, t2, t3;\n uint32_t XRa, XRd, rs, bits5;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n \n XRa = extract32(ctx->opcode, 6, 4);\n XRd = extract32(ctx->opcode, 10, 4);\n@@ -3660,23 +3660,23 @@ static void gen_mxu_s32extr(DisasContext *ctx)\n gen_load_mxu_gpr(t0, XRd);\n gen_load_mxu_gpr(t1, XRa);\n gen_load_gpr(t2, rs);\n- tcg_gen_andi_tl(t2, t2, 0x1f);\n- tcg_gen_subfi_tl(t2, 32, t2);\n- tcg_gen_brcondi_tl(TCG_COND_GE, t2, bits5, l_xra_only);\n- tcg_gen_subfi_tl(t2, bits5, t2);\n- tcg_gen_subfi_tl(t3, 32, t2);\n- tcg_gen_shr_tl(t0, t0, t3);\n- tcg_gen_shl_tl(t1, t1, t2);\n- tcg_gen_or_tl(t0, t0, t1);\n+ tcg_gen_andi_i32(t2, t2, 0x1f);\n+ tcg_gen_subfi_i32(t2, 32, t2);\n+ tcg_gen_brcondi_i32(TCG_COND_GE, t2, bits5, l_xra_only);\n+ tcg_gen_subfi_i32(t2, bits5, t2);\n+ tcg_gen_subfi_i32(t3, 32, t2);\n+ tcg_gen_shr_i32(t0, t0, t3);\n+ tcg_gen_shl_i32(t1, t1, t2);\n+ tcg_gen_or_i32(t0, t0, t1);\n tcg_gen_br(l_done);\n gen_set_label(l_xra_only);\n- tcg_gen_subi_tl(t2, t2, bits5);\n- tcg_gen_shr_tl(t0, t1, t2);\n+ tcg_gen_subi_i32(t2, t2, bits5);\n+ tcg_gen_shr_i32(t0, t1, t2);\n gen_set_label(l_done);\n- tcg_gen_extract_tl(t0, t0, 0, bits5);\n+ tcg_gen_extract_i32(t0, t0, 0, bits5);\n } else {\n /* unspecified behavior but matches tests on real hardware*/\n- tcg_gen_movi_tl(t0, 0);\n+ tcg_gen_movi_i32(t0, 0);\n }\n gen_store_mxu_gpr(t0, XRa);\n }\n@@ -3688,14 +3688,14 @@ static void gen_mxu_s32extr(DisasContext *ctx)\n */\n static void gen_mxu_s32extrv(DisasContext *ctx)\n {\n- TCGv t0, t1, t2, t3, t4;\n+ TCGv_i32 t0, t1, t2, t3, t4;\n uint32_t XRa, XRd, rs, rt;\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n- t2 = tcg_temp_new();\n- t3 = tcg_temp_new();\n- t4 = tcg_temp_new();\n+ t0 = tcg_temp_new_i32();\n+ t1 = tcg_temp_new_i32();\n+ t2 = tcg_temp_new_i32();\n+ t3 = tcg_temp_new_i32();\n+ t4 = tcg_temp_new_i32();\n TCGLabel *l_xra_only = gen_new_label();\n TCGLabel *l_done = gen_new_label();\n TCGLabel *l_zero = gen_new_label();\n@@ -3711,32 +3711,32 @@ static void gen_mxu_s32extrv(DisasContext *ctx)\n gen_load_mxu_gpr(t1, XRa);\n gen_load_gpr(t2, rs);\n gen_load_gpr(t4, rt);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t4, 0, l_zero);\n- tcg_gen_andi_tl(t2, t2, 0x1f);\n- tcg_gen_subfi_tl(t2, 32, t2);\n- tcg_gen_brcond_tl(TCG_COND_GE, t2, t4, l_xra_only);\n- tcg_gen_sub_tl(t2, t4, t2);\n- tcg_gen_subfi_tl(t3, 32, t2);\n- tcg_gen_shr_tl(t0, t0, t3);\n- tcg_gen_shl_tl(t1, t1, t2);\n- tcg_gen_or_tl(t0, t0, t1);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t4, 0, l_zero);\n+ tcg_gen_andi_i32(t2, t2, 0x1f);\n+ tcg_gen_subfi_i32(t2, 32, t2);\n+ tcg_gen_brcond_i32(TCG_COND_GE, t2, t4, l_xra_only);\n+ tcg_gen_sub_i32(t2, t4, t2);\n+ tcg_gen_subfi_i32(t3, 32, t2);\n+ tcg_gen_shr_i32(t0, t0, t3);\n+ tcg_gen_shl_i32(t1, t1, t2);\n+ tcg_gen_or_i32(t0, t0, t1);\n tcg_gen_br(l_extract);\n \n gen_set_label(l_xra_only);\n- tcg_gen_sub_tl(t2, t2, t4);\n- tcg_gen_shr_tl(t0, t1, t2);\n+ tcg_gen_sub_i32(t2, t2, t4);\n+ tcg_gen_shr_i32(t0, t1, t2);\n tcg_gen_br(l_extract);\n \n /* unspecified behavior but matches tests on real hardware*/\n gen_set_label(l_zero);\n- tcg_gen_movi_tl(t0, 0);\n+ tcg_gen_movi_i32(t0, 0);\n tcg_gen_br(l_done);\n \n /* {XRa} = extract({tmp}, 0, rt) */\n gen_set_label(l_extract);\n- tcg_gen_subfi_tl(t4, 32, t4);\n- tcg_gen_shl_tl(t0, t0, t4);\n- tcg_gen_shr_tl(t0, t0, t4);\n+ tcg_gen_subfi_i32(t4, 32, t4);\n+ tcg_gen_shl_i32(t0, t0, t4);\n+ tcg_gen_shr_i32(t0, t0, t4);\n \n gen_set_label(l_done);\n gen_store_mxu_gpr(t0, XRa);\n@@ -3762,33 +3762,33 @@ static void gen_mxu_s32lui(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else {\n uint32_t s16;\n- TCGv t0 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n \n switch (optn3) {\n case 0:\n- tcg_gen_movi_tl(t0, s8);\n+ tcg_gen_movi_i32(t0, s8);\n break;\n case 1:\n- tcg_gen_movi_tl(t0, s8 << 8);\n+ tcg_gen_movi_i32(t0, s8 << 8);\n break;\n case 2:\n- tcg_gen_movi_tl(t0, s8 << 16);\n+ tcg_gen_movi_i32(t0, s8 << 16);\n break;\n case 3:\n- tcg_gen_movi_tl(t0, s8 << 24);\n+ tcg_gen_movi_i32(t0, s8 << 24);\n break;\n case 4:\n- tcg_gen_movi_tl(t0, (s8 << 16) | s8);\n+ tcg_gen_movi_i32(t0, (s8 << 16) | s8);\n break;\n case 5:\n- tcg_gen_movi_tl(t0, (s8 << 24) | (s8 << 8));\n+ tcg_gen_movi_i32(t0, (s8 << 24) | (s8 << 8));\n break;\n case 6:\n s16 = (uint16_t)(int16_t)(int8_t)s8;\n- tcg_gen_movi_tl(t0, (s16 << 16) | s16);\n+ tcg_gen_movi_i32(t0, (s16 << 16) | s16);\n break;\n case 7:\n- tcg_gen_movi_tl(t0, (s8 << 24) | (s8 << 16) | (s8 << 8) | s8);\n+ tcg_gen_movi_i32(t0, (s8 << 24) | (s8 << 16) | (s8 << 8) | s8);\n break;\n }\n gen_store_mxu_gpr(t0, XRa);\n@@ -3816,11 +3816,11 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n \n- tcg_gen_movi_tl(t2, 0);\n+ tcg_gen_movi_i32(t2, 0);\n if (XRb != 0) {\n TCGLabel *l_less_hi = gen_new_label();\n TCGLabel *l_less_lo = gen_new_label();\n@@ -3829,32 +3829,32 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)\n TCGLabel *l_greater_lo = gen_new_label();\n TCGLabel *l_done = gen_new_label();\n \n- tcg_gen_sari_tl(t0, mxu_gpr[XRb - 1], 16);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi);\n- tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi);\n+ tcg_gen_sari_i32(t0, mxu_gpr[XRb - 1], 16);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t0, 0, l_less_hi);\n+ tcg_gen_brcondi_i32(TCG_COND_GT, t0, 255, l_greater_hi);\n tcg_gen_br(l_lo);\n gen_set_label(l_less_hi);\n- tcg_gen_movi_tl(t0, 0);\n+ tcg_gen_movi_i32(t0, 0);\n tcg_gen_br(l_lo);\n gen_set_label(l_greater_hi);\n- tcg_gen_movi_tl(t0, 255);\n+ tcg_gen_movi_i32(t0, 255);\n \n gen_set_label(l_lo);\n- tcg_gen_shli_tl(t1, mxu_gpr[XRb - 1], 16);\n- tcg_gen_sari_tl(t1, t1, 16);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);\n- tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);\n+ tcg_gen_shli_i32(t1, mxu_gpr[XRb - 1], 16);\n+ tcg_gen_sari_i32(t1, t1, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t1, 0, l_less_lo);\n+ tcg_gen_brcondi_i32(TCG_COND_GT, t1, 255, l_greater_lo);\n tcg_gen_br(l_done);\n gen_set_label(l_less_lo);\n- tcg_gen_movi_tl(t1, 0);\n+ tcg_gen_movi_i32(t1, 0);\n tcg_gen_br(l_done);\n gen_set_label(l_greater_lo);\n- tcg_gen_movi_tl(t1, 255);\n+ tcg_gen_movi_i32(t1, 255);\n \n gen_set_label(l_done);\n- tcg_gen_shli_tl(t2, t0, 24);\n- tcg_gen_shli_tl(t1, t1, 16);\n- tcg_gen_or_tl(t2, t2, t1);\n+ tcg_gen_shli_i32(t2, t0, 24);\n+ tcg_gen_shli_i32(t1, t1, 16);\n+ tcg_gen_or_i32(t2, t2, t1);\n }\n \n if (XRc != 0) {\n@@ -3865,32 +3865,32 @@ static void gen_mxu_Q16SAT(DisasContext *ctx)\n TCGLabel *l_greater_lo = gen_new_label();\n TCGLabel *l_done = gen_new_label();\n \n- tcg_gen_sari_tl(t0, mxu_gpr[XRc - 1], 16);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t0, 0, l_less_hi);\n- tcg_gen_brcondi_tl(TCG_COND_GT, t0, 255, l_greater_hi);\n+ tcg_gen_sari_i32(t0, mxu_gpr[XRc - 1], 16);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t0, 0, l_less_hi);\n+ tcg_gen_brcondi_i32(TCG_COND_GT, t0, 255, l_greater_hi);\n tcg_gen_br(l_lo);\n gen_set_label(l_less_hi);\n- tcg_gen_movi_tl(t0, 0);\n+ tcg_gen_movi_i32(t0, 0);\n tcg_gen_br(l_lo);\n gen_set_label(l_greater_hi);\n- tcg_gen_movi_tl(t0, 255);\n+ tcg_gen_movi_i32(t0, 255);\n \n gen_set_label(l_lo);\n- tcg_gen_shli_tl(t1, mxu_gpr[XRc - 1], 16);\n- tcg_gen_sari_tl(t1, t1, 16);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l_less_lo);\n- tcg_gen_brcondi_tl(TCG_COND_GT, t1, 255, l_greater_lo);\n+ tcg_gen_shli_i32(t1, mxu_gpr[XRc - 1], 16);\n+ tcg_gen_sari_i32(t1, t1, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t1, 0, l_less_lo);\n+ tcg_gen_brcondi_i32(TCG_COND_GT, t1, 255, l_greater_lo);\n tcg_gen_br(l_done);\n gen_set_label(l_less_lo);\n- tcg_gen_movi_tl(t1, 0);\n+ tcg_gen_movi_i32(t1, 0);\n tcg_gen_br(l_done);\n gen_set_label(l_greater_lo);\n- tcg_gen_movi_tl(t1, 255);\n+ tcg_gen_movi_i32(t1, 255);\n \n gen_set_label(l_done);\n- tcg_gen_shli_tl(t0, t0, 8);\n- tcg_gen_or_tl(t2, t2, t0);\n- tcg_gen_or_tl(t2, t2, t1);\n+ tcg_gen_shli_i32(t0, t0, 8);\n+ tcg_gen_or_i32(t2, t2, t0);\n+ tcg_gen_or_i32(t2, t2, t1);\n }\n gen_store_mxu_gpr(t2, XRa);\n }\n@@ -3910,11 +3910,11 @@ static void gen_mxu_q16scop(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n \n TCGLabel *l_b_hi_lt = gen_new_label();\n TCGLabel *l_b_hi_gt = gen_new_label();\n@@ -3930,47 +3930,47 @@ static void gen_mxu_q16scop(DisasContext *ctx)\n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n \n- tcg_gen_sextract_tl(t2, t0, 16, 16);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_hi_lt);\n- tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_b_hi_gt);\n- tcg_gen_movi_tl(t3, 0);\n+ tcg_gen_sextract_i32(t2, t0, 16, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_b_hi_lt);\n+ tcg_gen_brcondi_i32(TCG_COND_GT, t2, 0, l_b_hi_gt);\n+ tcg_gen_movi_i32(t3, 0);\n tcg_gen_br(l_b_lo);\n gen_set_label(l_b_hi_lt);\n- tcg_gen_movi_tl(t3, 0xffff0000);\n+ tcg_gen_movi_i32(t3, 0xffff0000);\n tcg_gen_br(l_b_lo);\n gen_set_label(l_b_hi_gt);\n- tcg_gen_movi_tl(t3, 0x00010000);\n+ tcg_gen_movi_i32(t3, 0x00010000);\n \n gen_set_label(l_b_lo);\n- tcg_gen_sextract_tl(t2, t0, 0, 16);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_c_hi);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_b_lo_lt);\n- tcg_gen_ori_tl(t3, t3, 0x00000001);\n+ tcg_gen_sextract_i32(t2, t0, 0, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l_c_hi);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_b_lo_lt);\n+ tcg_gen_ori_i32(t3, t3, 0x00000001);\n tcg_gen_br(l_c_hi);\n gen_set_label(l_b_lo_lt);\n- tcg_gen_ori_tl(t3, t3, 0x0000ffff);\n+ tcg_gen_ori_i32(t3, t3, 0x0000ffff);\n tcg_gen_br(l_c_hi);\n \n gen_set_label(l_c_hi);\n- tcg_gen_sextract_tl(t2, t1, 16, 16);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_hi_lt);\n- tcg_gen_brcondi_tl(TCG_COND_GT, t2, 0, l_c_hi_gt);\n- tcg_gen_movi_tl(t4, 0);\n+ tcg_gen_sextract_i32(t2, t1, 16, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_c_hi_lt);\n+ tcg_gen_brcondi_i32(TCG_COND_GT, t2, 0, l_c_hi_gt);\n+ tcg_gen_movi_i32(t4, 0);\n tcg_gen_br(l_c_lo);\n gen_set_label(l_c_hi_lt);\n- tcg_gen_movi_tl(t4, 0xffff0000);\n+ tcg_gen_movi_i32(t4, 0xffff0000);\n tcg_gen_br(l_c_lo);\n gen_set_label(l_c_hi_gt);\n- tcg_gen_movi_tl(t4, 0x00010000);\n+ tcg_gen_movi_i32(t4, 0x00010000);\n \n gen_set_label(l_c_lo);\n- tcg_gen_sextract_tl(t2, t1, 0, 16);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_done);\n- tcg_gen_brcondi_tl(TCG_COND_LT, t2, 0, l_c_lo_lt);\n- tcg_gen_ori_tl(t4, t4, 0x00000001);\n+ tcg_gen_sextract_i32(t2, t1, 0, 16);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l_done);\n+ tcg_gen_brcondi_i32(TCG_COND_LT, t2, 0, l_c_lo_lt);\n+ tcg_gen_ori_i32(t4, t4, 0x00000001);\n tcg_gen_br(l_done);\n gen_set_label(l_c_lo_lt);\n- tcg_gen_ori_tl(t4, t4, 0x0000ffff);\n+ tcg_gen_ori_i32(t4, t4, 0x0000ffff);\n \n gen_set_label(l_done);\n gen_store_mxu_gpr(t3, XRa);\n@@ -3991,62 +3991,62 @@ static void gen_mxu_s32sfl(DisasContext *ctx)\n XRa = extract32(ctx->opcode, 6, 4);\n ptn2 = extract32(ctx->opcode, 24, 2);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n \n switch (ptn2) {\n case 0:\n- tcg_gen_andi_tl(t2, t0, 0xff000000);\n- tcg_gen_andi_tl(t3, t1, 0x000000ff);\n- tcg_gen_deposit_tl(t3, t3, t0, 8, 8);\n- tcg_gen_shri_tl(t0, t0, 8);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t3, t3, t0, 24, 8);\n- tcg_gen_deposit_tl(t3, t3, t1, 16, 8);\n- tcg_gen_shri_tl(t0, t0, 8);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t2, t2, t0, 8, 8);\n- tcg_gen_deposit_tl(t2, t2, t1, 0, 8);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t2, t2, t1, 16, 8);\n+ tcg_gen_andi_i32(t2, t0, 0xff000000);\n+ tcg_gen_andi_i32(t3, t1, 0x000000ff);\n+ tcg_gen_deposit_i32(t3, t3, t0, 8, 8);\n+ tcg_gen_shri_i32(t0, t0, 8);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t3, t3, t0, 24, 8);\n+ tcg_gen_deposit_i32(t3, t3, t1, 16, 8);\n+ tcg_gen_shri_i32(t0, t0, 8);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t2, t2, t0, 8, 8);\n+ tcg_gen_deposit_i32(t2, t2, t1, 0, 8);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t2, t2, t1, 16, 8);\n break;\n case 1:\n- tcg_gen_andi_tl(t2, t0, 0xff000000);\n- tcg_gen_andi_tl(t3, t1, 0x000000ff);\n- tcg_gen_deposit_tl(t3, t3, t0, 16, 8);\n- tcg_gen_shri_tl(t0, t0, 8);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t2, t2, t0, 16, 8);\n- tcg_gen_deposit_tl(t2, t2, t1, 0, 8);\n- tcg_gen_shri_tl(t0, t0, 8);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t3, t3, t0, 24, 8);\n- tcg_gen_deposit_tl(t3, t3, t1, 8, 8);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t2, t2, t1, 8, 8);\n+ tcg_gen_andi_i32(t2, t0, 0xff000000);\n+ tcg_gen_andi_i32(t3, t1, 0x000000ff);\n+ tcg_gen_deposit_i32(t3, t3, t0, 16, 8);\n+ tcg_gen_shri_i32(t0, t0, 8);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t2, t2, t0, 16, 8);\n+ tcg_gen_deposit_i32(t2, t2, t1, 0, 8);\n+ tcg_gen_shri_i32(t0, t0, 8);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t3, t3, t0, 24, 8);\n+ tcg_gen_deposit_i32(t3, t3, t1, 8, 8);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t2, t2, t1, 8, 8);\n break;\n case 2:\n- tcg_gen_andi_tl(t2, t0, 0xff00ff00);\n- tcg_gen_andi_tl(t3, t1, 0x00ff00ff);\n- tcg_gen_deposit_tl(t3, t3, t0, 8, 8);\n- tcg_gen_shri_tl(t0, t0, 16);\n- tcg_gen_shri_tl(t1, t1, 8);\n- tcg_gen_deposit_tl(t2, t2, t1, 0, 8);\n- tcg_gen_deposit_tl(t3, t3, t0, 24, 8);\n- tcg_gen_shri_tl(t1, t1, 16);\n- tcg_gen_deposit_tl(t2, t2, t1, 16, 8);\n+ tcg_gen_andi_i32(t2, t0, 0xff00ff00);\n+ tcg_gen_andi_i32(t3, t1, 0x00ff00ff);\n+ tcg_gen_deposit_i32(t3, t3, t0, 8, 8);\n+ tcg_gen_shri_i32(t0, t0, 16);\n+ tcg_gen_shri_i32(t1, t1, 8);\n+ tcg_gen_deposit_i32(t2, t2, t1, 0, 8);\n+ tcg_gen_deposit_i32(t3, t3, t0, 24, 8);\n+ tcg_gen_shri_i32(t1, t1, 16);\n+ tcg_gen_deposit_i32(t2, t2, t1, 16, 8);\n break;\n case 3:\n- tcg_gen_andi_tl(t2, t0, 0xffff0000);\n- tcg_gen_andi_tl(t3, t1, 0x0000ffff);\n- tcg_gen_shri_tl(t1, t1, 16);\n- tcg_gen_deposit_tl(t2, t2, t1, 0, 16);\n- tcg_gen_deposit_tl(t3, t3, t0, 16, 16);\n+ tcg_gen_andi_i32(t2, t0, 0xffff0000);\n+ tcg_gen_andi_i32(t3, t1, 0x0000ffff);\n+ tcg_gen_shri_i32(t1, t1, 16);\n+ tcg_gen_deposit_i32(t2, t2, t1, 0, 16);\n+ tcg_gen_deposit_i32(t3, t3, t0, 16, 16);\n break;\n }\n \n@@ -4067,30 +4067,30 @@ static void gen_mxu_q8sad(DisasContext *ctx)\n XRb = extract32(ctx->opcode, 10, 4);\n XRa = extract32(ctx->opcode, 6, 4);\n \n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n- TCGv t4 = tcg_temp_new();\n- TCGv t5 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n+ TCGv_i32 t4 = tcg_temp_new_i32();\n+ TCGv_i32 t5 = tcg_temp_new_i32();\n \n gen_load_mxu_gpr(t2, XRb);\n gen_load_mxu_gpr(t3, XRc);\n gen_load_mxu_gpr(t5, XRd);\n- tcg_gen_movi_tl(t4, 0);\n+ tcg_gen_movi_i32(t4, 0);\n \n for (int i = 0; i < 4; i++) {\n- tcg_gen_andi_tl(t0, t2, 0xff);\n- tcg_gen_andi_tl(t1, t3, 0xff);\n- tcg_gen_sub_tl(t0, t0, t1);\n- tcg_gen_abs_tl(t0, t0);\n- tcg_gen_add_tl(t4, t4, t0);\n+ tcg_gen_andi_i32(t0, t2, 0xff);\n+ tcg_gen_andi_i32(t1, t3, 0xff);\n+ tcg_gen_sub_i32(t0, t0, t1);\n+ tcg_gen_abs_i32(t0, t0);\n+ tcg_gen_add_i32(t4, t4, t0);\n if (i < 3) {\n- tcg_gen_shri_tl(t2, t2, 8);\n- tcg_gen_shri_tl(t3, t3, 8);\n+ tcg_gen_shri_i32(t2, t2, 8);\n+ tcg_gen_shri_i32(t3, t3, 8);\n }\n }\n- tcg_gen_add_tl(t5, t5, t4);\n+ tcg_gen_add_i32(t5, t5, t4);\n gen_store_mxu_gpr(t4, XRa);\n gen_store_mxu_gpr(t5, XRd);\n }\n@@ -4196,8 +4196,8 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)\n /* XRa */\n /* */\n \n- TCGv_i32 t0 = tcg_temp_new();\n- TCGv_i32 t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n \n tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF);\n tcg_gen_shli_i32(t0, t0, 8);\n@@ -4219,8 +4219,8 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)\n /* XRa */\n /* */\n \n- TCGv_i32 t0 = tcg_temp_new();\n- TCGv_i32 t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n \n tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF);\n tcg_gen_shli_i32(t0, t0, 16);\n@@ -4242,8 +4242,8 @@ static void gen_mxu_S32ALNI(DisasContext *ctx)\n /* XRa */\n /* */\n \n- TCGv_i32 t0 = tcg_temp_new();\n- TCGv_i32 t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n \n tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF);\n tcg_gen_shli_i32(t0, t0, 24);\n@@ -4290,13 +4290,13 @@ static void gen_mxu_S32ALN(DisasContext *ctx)\n /* destination is zero register -> do nothing */\n } else if (unlikely((XRb == 0) && (XRc == 0))) {\n /* both operands zero registers -> just set destination to all 0s */\n- tcg_gen_movi_tl(mxu_gpr[XRa - 1], 0);\n+ tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0);\n } else {\n /* the most general case */\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n- TCGv t2 = tcg_temp_new();\n- TCGv t3 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n+ TCGv_i32 t2 = tcg_temp_new_i32();\n+ TCGv_i32 t3 = tcg_temp_new_i32();\n TCGLabel *l_exit = gen_new_label();\n TCGLabel *l_b_only = gen_new_label();\n TCGLabel *l_c_only = gen_new_label();\n@@ -4304,20 +4304,20 @@ static void gen_mxu_S32ALN(DisasContext *ctx)\n gen_load_mxu_gpr(t0, XRb);\n gen_load_mxu_gpr(t1, XRc);\n gen_load_gpr(t2, rs);\n- tcg_gen_andi_tl(t2, t2, 0x07);\n+ tcg_gen_andi_i32(t2, t2, 0x07);\n \n /* do nothing for undefined cases */\n- tcg_gen_brcondi_tl(TCG_COND_GE, t2, 5, l_exit);\n+ tcg_gen_brcondi_i32(TCG_COND_GE, t2, 5, l_exit);\n \n- tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l_b_only);\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 4, l_c_only);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l_b_only);\n+ tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 4, l_c_only);\n \n- tcg_gen_shli_tl(t2, t2, 3);\n- tcg_gen_subfi_tl(t3, 32, t2);\n+ tcg_gen_shli_i32(t2, t2, 3);\n+ tcg_gen_subfi_i32(t3, 32, t2);\n \n- tcg_gen_shl_tl(t0, t0, t2);\n- tcg_gen_shr_tl(t1, t1, t3);\n- tcg_gen_or_tl(mxu_gpr[XRa - 1], t0, t1);\n+ tcg_gen_shl_i32(t0, t0, t2);\n+ tcg_gen_shr_i32(t1, t1, t3);\n+ tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1);\n tcg_gen_br(l_exit);\n \n gen_set_label(l_b_only);\n@@ -4359,8 +4359,8 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)\n } else if (unlikely(XRa == 0 && XRd == 0)) {\n /* do nothing because result just dropped */\n } else {\n- TCGv t0 = tcg_temp_new();\n- TCGv t1 = tcg_temp_new();\n+ TCGv_i32 t0 = tcg_temp_new_i32();\n+ TCGv_i32 t1 = tcg_temp_new_i32();\n TCGv_i64 t2 = tcg_temp_new_i64();\n TCGv_i64 t3 = tcg_temp_new_i64();\n \n@@ -4368,18 +4368,18 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)\n gen_load_gpr(t1, Rc);\n \n if (uns) {\n- tcg_gen_extu_tl_i64(t2, t0);\n- tcg_gen_extu_tl_i64(t3, t1);\n+ tcg_gen_extu_i32_i64(t2, t0);\n+ tcg_gen_extu_i32_i64(t3, t1);\n } else {\n- tcg_gen_ext_tl_i64(t2, t0);\n- tcg_gen_ext_tl_i64(t3, t1);\n+ tcg_gen_ext_i32_i64(t2, t0);\n+ tcg_gen_ext_i32_i64(t3, t1);\n }\n tcg_gen_mul_i64(t2, t2, t3);\n \n gen_load_mxu_gpr(t0, XRa);\n gen_load_mxu_gpr(t1, XRd);\n \n- tcg_gen_concat_tl_i64(t3, t1, t0);\n+ tcg_gen_concat_i32_i64(t3, t1, t0);\n if (sub) {\n tcg_gen_sub_i64(t3, t3, t2);\n } else {\n@@ -4388,8 +4388,8 @@ static void gen_mxu_s32madd_sub(DisasContext *ctx, bool sub, bool uns)\n gen_move_low32(t1, t3);\n gen_move_high32(t0, t3);\n \n- tcg_gen_mov_tl(cpu_HI[0], t0);\n- tcg_gen_mov_tl(cpu_LO[0], t1);\n+ tcg_gen_mov_i32(cpu_HI[0], t0);\n+ tcg_gen_mov_i32(cpu_LO[0], t1);\n \n gen_store_mxu_gpr(t1, XRd);\n gen_store_mxu_gpr(t0, XRa);\n@@ -4936,12 +4936,12 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)\n }\n \n {\n- TCGv t_mxu_cr = tcg_temp_new();\n+ TCGv_i32 t_mxu_cr = tcg_temp_new_i32();\n TCGLabel *l_exit = gen_new_label();\n \n gen_load_mxu_cr(t_mxu_cr);\n- tcg_gen_andi_tl(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);\n- tcg_gen_brcondi_tl(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);\n+ tcg_gen_andi_i32(t_mxu_cr, t_mxu_cr, MXU_CR_MXU_EN);\n+ tcg_gen_brcondi_i32(TCG_COND_NE, t_mxu_cr, MXU_CR_MXU_EN, l_exit);\n \n switch (opcode) {\n case OPC_MXU_S32MADD:\n", "prefixes": [ "PATCH-for-11.1", "1/2" ] }