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GET /api/patches/2218616/?format=api
{ "id": 2218616, "url": "http://patchwork.ozlabs.org/api/patches/2218616/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401144503.80510-3-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401144503.80510-3-philmd@linaro.org>", "list_archive_url": null, "date": "2026-04-01T14:45:02", "name": "[PATCH-for-11.1,2/2] target/mips: Expand TCGv type for 64-bit extensions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3c7a7aad25e2a28b1f5b93880418910f469e82f2", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401144503.80510-3-philmd@linaro.org/mbox/", "series": [ { "id": 498345, "url": "http://patchwork.ozlabs.org/api/series/498345/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498345", "date": "2026-04-01T14:45:00", "name": "target/mips: Expand TCGv for fixed wordsize extensions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498345/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218616/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218616/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZRQfdpgJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32f;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "These TX79, Octeon and Loongarch extensions are only built\nas 64-bit, so TCGv expands to TCGv_i64. Use the latter which\nis more explicit. Mechanical changes.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/lcsr_translate.c | 16 +++---\n target/mips/tcg/loong_translate.c | 92 +++++++++++++++---------------\n target/mips/tcg/octeon_translate.c | 60 +++++++++----------\n target/mips/tcg/tx79_translate.c | 14 ++---\n 4 files changed, 91 insertions(+), 91 deletions(-)", "diff": "diff --git a/target/mips/tcg/lcsr_translate.c b/target/mips/tcg/lcsr_translate.c\nindex 352b0f43282..128c17a9181 100644\n--- a/target/mips/tcg/lcsr_translate.c\n+++ b/target/mips/tcg/lcsr_translate.c\n@@ -18,8 +18,8 @@\n \n static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)\n {\n- TCGv dest = tcg_temp_new();\n- TCGv src1 = tcg_temp_new();\n+ TCGv_i64 dest = tcg_temp_new_i64();\n+ TCGv_i64 src1 = tcg_temp_new_i64();\n \n gen_load_gpr(src1, a->rs);\n gen_helper_lcsr_cpucfg(dest, tcg_env, src1);\n@@ -30,10 +30,10 @@ static bool trans_CPUCFG(DisasContext *ctx, arg_CPUCFG *a)\n \n #ifndef CONFIG_USER_ONLY\n static bool gen_rdcsr(DisasContext *ctx, arg_r *a,\n- void (*func)(TCGv, TCGv_ptr, TCGv))\n+ void (*func)(TCGv_i64, TCGv_ptr, TCGv_i64))\n {\n- TCGv dest = tcg_temp_new();\n- TCGv src1 = tcg_temp_new();\n+ TCGv_i64 dest = tcg_temp_new_i64();\n+ TCGv_i64 src1 = tcg_temp_new_i64();\n \n check_cp0_enabled(ctx);\n gen_load_gpr(src1, a->rs);\n@@ -44,10 +44,10 @@ static bool gen_rdcsr(DisasContext *ctx, arg_r *a,\n }\n \n static bool gen_wrcsr(DisasContext *ctx, arg_r *a,\n- void (*func)(TCGv_ptr, TCGv, TCGv))\n+ void (*func)(TCGv_ptr, TCGv_i64, TCGv_i64))\n {\n- TCGv val = tcg_temp_new();\n- TCGv addr = tcg_temp_new();\n+ TCGv_i64 val = tcg_temp_new_i64();\n+ TCGv_i64 addr = tcg_temp_new_i64();\n \n check_cp0_enabled(ctx);\n gen_load_gpr(addr, a->rs);\ndiff --git a/target/mips/tcg/loong_translate.c b/target/mips/tcg/loong_translate.c\nindex 7d74cc34f8a..797e3b5f721 100644\n--- a/target/mips/tcg/loong_translate.c\n+++ b/target/mips/tcg/loong_translate.c\n@@ -28,7 +28,7 @@\n static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,\n bool is_double)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n TCGLabel *l1, *l2, *l3;\n \n if (rd == 0) {\n@@ -36,8 +36,8 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n l1 = gen_new_label();\n l2 = gen_new_label();\n l3 = gen_new_label();\n@@ -46,23 +46,23 @@ static bool gen_lext_DIV_G(DisasContext *s, int rd, int rs, int rt,\n gen_load_gpr(t1, rt);\n \n if (!is_double) {\n- tcg_gen_ext32s_tl(t0, t0);\n- tcg_gen_ext32s_tl(t1, t1);\n+ tcg_gen_ext32s_i64(t0, t0);\n+ tcg_gen_ext32s_i64(t1, t1);\n }\n- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);\n- tcg_gen_movi_tl(cpu_gpr[rd], 0);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1);\n+ tcg_gen_movi_i64(cpu_gpr[rd], 0);\n tcg_gen_br(l3);\n gen_set_label(l1);\n \n- tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);\n- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);\n- tcg_gen_mov_tl(cpu_gpr[rd], t0);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t1, -1LL, l2);\n+ tcg_gen_mov_i64(cpu_gpr[rd], t0);\n \n tcg_gen_br(l3);\n gen_set_label(l2);\n- tcg_gen_div_tl(cpu_gpr[rd], t0, t1);\n+ tcg_gen_div_i64(cpu_gpr[rd], t0, t1);\n if (!is_double) {\n- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);\n+ tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);\n }\n gen_set_label(l3);\n \n@@ -82,7 +82,7 @@ static bool trans_DDIV_G(DisasContext *s, arg_muldiv *a)\n static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,\n bool is_double)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n TCGLabel *l1, *l2;\n \n if (rd == 0) {\n@@ -90,8 +90,8 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n l1 = gen_new_label();\n l2 = gen_new_label();\n \n@@ -99,17 +99,17 @@ static bool gen_lext_DIVU_G(DisasContext *s, int rd, int rs, int rt,\n gen_load_gpr(t1, rt);\n \n if (!is_double) {\n- tcg_gen_ext32u_tl(t0, t0);\n- tcg_gen_ext32u_tl(t1, t1);\n+ tcg_gen_ext32u_i64(t0, t0);\n+ tcg_gen_ext32u_i64(t1, t1);\n }\n- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);\n- tcg_gen_movi_tl(cpu_gpr[rd], 0);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1);\n+ tcg_gen_movi_i64(cpu_gpr[rd], 0);\n \n tcg_gen_br(l2);\n gen_set_label(l1);\n- tcg_gen_divu_tl(cpu_gpr[rd], t0, t1);\n+ tcg_gen_divu_i64(cpu_gpr[rd], t0, t1);\n if (!is_double) {\n- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);\n+ tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);\n }\n gen_set_label(l2);\n \n@@ -129,7 +129,7 @@ static bool trans_DDIVU_G(DisasContext *s, arg_muldiv *a)\n static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,\n bool is_double)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n TCGLabel *l1, *l2, *l3;\n \n if (rd == 0) {\n@@ -137,8 +137,8 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n l1 = gen_new_label();\n l2 = gen_new_label();\n l3 = gen_new_label();\n@@ -147,19 +147,19 @@ static bool gen_lext_MOD_G(DisasContext *s, int rd, int rs, int rt,\n gen_load_gpr(t1, rt);\n \n if (!is_double) {\n- tcg_gen_ext32u_tl(t0, t0);\n- tcg_gen_ext32u_tl(t1, t1);\n+ tcg_gen_ext32u_i64(t0, t0);\n+ tcg_gen_ext32u_i64(t1, t1);\n }\n- tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);\n- tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);\n- tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2);\n+ tcg_gen_brcondi_i64(TCG_COND_EQ, t1, 0, l1);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t1, -1LL, l2);\n gen_set_label(l1);\n- tcg_gen_movi_tl(cpu_gpr[rd], 0);\n+ tcg_gen_movi_i64(cpu_gpr[rd], 0);\n tcg_gen_br(l3);\n gen_set_label(l2);\n- tcg_gen_rem_tl(cpu_gpr[rd], t0, t1);\n+ tcg_gen_rem_i64(cpu_gpr[rd], t0, t1);\n if (!is_double) {\n- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);\n+ tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);\n }\n gen_set_label(l3);\n \n@@ -179,7 +179,7 @@ static bool trans_DMOD_G(DisasContext *s, arg_muldiv *a)\n static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,\n bool is_double)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n TCGLabel *l1, *l2;\n \n if (rd == 0) {\n@@ -187,8 +187,8 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n l1 = gen_new_label();\n l2 = gen_new_label();\n \n@@ -196,16 +196,16 @@ static bool gen_lext_MODU_G(DisasContext *s, int rd, int rs, int rt,\n gen_load_gpr(t1, rt);\n \n if (!is_double) {\n- tcg_gen_ext32u_tl(t0, t0);\n- tcg_gen_ext32u_tl(t1, t1);\n+ tcg_gen_ext32u_i64(t0, t0);\n+ tcg_gen_ext32u_i64(t1, t1);\n }\n- tcg_gen_brcondi_tl(TCG_COND_NE, t1, 0, l1);\n- tcg_gen_movi_tl(cpu_gpr[rd], 0);\n+ tcg_gen_brcondi_i64(TCG_COND_NE, t1, 0, l1);\n+ tcg_gen_movi_i64(cpu_gpr[rd], 0);\n tcg_gen_br(l2);\n gen_set_label(l1);\n- tcg_gen_remu_tl(cpu_gpr[rd], t0, t1);\n+ tcg_gen_remu_i64(cpu_gpr[rd], t0, t1);\n if (!is_double) {\n- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);\n+ tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);\n }\n gen_set_label(l2);\n \n@@ -225,22 +225,22 @@ static bool trans_DMODU_G(DisasContext *s, arg_muldiv *a)\n static bool gen_lext_MULT_G(DisasContext *s, int rd, int rs, int rt,\n bool is_double)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n \n if (rd == 0) {\n /* Treat as NOP. */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n \n gen_load_gpr(t0, rs);\n gen_load_gpr(t1, rt);\n \n- tcg_gen_mul_tl(cpu_gpr[rd], t0, t1);\n+ tcg_gen_mul_i64(cpu_gpr[rd], t0, t1);\n if (!is_double) {\n- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);\n+ tcg_gen_ext32s_i64(cpu_gpr[rd], cpu_gpr[rd]);\n }\n \n return true;\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex b2eca29e06c..e1f52d444aa 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -15,7 +15,7 @@\n \n static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n {\n- TCGv p;\n+ TCGv_i64 p;\n \n if (ctx->hflags & MIPS_HFLAG_BMASK) {\n LOG_DISAS(\"Branch in delay / forbidden slot at PC 0x%\" VADDR_PRIx \"\\n\",\n@@ -25,14 +25,14 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n }\n \n /* Load needed operands */\n- TCGv t0 = tcg_temp_new();\n+ TCGv_i64 t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n \n- p = tcg_constant_tl(1ULL << a->p);\n+ p = tcg_constant_i64(1ULL << a->p);\n if (a->set) {\n- tcg_gen_and_tl(bcond, p, t0);\n+ tcg_gen_and_i64(bcond, p, t0);\n } else {\n- tcg_gen_andc_tl(bcond, p, t0);\n+ tcg_gen_andc_i64(bcond, p, t0);\n }\n \n ctx->hflags |= MIPS_HFLAG_BC;\n@@ -43,34 +43,34 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n \n static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n- tcg_gen_add_tl(t0, t0, t1);\n+ tcg_gen_add_i64(t0, t0, t1);\n tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);\n return true;\n }\n \n static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n@@ -80,97 +80,97 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n \n static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n- tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1);\n+ tcg_gen_sextract_i64(t0, t0, a->p, a->lenm1 + 1);\n gen_store_gpr(t0, a->rt);\n return true;\n }\n \n static bool trans_CINS(DisasContext *ctx, arg_CINS *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n- tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1);\n+ tcg_gen_deposit_z_i64(t0, t0, a->p, a->lenm1 + 1);\n gen_store_gpr(t0, a->rt);\n return true;\n }\n \n static bool trans_POP(DisasContext *ctx, arg_POP *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rd == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n if (!a->dw) {\n tcg_gen_andi_i64(t0, t0, 0xffffffff);\n }\n- tcg_gen_ctpop_tl(t0, t0);\n+ tcg_gen_ctpop_i64(t0, t0);\n gen_store_gpr(t0, a->rd);\n return true;\n }\n \n static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)\n {\n- TCGv t0, t1;\n+ TCGv_i64 t0, t1;\n \n if (a->rd == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n- t1 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n+ t1 = tcg_temp_new_i64();\n \n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n if (a->ne) {\n- tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);\n+ tcg_gen_setcond_i64(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);\n } else {\n- tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);\n+ tcg_gen_setcond_i64(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);\n }\n return true;\n }\n \n static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)\n {\n- TCGv t0;\n+ TCGv_i64 t0;\n \n if (a->rt == 0) {\n /* nop */\n return true;\n }\n \n- t0 = tcg_temp_new();\n+ t0 = tcg_temp_new_i64();\n \n gen_load_gpr(t0, a->rs);\n \n /* Sign-extend to 64 bit value */\n target_ulong imm = a->imm;\n if (a->ne) {\n- tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);\n+ tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);\n } else {\n- tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);\n+ tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);\n }\n return true;\n }\ndiff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c\nindex ae3f5e19c43..e071c867631 100644\n--- a/target/mips/tcg/tx79_translate.c\n+++ b/target/mips/tcg/tx79_translate.c\n@@ -241,8 +241,8 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_r *a,\n return true;\n }\n \n- c0 = tcg_constant_tl(0);\n- c1 = tcg_constant_tl(0xffffffff);\n+ c0 = tcg_constant_i64(0);\n+ c1 = tcg_constant_i64(0xffffffff);\n ax = tcg_temp_new_i64();\n bx = tcg_temp_new_i64();\n t0 = tcg_temp_new_i64();\n@@ -322,7 +322,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_r *a)\n static bool trans_LQ(DisasContext *ctx, arg_i *a)\n {\n TCGv_i64 t0;\n- TCGv addr;\n+ TCGv_i64 addr;\n \n if (a->rt == 0) {\n /* nop */\n@@ -330,14 +330,14 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)\n }\n \n t0 = tcg_temp_new_i64();\n- addr = tcg_temp_new();\n+ addr = tcg_temp_new_i64();\n \n gen_base_offset_addr(ctx, addr, a->base, a->offset);\n /*\n * Clear least-significant four bits of the effective\n * address, effectively creating an aligned address.\n */\n- tcg_gen_andi_tl(addr, addr, ~0xf);\n+ tcg_gen_andi_i64(addr, addr, ~0xf);\n \n /* Lower half */\n tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ);\n@@ -353,14 +353,14 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a)\n static bool trans_SQ(DisasContext *ctx, arg_i *a)\n {\n TCGv_i64 t0 = tcg_temp_new_i64();\n- TCGv addr = tcg_temp_new();\n+ TCGv_i64 addr = tcg_temp_new_i64();\n \n gen_base_offset_addr(ctx, addr, a->base, a->offset);\n /*\n * Clear least-significant four bits of the effective\n * address, effectively creating an aligned address.\n */\n- tcg_gen_andi_tl(addr, addr, ~0xf);\n+ tcg_gen_andi_i64(addr, addr, ~0xf);\n \n /* Lower half */\n gen_load_gpr(t0, a->rt);\n", "prefixes": [ "PATCH-for-11.1", "2/2" ] }