Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2218610,
    "url": "http://patchwork.ozlabs.org/api/patches/2218610/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260401-casey-ccf-clk-prep-v2-5-16a78c8c62da@linaro.org/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260401-casey-ccf-clk-prep-v2-5-16a78c8c62da@linaro.org>",
    "list_archive_url": null,
    "date": "2026-04-01T14:34:06",
    "name": "[v2,5/7] clk: make clk_set_rate() return signed long",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "cd9e21977260d6dcd2bb6cefd9a900e72ce30a0a",
    "submitter": {
        "id": 90679,
        "url": "http://patchwork.ozlabs.org/api/people/90679/?format=api",
        "name": "Casey Connolly",
        "email": "casey.connolly@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260401-casey-ccf-clk-prep-v2-5-16a78c8c62da@linaro.org/mbox/",
    "series": [
        {
            "id": 498343,
            "url": "http://patchwork.ozlabs.org/api/series/498343/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498343",
            "date": "2026-04-01T14:34:02",
            "name": "clk: prepare for adding Linux CCF port",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/498343/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2218610/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2218610/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=G03r6Qkt;\n\tdkim-atps=neutral",
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)",
            "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=linaro.org",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de",
            "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.b=\"G03r6Qkt\";\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=linaro.org",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=casey.connolly@linaro.org"
        ],
        "Received": [
            "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fm6w73dV1z1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 01:35:19 +1100 (AEDT)",
            "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 847AF840CC;\n\tWed,  1 Apr 2026 16:34:27 +0200 (CEST)",
            "by phobos.denx.de (Postfix, from userid 109)\n id 9C1968416C; Wed,  1 Apr 2026 16:34:24 +0200 (CEST)",
            "from mail-wm1-x332.google.com (mail-wm1-x332.google.com\n [IPv6:2a00:1450:4864:20::332])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 6117B840F1\n for <u-boot@lists.denx.de>; Wed,  1 Apr 2026 16:34:20 +0200 (CEST)",
            "by mail-wm1-x332.google.com with SMTP id\n 5b1f17b1804b1-486fba7ce4cso70491815e9.3\n for <u-boot@lists.denx.de>; Wed, 01 Apr 2026 07:34:20 -0700 (PDT)",
            "from lion.localdomain (p4fc3dd86.dip0.t-ipconnect.de.\n [79.195.221.134]) by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-4887e80a63esm161821795e9.3.2026.04.01.07.34.17\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 01 Apr 2026 07:34:18 -0700 (PDT)"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1775054060; x=1775658860; darn=lists.denx.de;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to; bh=mqHNYPVGvK2xTZXxwkkIIA5SBhwPjAjo5zpVcjpL3GQ=;\n b=G03r6Qktj8mBwdevjyfTrIMwdhZ4aeBG2HjX26i6g0QW0jXddHh6Dg1z/2jjYsxy6a\n mM3xveFRMBuQc1DgNhyQ/W8AEkR2lYclWJk+ezDodhIhWmSLpHnBokwwzxst7JNoWgQO\n xRx6dtcX/IxQGHKLRP7mdTcOrLpSglv6MEncD+rTtAZWnRXifwRbkF9CGrLn7CKarqV8\n zU5d/1/QJq9ybGVt5xdPzxIGvTWaKwMCGGFB8e0B0zkwTsps7lPukYg+mMCCbhWTySmw\n uy7WYUxb6tuRcje2eCf7Xy6KhboGgiXhFsFRCNuQYRBdgrPiuU2427BDH3Ork3YEb3Q4\n aAQQ==",
        "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775054060; x=1775658860;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=mqHNYPVGvK2xTZXxwkkIIA5SBhwPjAjo5zpVcjpL3GQ=;\n b=cCUG8+cukYnENPqHUKhHO93ihXPY/ppaBymFt4vZxLXqaW0YfCT5e+fAh8onG70Rad\n NgyiC2XJfk2REu+8FRoKScuutXut/5IKpMiB2QyBY36by9n9/IjFeNGYourZr6waLaCP\n /hlCfIegXLTY9QStkJgCOi+Bk2y4HO8MFbrsivoI2Jwt7MMSzQ6MgGsD1TD7lyPU1+s6\n 17DTtdFbA4K6sE9v7DdBVNJqCCXYguuyOXwEYXV/1tzjIbA7tOgcqpOIbatBQ768IEuT\n xq4Wz/UvXw6Rpf+zEYDKC6gnHBnkI/buAFoS5Zs7Ok61vZPLnY7dPle37uHDh4cB5PC/\n ooZQ==",
        "X-Forwarded-Encrypted": "i=1;\n AJvYcCVWm/gILAoHkbD7aLhO12t5Sk5ltEoBC8wGkYzNpL3rJAonAab/xBj4EwV8bewxZY2By1CMU2o=@lists.denx.de",
        "X-Gm-Message-State": "AOJu0YznO64S55tOyC5zOKZZk9FvjEvDOzFMnK4pdUSFuA9TJotnpmaU\n BKDyiTalEBeuKhuX1BuGSyMzmcPv+gegAhrzQKwlm6zQj861k2WOR1mli3kWgbHCt8E=",
        "X-Gm-Gg": "ATEYQzxl7wuU4YvwlIoxBJhdJw0VeZNwQaj1LtlFe8cBCTu7PIOcdGTt+v7vwCrpcJL\n QW22vQ+p8KtZvs0P8LVMAQ8l6Z2th+78L97ueI2hR6fLdJV+mXPBTi9fxnkCi75xLZ8ttXWrnuY\n 8xbj4t7VySyWFn0cbJYtl+MWJGUdkS48pMDMFCtRaBMrEonDVQtQMJedM6mJxDUDqNWw+iXqsZU\n CWflSf4pjUxk7AlIGSl/rrd4m5f+19DLt0zFbReMBhL2c8TfBi+NyHecsSdDMllv9JLXu3h7tUP\n IVVWwiJQOxB8ePv2yMQJPj8WM9+6fu2OwxxZBhWiuJYHu9OWZZNttwSW4YglR2JXyEm1O6g72RG\n cG4p/Ph+/n1L6IYej36HbaIX3360AeSSYG0TRPOh/m0pv8cc4OU3IvHm3NuPTFh3NVF4QndaYmt\n xcDFv78eYTcwY+oV6bvoKHtqtmNsqzI/Y04e0XX1VzF6+WTmYblE96Sl6fj+R1ddSJPIwE",
        "X-Received": "by 2002:a05:600c:4b23:b0:488:869c:ed9e with SMTP id\n 5b1f17b1804b1-488869ceee8mr24472465e9.23.1775054058951;\n Wed, 01 Apr 2026 07:34:18 -0700 (PDT)",
        "From": "Casey Connolly <casey.connolly@linaro.org>",
        "Date": "Wed, 01 Apr 2026 16:34:06 +0200",
        "Subject": "[PATCH v2 5/7] clk: make clk_set_rate() return signed long",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=\"utf-8\"",
        "Content-Transfer-Encoding": "7bit",
        "Message-Id": "<20260401-casey-ccf-clk-prep-v2-5-16a78c8c62da@linaro.org>",
        "References": "<20260401-casey-ccf-clk-prep-v2-0-16a78c8c62da@linaro.org>",
        "In-Reply-To": "<20260401-casey-ccf-clk-prep-v2-0-16a78c8c62da@linaro.org>",
        "To": "Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>,\n Marek Vasut <marex@denx.de>",
        "Cc": "Casey Connolly <casey.connolly@linaro.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Quentin Schulz <quentin.schulz@cherry.de>,\n Mattijs Korpershoek <mkorpershoek@kernel.org>, u-boot@lists.denx.de,\n u-boot-amlogic@groups.io, u-boot-qcom@groups.io",
        "X-Mailer": "b4 0.15-dev-47773",
        "X-Developer-Signature": "v=1; a=openpgp-sha256; l=90169;\n i=casey.connolly@linaro.org; h=from:subject:message-id;\n bh=pgmpIl8jt0jsmMJBidoZ60c0RLXzBIbzG1GZdWp6MxU=;\n b=owGbwMvMwCFYaeA6f6eBkTjjabUkhsyzOo9vcRio/GqPydpyojCFebN3/updx7LKdPhfCakmM\n blJnq3vKGVhEORgkBVTZBE/scyyae1le43tCy7AzGFlAhnCwMUpABN5ZcbwT2PDlpWsFTVuDNPM\n auVLnljlzWToqXr4P4D3SKR2ieikHEaG6RfanppfjJ99oM3s1bQQ699lX5a/Xvupc+LuEnt10cX\n ztwMA",
        "X-Developer-Key": "i=casey.connolly@linaro.org; a=openpgp;\n fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.39",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>",
        "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de",
        "X-Virus-Status": "Clean"
    },
    "content": "The docs for clk_set_rate() indicate that it can return an error and\nthis is desirable for clock drivers to do, the ulong return type however\nimplies that this can't happen.\n\nFix the return type and adapt all clock drivers. Consumers can now more\neasily handle error conditions.\n\nSigned-off-by: Casey Connolly <casey.connolly@linaro.org>\n---\n drivers/clk/adi/clk-shared.c             |  2 +-\n drivers/clk/airoha/clk-airoha.c          |  2 +-\n drivers/clk/aspeed/clk_ast2500.c         |  2 +-\n drivers/clk/aspeed/clk_ast2600.c         |  2 +-\n drivers/clk/at91/clk-generic.c           |  2 +-\n drivers/clk/at91/clk-master.c            |  2 +-\n drivers/clk/at91/clk-peripheral.c        |  2 +-\n drivers/clk/at91/clk-programmable.c      |  2 +-\n drivers/clk/at91/clk-sam9x60-pll.c       |  4 ++--\n drivers/clk/at91/clk-sam9x60-usb.c       |  2 +-\n drivers/clk/at91/compat.c                |  8 ++++----\n drivers/clk/clk-cdce9xx.c                |  2 +-\n drivers/clk/clk-hsdk-cgu.c               |  2 +-\n drivers/clk/clk-stub.c                   |  2 +-\n drivers/clk/clk-uclass.c                 |  2 +-\n drivers/clk/clk-xlnx-clock-wizard.c      |  2 +-\n drivers/clk/clk_k210.c                   |  6 +++---\n drivers/clk/clk_pic32.c                  |  2 +-\n drivers/clk/clk_sandbox.c                |  2 +-\n drivers/clk/clk_sandbox_test.c           |  2 +-\n drivers/clk/clk_scmi.c                   |  4 ++--\n drivers/clk/clk_versaclock.c             |  8 ++++----\n drivers/clk/clk_versal.c                 |  2 +-\n drivers/clk/clk_vexpress_osc.c           |  2 +-\n drivers/clk/clk_zynq.c                   |  6 +++---\n drivers/clk/clk_zynqmp.c                 |  4 ++--\n drivers/clk/ics8n3qv01.c                 |  2 +-\n drivers/clk/imx/clk-composite-8m.c       |  2 +-\n drivers/clk/imx/clk-fracn-gppll.c        |  2 +-\n drivers/clk/imx/clk-gate-93.c            |  2 +-\n drivers/clk/imx/clk-gate2.c              |  2 +-\n drivers/clk/imx/clk-imx8.c               |  2 +-\n drivers/clk/imx/clk-imx8.h               |  2 +-\n drivers/clk/imx/clk-imx8qm.c             |  2 +-\n drivers/clk/imx/clk-imx8qxp.c            |  2 +-\n drivers/clk/imx/clk-imxrt1170.c          |  2 +-\n drivers/clk/imx/clk-pfd.c                |  2 +-\n drivers/clk/imx/clk-pll14xx.c            |  4 ++--\n drivers/clk/imx/clk-pllv3.c              |  8 ++++----\n drivers/clk/mediatek/clk-mtk.c           |  2 +-\n drivers/clk/meson/a1.c                   |  6 +++---\n drivers/clk/meson/g12a.c                 |  8 ++++----\n drivers/clk/meson/gxbb.c                 |  6 +++---\n drivers/clk/microchip/mpfs_clk_cfg.c     |  2 +-\n drivers/clk/mvebu/armada-37xx-periph.c   |  2 +-\n drivers/clk/nuvoton/clk_npcm.c           |  2 +-\n drivers/clk/owl/clk_owl.c                |  4 ++--\n drivers/clk/qcom/clock-apq8016.c         |  2 +-\n drivers/clk/qcom/clock-apq8096.c         |  2 +-\n drivers/clk/qcom/clock-ipq4019.c         |  2 +-\n drivers/clk/qcom/clock-ipq5424.c         |  2 +-\n drivers/clk/qcom/clock-ipq9574.c         |  2 +-\n drivers/clk/qcom/clock-qcm2290.c         |  2 +-\n drivers/clk/qcom/clock-qcom.c            |  2 +-\n drivers/clk/qcom/clock-qcom.h            |  2 +-\n drivers/clk/qcom/clock-qcs404.c          |  2 +-\n drivers/clk/qcom/clock-qcs615.c          |  2 +-\n drivers/clk/qcom/clock-qcs8300.c         |  2 +-\n drivers/clk/qcom/clock-sa8775p.c         |  2 +-\n drivers/clk/qcom/clock-sc7280.c          |  2 +-\n drivers/clk/qcom/clock-sdm845.c          |  4 ++--\n drivers/clk/qcom/clock-sm6115.c          |  2 +-\n drivers/clk/qcom/clock-sm6350.c          |  2 +-\n drivers/clk/qcom/clock-sm7150.c          |  2 +-\n drivers/clk/qcom/clock-sm8150.c          |  2 +-\n drivers/clk/qcom/clock-sm8250.c          |  2 +-\n drivers/clk/qcom/clock-sm8550.c          |  2 +-\n drivers/clk/qcom/clock-sm8650.c          |  2 +-\n drivers/clk/qcom/clock-x1e80100.c        |  2 +-\n drivers/clk/renesas/clk-rcar-gen2.c      |  2 +-\n drivers/clk/renesas/clk-rcar-gen3.c      |  2 +-\n drivers/clk/renesas/compound-clock.c     |  2 +-\n drivers/clk/renesas/r9a06g032-clocks.c   |  4 ++--\n drivers/clk/renesas/rzg2l-cpg.c          |  6 +++---\n drivers/clk/rockchip/clk_px30.c          |  8 ++++----\n drivers/clk/rockchip/clk_rk3036.c        |  2 +-\n drivers/clk/rockchip/clk_rk3066.c        |  2 +-\n drivers/clk/rockchip/clk_rk3128.c        |  2 +-\n drivers/clk/rockchip/clk_rk3188.c        |  2 +-\n drivers/clk/rockchip/clk_rk322x.c        |  2 +-\n drivers/clk/rockchip/clk_rk3288.c        |  2 +-\n drivers/clk/rockchip/clk_rk3308.c        |  2 +-\n drivers/clk/rockchip/clk_rk3328.c        |  2 +-\n drivers/clk/rockchip/clk_rk3368.c        |  2 +-\n drivers/clk/rockchip/clk_rk3399.c        |  4 ++--\n drivers/clk/rockchip/clk_rk3528.c        |  8 ++++----\n drivers/clk/rockchip/clk_rk3568.c        | 10 +++++-----\n drivers/clk/rockchip/clk_rk3576.c        |  6 +++---\n drivers/clk/rockchip/clk_rk3588.c        |  8 ++++----\n drivers/clk/rockchip/clk_rv1108.c        |  2 +-\n drivers/clk/rockchip/clk_rv1126.c        |  8 ++++----\n drivers/clk/sifive/sifive-prci.c         |  2 +-\n drivers/clk/sophgo/clk-cv1800b.c         |  2 +-\n drivers/clk/sophgo/clk-ip.c              | 12 ++++++------\n drivers/clk/sophgo/clk-pll.c             |  4 ++--\n drivers/clk/starfive/clk-jh7110-pll.c    |  2 +-\n drivers/clk/stm32/clk-stm32-core.c       |  2 +-\n drivers/clk/stm32/clk-stm32f.c           |  2 +-\n drivers/clk/stm32/clk-stm32mp1.c         |  2 +-\n drivers/clk/tegra/tegra-car-clk.c        |  2 +-\n drivers/clk/tegra/tegra186-clk.c         |  2 +-\n drivers/clk/thead/clk-th1520-ap.c        |  2 +-\n drivers/clk/ti/clk-am3-dpll.c            |  2 +-\n drivers/clk/ti/clk-divider.c             |  2 +-\n drivers/clk/ti/clk-k3-pll.c              |  2 +-\n drivers/clk/ti/clk-k3.c                  |  2 +-\n drivers/clk/ti/clk-mux.c                 |  2 +-\n drivers/clk/ti/clk-sci.c                 |  2 +-\n drivers/clk/uccf/clk-composite.c         |  2 +-\n drivers/clk/uccf/clk-divider.c           |  2 +-\n drivers/clk/uccf/clk.c                   |  2 +-\n drivers/clk/uniphier/clk-uniphier-core.c |  4 ++--\n include/clk-uclass.h                     |  2 +-\n include/clk.h                            |  2 +-\n 114 files changed, 169 insertions(+), 169 deletions(-)",
    "diff": "diff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c\nindex 5d0b7eb34655..7376b9b5668d 100644\n--- a/drivers/clk/adi/clk-shared.c\n+++ b/drivers/clk/adi/clk-shared.c\n@@ -20,9 +20,9 @@ static ulong adi_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(c);\n }\n \n-static ulong adi_set_rate(struct clk *clk, ulong rate)\n+static long adi_set_rate(struct clk *clk, ulong rate)\n {\n \t//Not yet implemented\n \treturn 0;\n }\ndiff --git a/drivers/clk/airoha/clk-airoha.c b/drivers/clk/airoha/clk-airoha.c\nindex 200324a4fffd..4e0ad1845021 100644\n--- a/drivers/clk/airoha/clk-airoha.c\n+++ b/drivers/clk/airoha/clk-airoha.c\n@@ -399,9 +399,9 @@ static int airoha_clk_search_rate(const struct airoha_clk_desc *desc, int div,\n err:\n \treturn -EINVAL;\n }\n \n-static ulong airoha_clk_set_rate(struct clk *clk, ulong rate)\n+static long airoha_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct airoha_clk_priv *priv = dev_get_priv(clk->dev);\n \tstruct airoha_clk_soc_data *data = priv->data;\n \tconst struct airoha_clk_desc *desc;\ndiff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c\nindex 4d30ecb87d99..f284ae05503f 100644\n--- a/drivers/clk/aspeed/clk_ast2500.c\n+++ b/drivers/clk/aspeed/clk_ast2500.c\n@@ -467,9 +467,9 @@ static ulong ast2500_enable_sdclk(struct ast2500_scu *scu)\n \n \treturn 0;\n }\n \n-static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)\n+static long ast2500_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct ast2500_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tulong new_rate;\ndiff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c\nindex b9bbe41a592f..c3e89a030be1 100644\n--- a/drivers/clk/aspeed/clk_ast2600.c\n+++ b/drivers/clk/aspeed/clk_ast2600.c\n@@ -572,9 +572,9 @@ static uint32_t ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate)\n \n \treturn ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL);\n }\n \n-static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate)\n+static long ast2600_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct ast2600_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong new_rate;\n \ndiff --git a/drivers/clk/at91/clk-generic.c b/drivers/clk/at91/clk-generic.c\nindex 0424fb1b6f4e..00b27612096f 100644\n--- a/drivers/clk/at91/clk-generic.c\n+++ b/drivers/clk/at91/clk-generic.c\n@@ -83,9 +83,9 @@ static int clk_gck_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-static ulong clk_gck_set_rate(struct clk *clk, ulong rate)\n+static long clk_gck_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_gck *gck = to_clk_gck(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tu32 div;\ndiff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c\nindex 53652efc5740..feb7aea13bd8 100644\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -267,9 +267,9 @@ static int clk_sama7g5_master_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static ulong clk_sama7g5_master_set_rate(struct clk *clk, ulong rate)\n+static long clk_sama7g5_master_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_master *master = to_clk_master(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tulong div, rrate;\ndiff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c\nindex 8f0c7524e4cc..8c74b7015789 100644\n--- a/drivers/clk/at91/clk-peripheral.c\n+++ b/drivers/clk/at91/clk-peripheral.c\n@@ -167,9 +167,9 @@ static ulong clk_sam9x5_peripheral_get_rate(struct clk *clk)\n \n \treturn parent_rate >> shift;\n }\n \n-static ulong clk_sam9x5_peripheral_set_rate(struct clk *clk, ulong rate)\n+static long clk_sam9x5_peripheral_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tint shift;\ndiff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c\nindex 9cf8e38af08c..ce4f63902c7d 100644\n--- a/drivers/clk/at91/clk-programmable.c\n+++ b/drivers/clk/at91/clk-programmable.c\n@@ -83,9 +83,9 @@ static int clk_programmable_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-static ulong clk_programmable_set_rate(struct clk *clk, ulong rate)\n+static long clk_programmable_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_programmable *prog = to_clk_programmable(clk);\n \tconst struct clk_programmable_layout *layout = prog->layout;\n \tulong parent_rate = clk_get_parent_rate(clk);\ndiff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c\nindex b896be5fe238..cf56e2c86032 100644\n--- a/drivers/clk/at91/clk-sam9x60-pll.c\n+++ b/drivers/clk/at91/clk-sam9x60-pll.c\n@@ -89,9 +89,9 @@ static long sam9x60_frac_pll_compute_mul_frac(const struct clk_range *core_clk,\n \n \treturn tmprate;\n }\n \n-static ulong sam9x60_frac_pll_set_rate(struct clk *clk, ulong rate)\n+static long sam9x60_frac_pll_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct sam9x60_pll *pll = to_sam9x60_pll(clk);\n \tvoid __iomem *base = pll->base;\n \tulong parent_rate = clk_get_parent_rate(clk);\n@@ -299,9 +299,9 @@ static int sam9x60_div_pll_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static ulong sam9x60_div_pll_set_rate(struct clk *clk, ulong rate)\n+static long sam9x60_div_pll_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct sam9x60_pll *pll = to_sam9x60_pll(clk);\n \tvoid __iomem *base = pll->base;\n \tconst struct clk_pll_characteristics *characteristics =\ndiff --git a/drivers/clk/at91/clk-sam9x60-usb.c b/drivers/clk/at91/clk-sam9x60-usb.c\nindex 92bfd45f5353..308548519c11 100644\n--- a/drivers/clk/at91/clk-sam9x60-usb.c\n+++ b/drivers/clk/at91/clk-sam9x60-usb.c\n@@ -67,9 +67,9 @@ static ulong sam9x60_usb_clk_get_rate(struct clk *clk)\n \t\t(ffs(usb->layout->usbdiv_mask) - 1);\n \treturn parent_rate / (usbdiv + 1);\n }\n \n-static ulong sam9x60_usb_clk_set_rate(struct clk *clk, ulong rate)\n+static long sam9x60_usb_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct sam9x60_usb *usb = to_sam9x60_usb(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tu32 usbdiv, val;\ndiff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c\nindex 5099fe3b8c62..6c1cf1b4192e 100644\n--- a/drivers/clk/at91/compat.c\n+++ b/drivers/clk/at91/compat.c\n@@ -299,9 +299,9 @@ static ulong at91_plladiv_clk_get_rate(struct clk *clk)\n \n \treturn clk_rate;\n }\n \n-static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)\n+static long at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct pmc_plat *plat = dev_get_plat(clk->dev);\n \tstruct at91_pmc *pmc = plat->reg_base;\n \tstruct clk source;\n@@ -391,9 +391,9 @@ static ulong system_clk_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(&clk_dev);\n }\n \n-static ulong system_clk_set_rate(struct clk *clk, ulong rate)\n+static long system_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk clk_dev;\n \tint ret;\n \n@@ -774,9 +774,9 @@ static ulong generic_clk_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(&parent) / (gckdiv + 1);\n }\n \n-static ulong generic_clk_set_rate(struct clk *clk, ulong rate)\n+static long generic_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct pmc_plat *plat = dev_get_plat(clk->dev);\n \tstruct at91_pmc *pmc = plat->reg_base;\n \tstruct generic_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -908,9 +908,9 @@ static ulong at91_usb_clk_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(&source) / (usbdiv + 1);\n }\n \n-static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)\n+static long at91_usb_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct pmc_plat *plat = dev_get_plat(clk->dev);\n \tstruct at91_pmc *pmc = plat->reg_base;\n \tstruct at91_usb_clk_priv *priv = dev_get_priv(clk->dev);\ndiff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c\nindex 9689283cec48..c4694aa86c28 100644\n--- a/drivers/clk/clk-cdce9xx.c\n+++ b/drivers/clk/clk-cdce9xx.c\n@@ -170,9 +170,9 @@ static ulong cdce9xx_clk_get_rate(struct clk *clk)\n \n \treturn parent_rate / pdiv;\n }\n \n-static ulong cdce9xx_clk_set_rate(struct clk *clk, ulong rate)\n+static long cdce9xx_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tu32 parent_rate;\n \tint pdiv;\n \tu32 diff;\ndiff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c\nindex 4ff2b27205fd..b908fd75243b 100644\n--- a/drivers/clk/clk-hsdk-cgu.c\n+++ b/drivers/clk/clk-hsdk-cgu.c\n@@ -707,9 +707,9 @@ static ulong hsdk_cgu_get_rate(struct clk *sclk)\n \n \treturn clk->map[sclk->id].get_rate(sclk);\n }\n \n-static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)\n+static long hsdk_cgu_set_rate(struct clk *sclk, ulong rate)\n {\n \tstruct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);\n \n \tif (hsdk_prepare_clock_tree_branch(sclk))\ndiff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c\nindex ea77a4c720ae..d4cca5ff2ce7 100644\n--- a/drivers/clk/clk-stub.c\n+++ b/drivers/clk/clk-stub.c\n@@ -25,9 +25,9 @@ U_BOOT_DRIVER(nop_parent) = {\n \t.bind = dm_scan_fdt_dev,\n \t.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,\n };\n \n-static ulong stub_clk_set_rate(struct clk *clk, ulong rate)\n+static long stub_clk_set_rate(struct clk *clk, ulong rate)\n {\n \treturn (clk->rate = rate);\n }\n \ndiff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c\nindex 8a7033386a74..db4f056e4816 100644\n--- a/drivers/clk/clk-uclass.c\n+++ b/drivers/clk/clk-uclass.c\n@@ -585,9 +585,9 @@ static void clk_clean_rate_cache(struct clk *clk)\n \t\tclk_clean_rate_cache(clkp);\n \t}\n }\n \n-ulong clk_set_rate(struct clk *clk, ulong rate)\n+long clk_set_rate(struct clk *clk, ulong rate)\n {\n \tconst struct clk_ops_uboot *ops;\n \tstruct clk *clkp;\n \ndiff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c\nindex 18c5ae43789a..598aac5f3a2a 100644\n--- a/drivers/clk/clk-xlnx-clock-wizard.c\n+++ b/drivers/clk/clk-xlnx-clock-wizard.c\n@@ -86,9 +86,9 @@ static int clk_wzrd_enable(struct clk *clk)\n \n \treturn ret;\n }\n \n-static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)\n+static long clk_wzrd_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clkwzd *priv = dev_get_priv(clk->dev);\n \tu64 div;\n \tu32 cfg;\ndiff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c\nindex 329fc5bffd18..af9e5f172509 100644\n--- a/drivers/clk/clk_k210.c\n+++ b/drivers/clk/clk_k210.c\n@@ -862,9 +862,9 @@ again:\n \n \treturn 0;\n }\n \n-static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,\n+static long k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,\n \t\t\t       ulong rate_in)\n {\n \tint err;\n \tconst struct k210_pll_params *pll = &k210_plls[id];\n@@ -901,9 +901,9 @@ static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,\n \tserial_setbrg();\n \treturn k210_pll_get_rate(priv, id, rate);\n }\n #else\n-static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,\n+static long k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,\n \t\t\t       ulong rate_in)\n {\n \treturn -ENOSYS;\n }\n@@ -1108,9 +1108,9 @@ static int k210_clk_set_parent(struct clk *clk, struct clk *parent)\n \treturn do_k210_clk_set_parent(dev_get_priv(clk->dev), clk->id,\n \t\t\t\t      parent->id);\n }\n \n-static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)\n+static long k210_clk_set_rate(struct clk *clk, unsigned long rate)\n {\n \tint parent, ret, err;\n \tulong rate_in, val;\n \tconst struct k210_div_params *div;\ndiff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c\nindex 0b8e2f7ad8ec..b51921240a1c 100644\n--- a/drivers/clk/clk_pic32.c\n+++ b/drivers/clk/clk_pic32.c\n@@ -368,9 +368,9 @@ static ulong pic32_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong pic32_set_rate(struct clk *clk, ulong rate)\n+static long pic32_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct pic32_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong pll_hz;\n \ndiff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c\nindex dceba88852ab..667526810fc2 100644\n--- a/drivers/clk/clk_sandbox.c\n+++ b/drivers/clk/clk_sandbox.c\n@@ -40,9 +40,9 @@ static ulong sandbox_clk_round_rate(struct clk *clk, ulong rate)\n \n \treturn rate;\n }\n \n-static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate)\n+static long sandbox_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct sandbox_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong old_rate;\n \tulong id = clk_get_id(clk);\ndiff --git a/drivers/clk/clk_sandbox_test.c b/drivers/clk/clk_sandbox_test.c\nindex 87350212775c..b30888889ce9 100644\n--- a/drivers/clk/clk_sandbox_test.c\n+++ b/drivers/clk/clk_sandbox_test.c\n@@ -89,9 +89,9 @@ ulong sandbox_clk_test_round_rate(struct udevice *dev, int id, ulong rate)\n \n \treturn clk_round_rate(sbct->clkps[id], rate);\n }\n \n-ulong sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)\n+long sandbox_clk_test_set_rate(struct udevice *dev, int id, ulong rate)\n {\n \tstruct sandbox_clk_test *sbct = dev_get_priv(dev);\n \n \tif (id < 0 || id >= SANDBOX_CLK_TEST_ID_COUNT)\ndiff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c\nindex 16374560f2b7..97a698dd5645 100644\n--- a/drivers/clk/clk_scmi.c\n+++ b/drivers/clk/clk_scmi.c\n@@ -283,9 +283,9 @@ static ulong scmi_clk_get_rate(struct clk *clk)\n \n \treturn (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb);\n }\n \n-static ulong __scmi_clk_set_rate(struct clk *clk, ulong rate)\n+static long __scmi_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct scmi_clk_rate_set_in in = {\n \t\t.clock_id = clk_get_id(clk),\n \t\t.flags = SCMI_CLK_RATE_ROUND_CLOSEST,\n@@ -308,9 +308,9 @@ static ulong __scmi_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn scmi_clk_get_rate(clk);\n }\n \n-static ulong scmi_clk_set_rate(struct clk *clk, ulong rate)\n+static long scmi_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tu32 ctrl_flags;\n \tint ret;\n \ndiff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c\nindex 35f7ded0137b..19f67cce1267 100644\n--- a/drivers/clk/clk_versaclock.c\n+++ b/drivers/clk/clk_versaclock.c\n@@ -324,9 +324,9 @@ static unsigned long vc5_pfd_recalc_rate(struct clk *hw)\n \telse\n \t\treturn parent_rate / VC5_REF_DIVIDER_REF_DIV(div);\n }\n \n-static unsigned long vc5_pfd_set_rate(struct clk *hw, unsigned long rate)\n+static long vc5_pfd_set_rate(struct clk *hw, unsigned long rate)\n {\n \tstruct vc5_driver_data *vc5 =\n \t\tcontainer_of(hw, struct vc5_driver_data, clk_pfd);\n \tunsigned long idiv;\n@@ -413,9 +413,9 @@ static unsigned long vc5_pll_round_rate(struct clk *hw, unsigned long rate)\n \n \treturn (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);\n }\n \n-static unsigned long vc5_pll_set_rate(struct clk *hw, unsigned long rate)\n+static long vc5_pll_set_rate(struct clk *hw, unsigned long rate)\n {\n \tstruct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);\n \tstruct vc5_driver_data *vc5 = hwdata->vc5;\n \tu8 fb[5];\n@@ -498,9 +498,9 @@ static unsigned long vc5_fod_round_rate(struct clk *hw, unsigned long rate)\n \n \treturn div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);\n }\n \n-static unsigned long vc5_fod_set_rate(struct clk *hw, unsigned long rate)\n+static long vc5_fod_set_rate(struct clk *hw, unsigned long rate)\n {\n \tstruct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);\n \tstruct vc5_driver_data *vc5 = hwdata->vc5;\n \n@@ -616,9 +616,9 @@ static int vc5_clk_out_set_parent(struct vc5_driver_data *vc, u8 num, u8 index)\n \n \treturn vc5_update_bits(vc->i2c, VC5_OUT_DIV_CONTROL(num), mask, src);\n }\n \n-static unsigned long vc5_clk_out_set_rate(struct clk *hw, unsigned long rate)\n+static long vc5_clk_out_set_rate(struct clk *hw, unsigned long rate)\n {\n \tstruct udevice *dev;\n \tstruct vc5_driver_data *vc;\n \tstruct clk *parent;\ndiff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c\nindex 14dadf859a1f..7eb5370f0116 100644\n--- a/drivers/clk/clk_versal.c\n+++ b/drivers/clk/clk_versal.c\n@@ -744,9 +744,9 @@ static ulong versal_clk_get_rate(struct clk *clk)\n \n \treturn clk_rate;\n }\n \n-static ulong versal_clk_set_rate(struct clk *clk, ulong rate)\n+static long versal_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct versal_clk_priv *priv = dev_get_priv(clk->dev);\n \tu32 id = clk_get_id(clk);\n \tu32 clk_id;\ndiff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c\nindex a6f0ba595a23..5e129b894f67 100644\n--- a/drivers/clk/clk_vexpress_osc.c\n+++ b/drivers/clk/clk_vexpress_osc.c\n@@ -37,9 +37,9 @@ static ulong vexpress_osc_clk_get_rate(struct clk *clk)\n \treturn data;\n }\n \n #ifndef CONFIG_XPL_BUILD\n-static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)\n+static long vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tint err;\n \tu32 buffer[2];\n \tstruct udevice *vexpress_cfg = dev_get_parent(clk->dev);\ndiff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c\nindex 229972fb505d..2a1ff3bd3feb 100644\n--- a/drivers/clk/clk_zynq.c\n+++ b/drivers/clk/clk_zynq.c\n@@ -311,9 +311,9 @@ static unsigned long zynq_clk_calc_peripheral_two_divs(ulong rate,\n \n \treturn best_rate;\n }\n \n-static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv,\n+static long zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv,\n \t\t\t\t\t  enum zynq_clk id, ulong rate,\n \t\t\t\t\t  bool two_divs)\n {\n \tenum zynq_clk pll;\n@@ -346,9 +346,9 @@ static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv,\n \n \treturn new_rate;\n }\n \n-static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id,\n+static long zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id,\n \t\t\t\t   ulong rate)\n {\n \tstruct clk *parent;\n \n@@ -401,9 +401,9 @@ static ulong zynq_clk_get_rate(struct clk *clk)\n \t\treturn -ENXIO;\n \t}\n }\n \n-static ulong zynq_clk_set_rate(struct clk *clk, ulong rate)\n+static long zynq_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct zynq_clk_priv *priv = dev_get_priv(clk->dev);\n \tenum zynq_clk id = clk->id;\n \tbool two_divs = false;\ndiff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c\nindex 1f23b06553bf..873862113b73 100644\n--- a/drivers/clk/clk_zynqmp.c\n+++ b/drivers/clk/clk_zynqmp.c\n@@ -638,9 +638,9 @@ static unsigned long zynqmp_clk_calc_peripheral_two_divs(ulong rate,\n \n \treturn best_rate;\n }\n \n-static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,\n+static long zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,\n \t\t\t\t\t  enum zynqmp_clk id, ulong rate,\n \t\t\t\t\t  bool two_divs)\n {\n \tenum zynqmp_clk pll;\n@@ -734,9 +734,9 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)\n \t\treturn -ENXIO;\n \t}\n }\n \n-static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)\n+static long zynqmp_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct zynqmp_clk_priv *priv = dev_get_priv(clk->dev);\n \tenum zynqmp_clk id = clk->id;\n \tbool two_divs = true;\ndiff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c\nindex 04e6a349436a..f0d8b7bcc660 100644\n--- a/drivers/clk/ics8n3qv01.c\n+++ b/drivers/clk/ics8n3qv01.c\n@@ -105,9 +105,9 @@ static int ics8n3qv01_calc_parameters(uint fout, uint *_mint, uint *_mfrac,\n \n \treturn 0;\n }\n \n-static ulong ics8n3qv01_set_rate(struct clk *clk, ulong fout)\n+static long ics8n3qv01_set_rate(struct clk *clk, ulong fout)\n {\n \tstruct ics8n3qv01_priv *priv = dev_get_priv(clk->dev);\n \tuint n, mint, mfrac;\n \tuint fout_calc = 0;\ndiff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c\nindex 848c7b9d3fb1..cbeb2bcc9f59 100644\n--- a/drivers/clk/imx/clk-composite-8m.c\n+++ b/drivers/clk/imx/clk-composite-8m.c\n@@ -83,9 +83,9 @@ static int imx8m_clk_composite_compute_dividers(unsigned long rate,\n /*\n  * The clk are bound to a dev, because it is part of composite clk\n  * use composite clk to get dev\n  */\n-static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,\n+static long imx8m_clk_composite_divider_set_rate(struct clk *clk,\n \t\t\t\t\t\t  unsigned long rate)\n {\n \tstruct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);\n \tstruct clk_composite *composite = (struct clk_composite *)clk->data;\ndiff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c\nindex b885c4bc01d4..d0b0f1e0479b 100644\n--- a/drivers/clk/imx/clk-fracn-gppll.c\n+++ b/drivers/clk/imx/clk-fracn-gppll.c\n@@ -224,9 +224,9 @@ static int clk_fracn_gppll_wait_lock(struct clk_fracn_gppll *pll)\n \treturn readl_poll_timeout(pll->base + PLL_STATUS, val,\n \t\t\t\t  val & LOCK_STATUS, LOCK_TIMEOUT_US);\n }\n \n-static ulong clk_fracn_gppll_set_rate(struct clk *clk, unsigned long drate)\n+static long clk_fracn_gppll_set_rate(struct clk *clk, unsigned long drate)\n {\n \tstruct clk_fracn_gppll *pll = to_clk_fracn_gppll(clk);\n \tconst struct imx_fracn_gppll_rate_table *rate;\n \tu32 tmp, pll_div, ana_mfn;\ndiff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c\nindex ff3ae5b57d36..b6f905365178 100644\n--- a/drivers/clk/imx/clk-gate-93.c\n+++ b/drivers/clk/imx/clk-gate-93.c\n@@ -92,9 +92,9 @@ static int imx93_clk_gate_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static ulong imx93_clk_set_rate(struct clk *clk, ulong rate)\n+static long imx93_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk *parent = clk_get_parent(clk);\n \n \tif (parent)\ndiff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c\nindex b5cd1b31036e..d570915d3b64 100644\n--- a/drivers/clk/imx/clk-gate2.c\n+++ b/drivers/clk/imx/clk-gate2.c\n@@ -72,9 +72,9 @@ static int clk_gate2_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)\n+static long clk_gate2_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk *parent = clk_get_parent(clk);\n \n \tif (parent)\ndiff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c\nindex 423b052cc5b6..101f66c16a4e 100644\n--- a/drivers/clk/imx/clk-imx8.c\n+++ b/drivers/clk/imx/clk-imx8.c\n@@ -20,9 +20,9 @@ __weak ulong imx8_clk_get_rate(struct clk *clk)\n {\n \treturn 0;\n }\n \n-__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)\n+__weak long imx8_clk_set_rate(struct clk *clk, unsigned long rate)\n {\n \treturn 0;\n }\n \ndiff --git a/drivers/clk/imx/clk-imx8.h b/drivers/clk/imx/clk-imx8.h\nindex 6e850ba26669..a5e73fcd95bd 100644\n--- a/drivers/clk/imx/clk-imx8.h\n+++ b/drivers/clk/imx/clk-imx8.h\n@@ -14,6 +14,6 @@ extern struct imx8_clks imx8_clk_names[];\n extern int num_clks;\n #endif\n \n ulong imx8_clk_get_rate(struct clk *clk);\n-ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate);\n+long imx8_clk_set_rate(struct clk *clk, unsigned long rate);\n int __imx8_clk_enable(struct clk *clk, bool enable);\ndiff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c\nindex 466d71786cfb..3239e7d9be6b 100644\n--- a/drivers/clk/imx/clk-imx8qm.c\n+++ b/drivers/clk/imx/clk-imx8qm.c\n@@ -149,9 +149,9 @@ ulong imx8_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)\n+long imx8_clk_set_rate(struct clk *clk, unsigned long rate)\n {\n \tsc_pm_clk_t pm_clk;\n \tu32 new_rate = rate;\n \tu16 resource;\ndiff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c\nindex 79098623bc8c..bf29443be060 100644\n--- a/drivers/clk/imx/clk-imx8qxp.c\n+++ b/drivers/clk/imx/clk-imx8qxp.c\n@@ -142,9 +142,9 @@ ulong imx8_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)\n+long imx8_clk_set_rate(struct clk *clk, unsigned long rate)\n {\n \tsc_pm_clk_t pm_clk;\n \tu32 new_rate = rate;\n \tu16 resource;\ndiff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c\nindex ed31cb2d09ef..289d23dc0b81 100644\n--- a/drivers/clk/imx/clk-imxrt1170.c\n+++ b/drivers/clk/imx/clk-imxrt1170.c\n@@ -27,9 +27,9 @@ static ulong imxrt1170_clk_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(c);\n }\n \n-static ulong imxrt1170_clk_set_rate(struct clk *clk, ulong rate)\n+static long imxrt1170_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk *c;\n \tint ret;\n \ndiff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c\nindex de26b1e3f83d..58702034ab51 100644\n--- a/drivers/clk/imx/clk-pfd.c\n+++ b/drivers/clk/imx/clk-pfd.c\n@@ -52,9 +52,9 @@ static unsigned long clk_pfd_recalc_rate(struct clk *clk)\n \n \treturn tmp;\n }\n \n-static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)\n+static long clk_pfd_set_rate(struct clk *clk, unsigned long rate)\n {\n \tstruct clk_pfd *pfd = to_clk_pfd(clk);\n \tunsigned long parent_rate = clk_get_parent_rate(clk);\n \tu64 tmp = parent_rate;\ndiff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c\nindex 0bb4d2c7e28c..dacd5851f292 100644\n--- a/drivers/clk/imx/clk-pll14xx.c\n+++ b/drivers/clk/imx/clk-pll14xx.c\n@@ -210,9 +210,9 @@ static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)\n \treturn readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,\n \t\t\tLOCK_TIMEOUT_US);\n }\n \n-static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)\n+static long clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)\n {\n \tstruct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));\n \tconst struct imx_pll14xx_rate_table *rate;\n \tu32 tmp, div_val;\n@@ -275,9 +275,9 @@ static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)\n \n \treturn clk_pll1416x_recalc_rate(clk);\n }\n \n-static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)\n+static long clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)\n {\n \tstruct clk_pll14xx *pll = to_clk_pll14xx(dev_get_clk_ptr(clk->dev));\n \tconst struct imx_pll14xx_rate_table *rate;\n \tu32 tmp, div_val;\ndiff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c\nindex e907fd378c6d..2527ade99c88 100644\n--- a/drivers/clk/imx/clk-pllv3.c\n+++ b/drivers/clk/imx/clk-pllv3.c\n@@ -54,9 +54,9 @@ static ulong clk_pllv3_genericv2_get_rate(struct clk *clk)\n \n \treturn (div == 0) ? parent_rate * 22 : parent_rate * 20;\n }\n \n-static ulong clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)\n+static long clk_pllv3_genericv2_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_pllv3 *pll = to_clk_pllv3(clk);\n \tunsigned long parent_rate = clk_get_parent_rate(clk);\n \n@@ -78,9 +78,9 @@ static ulong clk_pllv3_generic_get_rate(struct clk *clk)\n \n \treturn (div == 1) ? parent_rate * 22 : parent_rate * 20;\n }\n \n-static ulong clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)\n+static long clk_pllv3_generic_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_pllv3 *pll = to_clk_pllv3(clk);\n \tunsigned long parent_rate = clk_get_parent_rate(clk);\n \tu32 val, div;\n@@ -162,9 +162,9 @@ static ulong clk_pllv3_sys_get_rate(struct clk *clk)\n \n \treturn parent_rate * div / 2;\n }\n \n-static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)\n+static long clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_pllv3 *pll = to_clk_pllv3(clk);\n \tunsigned long parent_rate = clk_get_parent_rate(clk);\n \tunsigned long min_rate;\n@@ -217,9 +217,9 @@ static ulong clk_pllv3_av_get_rate(struct clk *clk)\n \n \treturn parent_rate * div + (unsigned long)temp64;\n }\n \n-static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)\n+static long clk_pllv3_av_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_pllv3 *pll = to_clk_pllv3(clk);\n \tunsigned long parent_rate = clk_get_parent_rate(clk);\n \tunsigned long min_rate;\ndiff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex 7c55bc4defa8..ebf29a6006b5 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -443,9 +443,9 @@ static void mtk_pll_calc_values(struct mtk_clk_priv *priv, u32 id,\n \n \t*pcw = (u32)_pcw;\n }\n \n-static ulong mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)\n+static long mtk_apmixedsys_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct mtk_clk_priv *priv = dev_get_priv(clk->dev);\n \tu32 pcw = 0;\n \tu32 postdiv;\ndiff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c\nindex e87ad773da8f..ff9ec74b0e90 100644\n--- a/drivers/clk/meson/a1.c\n+++ b/drivers/clk/meson/a1.c\n@@ -475,9 +475,9 @@ static ulong meson_clk_get_rate(struct clk *clk)\n  *  ---------|\\\n  *     ..... | |---DIV--\n  *  ---------|/\n  */\n-static ulong meson_composite_set_rate(struct clk *clk, ulong id, ulong rate)\n+static long meson_composite_set_rate(struct clk *clk, ulong id, ulong rate)\n {\n \tunsigned int i, best_div_val;\n \tunsigned long best_delta, best_parent;\n \tconst struct meson_clk_info *div;\n@@ -525,9 +525,9 @@ static ulong meson_composite_set_rate(struct clk *clk, ulong id, ulong rate)\n }\n \n static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned int id, ulong rate);\n \n-static ulong meson_mux_set_rate(struct clk *clk, unsigned long id, ulong rate)\n+static long meson_mux_set_rate(struct clk *clk, unsigned long id, ulong rate)\n {\n \tint i;\n \tulong ret = -EINVAL;\n \tstruct meson_clk *priv = dev_get_priv(clk->dev);\n@@ -569,9 +569,9 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned int id, ulong ra\n \n \treturn -EINVAL;\n }\n \n-static ulong meson_clk_set_rate(struct clk *clk, ulong rate)\n+static long meson_clk_set_rate(struct clk *clk, ulong rate)\n {\n \treturn meson_clk_set_rate_by_id(clk, clk->id, rate);\n }\n \ndiff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c\nindex c0172e243274..cff7dd2b838d 100644\n--- a/drivers/clk/meson/g12a.c\n+++ b/drivers/clk/meson/g12a.c\n@@ -95,9 +95,9 @@ struct meson_clk {\n \tstruct regmap *map;\n };\n \n static ulong meson_div_get_rate(struct clk *clk, unsigned long id);\n-static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n+static long meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n \t\t\t\tulong current_rate);\n static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,\n \t\t\t\t  unsigned long parent_id);\n static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);\n@@ -284,9 +284,9 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)\n \n \treturn rate;\n }\n \n-static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n+static long meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n \t\t\t\tulong current_rate)\n {\n \tstruct meson_clk *priv = dev_get_priv(clk->dev);\n \tunsigned int new_div = -EINVAL;\n@@ -862,9 +862,9 @@ static ulong meson_clk_get_rate(struct clk *clk)\n {\n \treturn meson_clk_get_rate_by_id(clk, clk->id);\n }\n \n-static ulong meson_pcie_pll_set_rate(struct clk *clk, ulong rate)\n+static long meson_pcie_pll_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct meson_clk *priv = dev_get_priv(clk->dev);\n \n \tregmap_write(priv->map, HHI_PCIE_PLL_CNTL0, 0x20090496);\n@@ -952,9 +952,9 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,\n \n \treturn -EINVAL;\n }\n \n-static ulong meson_clk_set_rate(struct clk *clk, ulong rate)\n+static long meson_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);\n \tint ret;\n \ndiff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c\nindex 14c0d1f9158d..d44972e32452 100644\n--- a/drivers/clk/meson/gxbb.c\n+++ b/drivers/clk/meson/gxbb.c\n@@ -74,9 +74,9 @@ struct meson_clk {\n \tstruct regmap *map;\n };\n \n static ulong meson_div_get_rate(struct clk *clk, unsigned long id);\n-static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n+static long meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n \t\t\t\tulong current_rate);\n static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,\n \t\t\t\t  unsigned long parent_id);\n static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);\n@@ -326,9 +326,9 @@ static ulong meson_div_get_rate(struct clk *clk, unsigned long id)\n \n \treturn rate;\n }\n \n-static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n+static long meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,\n \t\t\t\tulong current_rate)\n {\n \tstruct meson_clk *priv = dev_get_priv(clk->dev);\n \tunsigned int new_div = -EINVAL;\n@@ -906,9 +906,9 @@ static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,\n \n \treturn -EINVAL;\n }\n \n-static ulong meson_clk_set_rate(struct clk *clk, ulong rate)\n+static long meson_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);\n \tint ret;\n \ndiff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c\nindex 294ee0f5cc0d..d24017b5cc11 100644\n--- a/drivers/clk/microchip/mpfs_clk_cfg.c\n+++ b/drivers/clk/microchip/mpfs_clk_cfg.c\n@@ -80,9 +80,9 @@ static ulong mpfs_cfg_clk_recalc_rate(struct clk *hw)\n \n \treturn rate;\n }\n \n-static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate)\n+static long mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate)\n {\n \tstruct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);\n \tstruct mpfs_cfg_clock *cfg = &cfg_hw->cfg;\n \tu32  val;\ndiff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c\nindex b25b3df3b666..988067afa3e0 100644\n--- a/drivers/clk/mvebu/armada-37xx-periph.c\n+++ b/drivers/clk/mvebu/armada-37xx-periph.c\n@@ -383,9 +383,9 @@ static ulong find_best_div(const struct clk_div_table *t0,\n \n \treturn best_rate;\n }\n \n-static ulong armada_37xx_periph_clk_set_rate(struct clk *clk, ulong req_rate)\n+static long armada_37xx_periph_clk_set_rate(struct clk *clk, ulong req_rate)\n {\n \tstruct a37xx_periphclk *priv = dev_get_priv(clk->dev);\n \tconst struct clk_periph *periph_clk = &priv->clks[clk->id];\n \tulong rate, old_rate, parent_rate;\ndiff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c\nindex ecb23431ecbd..b609e6236cb7 100644\n--- a/drivers/clk/nuvoton/clk_npcm.c\n+++ b/drivers/clk/nuvoton/clk_npcm.c\n@@ -245,9 +245,9 @@ static ulong npcm_clk_get_rate(struct clk *clk)\n \telse\n \t\treturn npcm_clk_get_fout(clk);\n }\n \n-static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)\n+static long npcm_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tulong parent_rate;\n \tu32 div;\n \tint ret;\ndiff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c\nindex 832177b8547f..5782ce89e12e 100644\n--- a/drivers/clk/owl/clk_owl.c\n+++ b/drivers/clk/owl/clk_owl.c\n@@ -165,9 +165,9 @@ static ulong owl_get_sd_clk_rate(struct owl_clk_priv *priv, int sd_index)\n \n \treturn (parent_rate / div);\n }\n \n-static ulong owl_set_sd_clk_rate(struct owl_clk_priv *priv, ulong rate,\n+static long owl_set_sd_clk_rate(struct owl_clk_priv *priv, ulong rate,\n \t\t\t\t int sd_index)\n {\n \tuint div, val;\n \tulong parent_rate = get_sd_parent_rate(priv, sd_index);\n@@ -207,9 +207,9 @@ static ulong owl_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong owl_clk_set_rate(struct clk *clk, ulong rate)\n+static long owl_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct owl_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong new_rate;\n \ndiff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c\nindex b7bd9c9a342a..46a962f29bfe 100644\n--- a/drivers/clk/qcom/clock-apq8016.c\n+++ b/drivers/clk/qcom/clock-apq8016.c\n@@ -109,9 +109,9 @@ int apq8016_clk_init_uart(phys_addr_t base, unsigned long id)\n \n \treturn 0;\n }\n \n-static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)\n+static long apq8016_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tswitch (clk->id) {\ndiff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c\nindex 551f52d51977..063867303966 100644\n--- a/drivers/clk/qcom/clock-apq8096.c\n+++ b/drivers/clk/qcom/clock-apq8096.c\n@@ -77,9 +77,9 @@ static int clk_init_uart(struct msm_clk_priv *priv)\n \n \treturn 0;\n }\n \n-static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate)\n+static long apq8096_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tswitch (clk->id) {\ndiff --git a/drivers/clk/qcom/clock-ipq4019.c b/drivers/clk/qcom/clock-ipq4019.c\nindex f6760c6fb3df..8b9c19dfae64 100644\n--- a/drivers/clk/qcom/clock-ipq4019.c\n+++ b/drivers/clk/qcom/clock-ipq4019.c\n@@ -20,9 +20,9 @@\n #define BLSP1_QUP1_I2C_APPS_CMD_RCGR\t(0x200C)\n #define BLSP1_QUP2_I2C_APPS_CBCR\t(0x3010)\n #define BLSP1_QUP2_I2C_APPS_CMD_RCGR\t(0x3000)\n \n-static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)\n+static long ipq4019_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tswitch (clk->id) {\n \tcase GCC_BLSP1_UART1_APPS_CLK: /*UART1*/\n \t\t/* This clock is already initialized by SBL1 */\ndiff --git a/drivers/clk/qcom/clock-ipq5424.c b/drivers/clk/qcom/clock-ipq5424.c\nindex 40823a30ead2..a26ceda972c9 100644\n--- a/drivers/clk/qcom/clock-ipq5424.c\n+++ b/drivers/clk/qcom/clock-ipq5424.c\n@@ -19,9 +19,9 @@\n #include \"clock-qcom.h\"\n \n #define GCC_IM_SLEEP_CBCR\t0x1834020u\n \n-static ulong ipq5424_set_rate(struct clk *clk, ulong rate)\n+static long ipq5424_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tswitch (clk->id) {\ndiff --git a/drivers/clk/qcom/clock-ipq9574.c b/drivers/clk/qcom/clock-ipq9574.c\nindex b0af40360598..1c5f5ec195d9 100644\n--- a/drivers/clk/qcom/clock-ipq9574.c\n+++ b/drivers/clk/qcom/clock-ipq9574.c\n@@ -25,9 +25,9 @@\n #define GCC_SDCC1_AHB_CBCR\t\t\t0x33034\n #define GCC_SDCC1_APPS_CMD_RCGR\t\t\t0x33004\n #define GCC_SDCC1_ICE_CORE_CBCR\t\t\t0x33030\n \n-static ulong ipq9574_set_rate(struct clk *clk, ulong rate)\n+static long ipq9574_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tswitch (clk->id) {\ndiff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c\nindex 5a599085b500..2efa588968a3 100644\n--- a/drivers/clk/qcom/clock-qcm2290.c\n+++ b/drivers/clk/qcom/clock-qcm2290.c\n@@ -103,9 +103,9 @@ static const struct gate_clk qcm2290_clks[] = {\n \tGATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, 0x00000001),\n \tGATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, 0x00000001),\n };\n \n-static ulong qcm2290_set_rate(struct clk *clk, ulong rate)\n+static long qcm2290_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c\nindex 6df8285cb301..c6dc4d8ebacc 100644\n--- a/drivers/clk/qcom/clock-qcom.c\n+++ b/drivers/clk/qcom/clock-qcom.c\n@@ -241,9 +241,9 @@ static int msm_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static ulong msm_clk_set_rate(struct clk *clk, ulong rate)\n+static long msm_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev);\n \n \tif (data->set_rate)\ndiff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h\nindex 3a4550d85366..324094f5c7c6 100644\n--- a/drivers/clk/qcom/clock-qcom.h\n+++ b/drivers/clk/qcom/clock-qcom.h\n@@ -94,9 +94,9 @@ struct msm_clk_data {\n \tunsigned long\t\t\tnum_rcgs;\n \tconst char * const\t\t*dbg_rcg_names;\n \n \tint (*enable)(struct clk *clk);\n-\tunsigned long (*set_rate)(struct clk *clk, unsigned long rate);\n+\tlong (*set_rate)(struct clk *clk, unsigned long rate);\n };\n \n struct msm_clk_priv {\n \tphys_addr_t\t\tbase;\ndiff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c\nindex 8b11de03a7d9..866666fe4549 100644\n--- a/drivers/clk/qcom/clock-qcs404.c\n+++ b/drivers/clk/qcom/clock-qcs404.c\n@@ -92,9 +92,9 @@ static struct pll_vote_clk gpll1_vote_clk = {\n \t.ena_vote = APCS_GPLL_ENA_VOTE,\n \t.vote_bit = BIT(1),\n };\n \n-static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)\n+static long qcs404_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tswitch (clk->id) {\ndiff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c\nindex 2087fc38f63d..d6b53359c896 100644\n--- a/drivers/clk/qcom/clock-qcs615.c\n+++ b/drivers/clk/qcom/clock-qcs615.c\n@@ -32,9 +32,9 @@\n #define GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT BIT(25)\n #define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26)\n #define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27)\n \n-static ulong qcs615_set_rate(struct clk *clk, ulong rate)\n+static long qcs615_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tif (clk->id < priv->data->num_clks)\ndiff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c\nindex cd8aecdf788a..fd6359773e19 100644\n--- a/drivers/clk/qcom/clock-qcs8300.c\n+++ b/drivers/clk/qcom/clock-qcs8300.c\n@@ -16,9 +16,9 @@\n \n #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038\n #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020\n \n-static ulong qcs8300_set_rate(struct clk *clk, ulong rate)\n+static long qcs8300_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tif (clk->id < priv->data->num_clks)\ndiff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c\nindex 4957abf6f589..9b6c583e65c3 100644\n--- a/drivers/clk/qcom/clock-sa8775p.c\n+++ b/drivers/clk/qcom/clock-sa8775p.c\n@@ -43,9 +43,9 @@\n #define GCC_QUPV3_WRAP2_S6_CLK_ENA_BIT BIT(29)\n \n #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25)\n \n-static ulong sa8775p_set_rate(struct clk *clk, ulong rate)\n+static long sa8775p_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \n \tif (clk->id < priv->data->num_clks)\ndiff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c\nindex 7b6ed8260236..dd17eb7e4e28 100644\n--- a/drivers/clk/qcom/clock-sc7280.c\n+++ b/drivers/clk/qcom/clock-sc7280.c\n@@ -53,9 +53,9 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = {\n \tF(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),\n \t{ }\n };\n \n-static ulong sc7280_set_rate(struct clk *clk, ulong rate)\n+static long sc7280_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c\nindex c9a057cf6f9b..6f76dbe06f44 100644\n--- a/drivers/clk/qcom/clock-sdm845.c\n+++ b/drivers/clk/qcom/clock-sdm845.c\n@@ -67,9 +67,9 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {\n \tF(201500000, CFG_CLK_SRC_GPLL4, 4, 0, 0),\n \t{ }\n };\n \n-static ulong sdm670_clk_set_rate(struct clk *clk, ulong rate)\n+static long sdm670_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \n@@ -83,9 +83,9 @@ static ulong sdm670_clk_set_rate(struct clk *clk, ulong rate)\n \t\treturn 0;\n \t}\n }\n \n-static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)\n+static long sdm845_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm6115.c b/drivers/clk/qcom/clock-sm6115.c\nindex 17c2e5617580..542153b1f67e 100644\n--- a/drivers/clk/qcom/clock-sm6115.c\n+++ b/drivers/clk/qcom/clock-sm6115.c\n@@ -93,9 +93,9 @@ static const struct gate_clk sm6115_clks[] = {\n \tGATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, 0x00000001),\n \tGATE_CLK(GCC_UFS_CLKREF_CLK, 0x8c000, 0x00000001),\n };\n \n-static ulong sm6115_set_rate(struct clk *clk, ulong rate)\n+static long sm6115_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm6350.c b/drivers/clk/qcom/clock-sm6350.c\nindex ee6653848c7b..46a01981538f 100644\n--- a/drivers/clk/qcom/clock-sm6350.c\n+++ b/drivers/clk/qcom/clock-sm6350.c\n@@ -63,9 +63,9 @@ static struct pll_vote_clk gpll7_vote_clk = {\n \t.ena_vote = APCS_GPLLX_ENA_REG,\n \t.vote_bit = BIT(7),\n };\n \n-static ulong sm6350_set_rate(struct clk *clk, ulong rate)\n+static long sm6350_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm7150.c b/drivers/clk/qcom/clock-sm7150.c\nindex 8fe2076e55eb..132526ffd01f 100644\n--- a/drivers/clk/qcom/clock-sm7150.c\n+++ b/drivers/clk/qcom/clock-sm7150.c\n@@ -78,9 +78,9 @@ static const struct freq_tbl ftbl_gcc_usb3_prim_phy_aux_clk_src[] = {\n \tF(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),\n \t{ }\n };\n \n-static ulong sm7150_clk_set_rate(struct clk *clk, ulong rate)\n+static long sm7150_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm8150.c b/drivers/clk/qcom/clock-sm8150.c\nindex 7dd0d56eb430..be88a280fcbf 100644\n--- a/drivers/clk/qcom/clock-sm8150.c\n+++ b/drivers/clk/qcom/clock-sm8150.c\n@@ -92,9 +92,9 @@ static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {\n \tF(202000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),\n \t{ }\n };\n \n-static ulong sm8150_clk_set_rate(struct clk *clk, ulong rate)\n+static long sm8150_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm8250.c b/drivers/clk/qcom/clock-sm8250.c\nindex 37268c4eaf5a..eb5d802786cf 100644\n--- a/drivers/clk/qcom/clock-sm8250.c\n+++ b/drivers/clk/qcom/clock-sm8250.c\n@@ -53,9 +53,9 @@ static struct pll_vote_clk gpll9_vote_clk = {\n \t.ena_vote = APCS_GPLLX_ENA_REG,\n \t.vote_bit = BIT(9),\n };\n \n-static ulong sm8250_set_rate(struct clk *clk, ulong rate)\n+static long sm8250_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c\nindex 02d6e8d77345..538b5f0bf553 100644\n--- a/drivers/clk/qcom/clock-sm8550.c\n+++ b/drivers/clk/qcom/clock-sm8550.c\n@@ -66,9 +66,9 @@ static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {\n \tF(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),\n \t{ }\n };\n \n-static ulong sm8550_set_rate(struct clk *clk, ulong rate)\n+static long sm8550_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c\nindex fbd1a186d1ba..3cdb7ff9877a 100644\n--- a/drivers/clk/qcom/clock-sm8650.c\n+++ b/drivers/clk/qcom/clock-sm8650.c\n@@ -63,9 +63,9 @@ static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {\n \tF(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),\n \t{ }\n };\n \n-static ulong sm8650_set_rate(struct clk *clk, ulong rate)\n+static long sm8650_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c\nindex ee57a02564a3..c0421d7f6023 100644\n--- a/drivers/clk/qcom/clock-x1e80100.c\n+++ b/drivers/clk/qcom/clock-x1e80100.c\n@@ -63,9 +63,9 @@ static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {\n \tF(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),\n \t{ }\n };\n \n-static ulong x1e80100_set_rate(struct clk *clk, ulong rate)\n+static long x1e80100_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct msm_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct freq_tbl *freq;\n \ndiff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c\nindex e659ad39da7d..435ea3f5f37e 100644\n--- a/drivers/clk/renesas/clk-rcar-gen2.c\n+++ b/drivers/clk/renesas/clk-rcar-gen2.c\n@@ -240,9 +240,9 @@ static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)\n+static long gen2_clk_set_rate(struct clk *clk, ulong rate)\n {\n \t/* Force correct MMC-IF divider configuration if applicable */\n \tgen2_clk_setup_mmcif_div(clk, rate);\n \treturn gen2_clk_get_rate(clk);\ndiff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c\nindex ae21f2a663f8..4fe22b27c284 100644\n--- a/drivers/clk/renesas/clk-rcar-gen3.c\n+++ b/drivers/clk/renesas/clk-rcar-gen3.c\n@@ -432,9 +432,9 @@ static ulong gen3_clk_get_rate(struct clk *clk)\n {\n \treturn gen3_clk_get_rate64(clk);\n }\n \n-static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)\n+static long gen3_clk_set_rate(struct clk *clk, ulong rate)\n {\n \t/* Force correct SD-IF divider configuration if applicable */\n \tgen3_clk_setup_sdif_div(clk, rate);\n \treturn gen3_clk_get_rate64(clk);\ndiff --git a/drivers/clk/renesas/compound-clock.c b/drivers/clk/renesas/compound-clock.c\nindex 2dc3e2e0deea..fb8bf19398ba 100644\n--- a/drivers/clk/renesas/compound-clock.c\n+++ b/drivers/clk/renesas/compound-clock.c\n@@ -42,9 +42,9 @@ static ulong clk_compound_rate_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(&cc->per);\n }\n \n-static ulong clk_compound_rate_set_rate(struct clk *clk, ulong rate)\n+static long clk_compound_rate_set_rate(struct clk *clk, ulong rate)\n {\n \treturn 0;\t/* Set rate is not forwarded to SCP */\n }\n \ndiff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c\nindex 3ef98237ba15..91e1ace17ad9 100644\n--- a/drivers/clk/renesas/r9a06g032-clocks.c\n+++ b/drivers/clk/renesas/r9a06g032-clocks.c\n@@ -842,9 +842,9 @@ static ulong r9a06g032_div_get_rate(struct clk *clk)\n \t\tdiv = desc->div_max;\n \treturn DIV_ROUND_UP(parent_rate, div);\n }\n \n-static ulong r9a06g032_div_set_rate(struct clk *clk, ulong rate)\n+static long r9a06g032_div_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct r9a06g032_priv *clocks = dev_get_priv(clk->dev);\n \tconst struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);\n \tunsigned long parent_rate = r9a06g032_clk_get_parent_rate(clk);\n@@ -1018,9 +1018,9 @@ static ulong r9a06g032_clk_get_rate(struct clk *clk)\n \n \treturn ret;\n }\n \n-static ulong r9a06g032_clk_set_rate(struct clk *clk, ulong rate)\n+static long r9a06g032_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tconst struct r9a06g032_clkdesc *desc = r9a06g032_clk_get(clk);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c\nindex 03cb4f26d474..0401205bb96f 100644\n--- a/drivers/clk/renesas/rzg2l-cpg.c\n+++ b/drivers/clk/renesas/rzg2l-cpg.c\n@@ -279,9 +279,9 @@ static ulong rzg2l_cpg_clk_get_rate(struct clk *clk)\n {\n \treturn rzg2l_cpg_clk_get_rate_by_id(clk->dev, clk->id);\n }\n \n-static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate)\n+static long rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate)\n {\n \tstruct rzg2l_cpg_data *data =\n \t\t(struct rzg2l_cpg_data *)dev_get_driver_data(dev);\n \tconst ulong offset = CPG_CONF_OFFSET(cc->conf);\n@@ -345,9 +345,9 @@ static ulong rzg2l_sdhi_clk_set_rate(struct udevice *dev, const struct cpg_core_\n \n \treturn target_rate;\n }\n \n-static ulong rzg2l_core_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate)\n+static long rzg2l_core_clk_set_rate(struct udevice *dev, const struct cpg_core_clk *cc, ulong rate)\n {\n \tif (cc->type == CLK_TYPE_SD_MUX)\n \t\treturn rzg2l_sdhi_clk_set_rate(dev, cc, rate);\n \n@@ -391,9 +391,9 @@ static ulong rzg2l_cpg_clk_set_rate_by_id(struct udevice *dev, unsigned int id,\n \tdev_err(dev, \"Core clock ID %u not found\\n\", cpg_clk_id);\n \treturn -ENODEV;\n }\n \n-static ulong rzg2l_cpg_clk_set_rate(struct clk *clk, ulong rate)\n+static long rzg2l_cpg_clk_set_rate(struct clk *clk, ulong rate)\n {\n \treturn rzg2l_cpg_clk_set_rate_by_id(clk->dev, clk->id, rate);\n }\n \ndiff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c\nindex 6e7f745102d5..61ad0f7809e5 100644\n--- a/drivers/clk/rockchip/clk_px30.c\n+++ b/drivers/clk/rockchip/clk_px30.c\n@@ -1128,9 +1128,9 @@ static ulong px30_clk_get_pll_rate(struct px30_clk_priv *priv,\n \n \treturn rkclk_pll_get_rate(&cru->pll[pll_id], &cru->mode, pll_id);\n }\n \n-static ulong px30_clk_set_pll_rate(struct px30_clk_priv *priv,\n+static long px30_clk_set_pll_rate(struct px30_clk_priv *priv,\n \t\t\t\t   enum px30_pll_id pll_id, ulong hz)\n {\n \tstruct px30_cru *cru = priv->cru;\n \n@@ -1273,9 +1273,9 @@ static ulong px30_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong px30_clk_set_rate(struct clk *clk, ulong rate)\n+static long px30_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct px30_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \n@@ -1563,9 +1563,9 @@ static ulong px30_pmuclk_get_gpll_rate(struct px30_pmuclk_priv *priv)\n \n \treturn rkclk_pll_get_rate(&pmucru->pll, &pmucru->pmu_mode, GPLL);\n }\n \n-static ulong px30_pmuclk_set_gpll_rate(struct px30_pmuclk_priv *priv, ulong hz)\n+static long px30_pmuclk_set_gpll_rate(struct px30_pmuclk_priv *priv, ulong hz)\n {\n \tstruct px30_pmucru *pmucru = priv->pmucru;\n \tulong pclk_pmu_rate;\n \tu32 div;\n@@ -1712,9 +1712,9 @@ static ulong px30_pmuclk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate)\n+static long px30_pmuclk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct px30_pmuclk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c\nindex e575143341d9..c0aa23825410 100644\n--- a/drivers/clk/rockchip/clk_rk3036.c\n+++ b/drivers/clk/rockchip/clk_rk3036.c\n@@ -290,9 +290,9 @@ static ulong rk3036_clk_get_rate(struct clk *clk)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3036_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3036_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong new_rate, gclk_rate;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c\nindex 9b6f7a2b6b00..ce7c5956df31 100644\n--- a/drivers/clk/rockchip/clk_rk3066.c\n+++ b/drivers/clk/rockchip/clk_rk3066.c\n@@ -539,9 +539,9 @@ static ulong rk3066_clk_get_rate(struct clk *clk)\n \n \treturn new_rate;\n }\n \n-static ulong rk3066_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3066_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3066_clk_priv *priv = dev_get_priv(clk->dev);\n \tstruct rk3066_cru *cru = priv->cru;\n \tulong new_rate;\ndiff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c\nindex 4665f0d31152..0d132a1624c0 100644\n--- a/drivers/clk/rockchip/clk_rk3128.c\n+++ b/drivers/clk/rockchip/clk_rk3128.c\n@@ -503,9 +503,9 @@ static ulong rk3128_clk_get_rate(struct clk *clk)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3128_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3128_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong new_rate, gclk_rate;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c\nindex 1c75c2d9bf5b..d54a5dbb14b8 100644\n--- a/drivers/clk/rockchip/clk_rk3188.c\n+++ b/drivers/clk/rockchip/clk_rk3188.c\n@@ -494,9 +494,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)\n \n \treturn new_rate;\n }\n \n-static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3188_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3188_clk_priv *priv = dev_get_priv(clk->dev);\n \tstruct rk3188_cru *cru = priv->cru;\n \tulong new_rate;\ndiff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c\nindex f40fe68de45b..fb438c6fabee 100644\n--- a/drivers/clk/rockchip/clk_rk322x.c\n+++ b/drivers/clk/rockchip/clk_rk322x.c\n@@ -372,9 +372,9 @@ static ulong rk322x_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk322x_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk322x_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong new_rate, gclk_rate;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c\nindex b672e728fb0a..10aed7c757a6 100644\n--- a/drivers/clk/rockchip/clk_rk3288.c\n+++ b/drivers/clk/rockchip/clk_rk3288.c\n@@ -787,9 +787,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)\n \n \treturn new_rate;\n }\n \n-static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3288_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3288_clk_priv *priv = dev_get_priv(clk->dev);\n \tstruct rockchip_cru *cru = priv->cru;\n \tulong new_rate, gclk_rate;\ndiff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c\nindex 828d545f5fab..99f8d78b377e 100644\n--- a/drivers/clk/rockchip/clk_rk3308.c\n+++ b/drivers/clk/rockchip/clk_rk3308.c\n@@ -1009,9 +1009,9 @@ static ulong rk3308_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3308_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3308_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c\nindex cb5df70bfaa0..b251a48e17f5 100644\n--- a/drivers/clk/rockchip/clk_rk3328.c\n+++ b/drivers/clk/rockchip/clk_rk3328.c\n@@ -713,9 +713,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3328_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3328_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\nindex 9949ebaf23fe..d056ed01e81d 100644\n--- a/drivers/clk/rockchip/clk_rk3368.c\n+++ b/drivers/clk/rockchip/clk_rk3368.c\n@@ -484,9 +484,9 @@ static ulong rk3368_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3368_clk_set_rate(struct clk *clk, ulong rate)\n {\n \t__maybe_unused struct rk3368_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c\nindex 976afc57f0b7..3c736ce0de73 100644\n--- a/drivers/clk/rockchip/clk_rk3399.c\n+++ b/drivers/clk/rockchip/clk_rk3399.c\n@@ -1008,9 +1008,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3399_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3399_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \n@@ -1626,9 +1626,9 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)\n+static long rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c\nindex f81ff829db9d..70de2efa7078 100644\n--- a/drivers/clk/rockchip/clk_rk3528.c\n+++ b/drivers/clk/rockchip/clk_rk3528.c\n@@ -246,9 +246,9 @@ static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,\n \n \treturn DIV_TO_RATE(priv->ppll_hz, div);\n }\n \n-static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,\n+static long rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,\n \t\t\t\t\t ulong clk_id, ulong rate)\n {\n \tstruct rk3528_cru *cru = priv->cru;\n \tu32 id, div, mask, shift;\n@@ -399,9 +399,9 @@ static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,\n \t/* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */\n \treturn is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);\n }\n \n-static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,\n+static long rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,\n \t\t\t\t\t  ulong clk_id, ulong rate)\n {\n \tstruct rk3528_cru *cru = priv->cru;\n \tu32 sel, div, mask, shift, con;\n@@ -1199,9 +1199,9 @@ static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)\n \n \treturn rate;\n }\n \n-static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,\n+static long rk3528_uart_set_rate(struct rk3528_clk_priv *priv,\n \t\t\t\t  ulong clk_id, ulong rate)\n {\n \tstruct rk3528_cru *cru = priv->cru;\n \tu32 sel_shift, sel_mask, div_shift, div_mask;\n@@ -1421,9 +1421,9 @@ static ulong rk3528_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n };\n \n-static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3528_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3528_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c\nindex e07838e2c82b..b8329c6d3ad0 100644\n--- a/drivers/clk/rockchip/clk_rk3568.c\n+++ b/drivers/clk/rockchip/clk_rk3568.c\n@@ -385,9 +385,9 @@ static ulong rk3568_pmuclk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)\n+static long rk3568_pmuclk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3568_pmuclk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \n@@ -647,9 +647,9 @@ static ulong rk3568_cpll_div_get_rate(struct rk3568_clk_priv *priv,\n \tdiv = (readl(&cru->clksel_con[con]) & mask) >> shift;\n \treturn DIV_TO_RATE(priv->cpll_hz, div);\n }\n \n-static ulong rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,\n+static long rk3568_cpll_div_set_rate(struct rk3568_clk_priv *priv,\n \t\t\t\t      ulong clk_id, ulong rate)\n {\n \tstruct rk3568_cru *cru = priv->cru;\n \tint div, mask, shift, con;\n@@ -1334,9 +1334,9 @@ static ulong rk3568_crypto_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static ulong rk3568_crypto_set_rate(struct rk3568_clk_priv *priv,\n+static long rk3568_crypto_set_rate(struct rk3568_clk_priv *priv,\n \t\t\t\t    ulong clk_id, ulong rate)\n {\n \tstruct rk3568_cru *cru = priv->cru;\n \tu32 src_clk, mask, shift;\n@@ -2241,9 +2241,9 @@ static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)\n \t\treturn OSC_HZ;\n \t}\n }\n \n-static ulong rk3568_uart_set_rate(struct rk3568_clk_priv *priv,\n+static long rk3568_uart_set_rate(struct rk3568_clk_priv *priv,\n \t\t\t\t  ulong clk_id, ulong rate)\n {\n \tstruct rk3568_cru *cru = priv->cru;\n \tu32 reg, clk_src, uart_src, div;\n@@ -2492,9 +2492,9 @@ static ulong rk3568_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n };\n \n-static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3568_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3568_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c\nindex 60dc576bed4a..5c86ba773527 100644\n--- a/drivers/clk/rockchip/clk_rk3576.c\n+++ b/drivers/clk/rockchip/clk_rk3576.c\n@@ -1654,9 +1654,9 @@ static ulong rk3576_uart_frac_get_rate(struct rk3576_clk_priv *priv, ulong clk_i\n \tm >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;\n \treturn p_rate * n / m;\n }\n \n-static ulong rk3576_uart_frac_set_rate(struct rk3576_clk_priv *priv,\n+static long rk3576_uart_frac_set_rate(struct rk3576_clk_priv *priv,\n \t\t\t\t       ulong clk_id, ulong rate)\n {\n \tstruct rk3576_cru *cru = priv->cru;\n \tu32 reg, clk_src, p_rate;\n@@ -1786,9 +1786,9 @@ static ulong rk3576_uart_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)\n \n \treturn DIV_TO_RATE(p_rate, div);\n }\n \n-static ulong rk3576_uart_set_rate(struct rk3576_clk_priv *priv,\n+static long rk3576_uart_set_rate(struct rk3576_clk_priv *priv,\n \t\t\t\t  ulong clk_id, ulong rate)\n {\n \tstruct rk3576_cru *cru = priv->cru;\n \tu32 reg, clk_src = 0, div = 0;\n@@ -2056,9 +2056,9 @@ static ulong rk3576_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n };\n \n-static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3576_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3576_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \ndiff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c\nindex 3047f1630bcc..a1332ef8834e 100644\n--- a/drivers/clk/rockchip/clk_rk3588.c\n+++ b/drivers/clk/rockchip/clk_rk3588.c\n@@ -1329,9 +1329,9 @@ static ulong rk3588_uart_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)\n \t\treturn OSC_HZ;\n \t}\n }\n \n-static ulong rk3588_uart_set_rate(struct rk3588_clk_priv *priv,\n+static long rk3588_uart_set_rate(struct rk3588_clk_priv *priv,\n \t\t\t\t  ulong clk_id, ulong rate)\n {\n \tstruct rk3588_cru *cru = priv->cru;\n \tu32 reg, clk_src, uart_src, div;\n@@ -1438,9 +1438,9 @@ static ulong rk3588_pciephy_get_rate(struct rk3588_clk_priv *priv, ulong clk_id)\n \telse\n \t\treturn OSC_HZ;\n }\n \n-static ulong rk3588_pciephy_set_rate(struct rk3588_clk_priv *priv,\n+static long rk3588_pciephy_set_rate(struct rk3588_clk_priv *priv,\n \t\t\t\t     ulong clk_id, ulong rate)\n {\n \tstruct rk3588_cru *cru = priv->cru;\n \tu32 clk_src, div;\n@@ -1649,9 +1649,9 @@ static ulong rk3588_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n };\n \n-static ulong rk3588_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3588_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rk3588_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \n@@ -2086,9 +2086,9 @@ static ulong rk3588_scru_clk_get_rate(struct clk *clk)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static ulong rk3588_scru_clk_set_rate(struct clk *clk, ulong rate)\n+static long rk3588_scru_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tu32 div, sel;\n \n \tswitch (clk->id) {\ndiff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c\nindex 98e226ec61a0..80658b2c5e02 100644\n--- a/drivers/clk/rockchip/clk_rv1108.c\n+++ b/drivers/clk/rockchip/clk_rv1108.c\n@@ -571,9 +571,9 @@ static ulong rv1108_clk_get_rate(struct clk *clk)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)\n+static long rv1108_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rv1108_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong new_rate;\n \ndiff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c\nindex caa1512719eb..84f5a43599da 100644\n--- a/drivers/clk/rockchip/clk_rv1126.c\n+++ b/drivers/clk/rockchip/clk_rv1126.c\n@@ -68,9 +68,9 @@ static struct rockchip_pll_clock rv1126_pll_clks[] = {\n \t[GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0),\n \t\t     RV1126_PMU_MODE, 0, 10, 0, rv1126_pll_rates),\n };\n \n-static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,\n+static long rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,\n \t\t\t\t  struct rv1126_pmuclk_priv *pmu_priv,\n \t\t\t\t  ulong rate);\n /*\n  *\n@@ -404,9 +404,9 @@ static ulong rv1126_pmuclk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate)\n+static long rv1126_pmuclk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \n@@ -1514,9 +1514,9 @@ static ulong rv1126_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n };\n \n-static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate)\n+static long rv1126_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct rv1126_clk_priv *priv = dev_get_priv(clk->dev);\n \tulong ret = 0;\n \n@@ -1707,9 +1707,9 @@ static struct clk_ops_uboot rv1126_clk_ops = {\n \t.set_parent = rv1126_clk_set_parent,\n #endif\n };\n \n-static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,\n+static long rv1126_gpll_set_rate(struct rv1126_clk_priv *priv,\n \t\t\t\t  struct rv1126_pmuclk_priv *pmu_priv,\n \t\t\t\t  ulong rate)\n {\n \tulong emmc_rate, sfc_rate, nandc_rate;\ndiff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c\nindex dc84d4b6386d..f8e9d77e18fe 100644\n--- a/drivers/clk/sifive/sifive-prci.c\n+++ b/drivers/clk/sifive/sifive-prci.c\n@@ -580,9 +580,9 @@ static ulong sifive_prci_get_rate(struct clk *clk)\n \n \treturn pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data));\n }\n \n-static ulong sifive_prci_set_rate(struct clk *clk, ulong rate)\n+static long sifive_prci_set_rate(struct clk *clk, ulong rate)\n {\n \tint err;\n \tstruct __prci_clock *pc;\n \tstruct prci_clk_desc *data =\ndiff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c\nindex c8e5f7f53ea2..2cc702cb1b3b 100644\n--- a/drivers/clk/sophgo/clk-cv1800b.c\n+++ b/drivers/clk/sophgo/clk-cv1800b.c\n@@ -707,9 +707,9 @@ static ulong cv1800b_clk_get_rate(struct clk *clk)\n \t\treturn err;\n \treturn clk_get_rate(c);\n }\n \n-static ulong cv1800b_clk_set_rate(struct clk *clk, ulong rate)\n+static long cv1800b_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk *c;\n \tint err = clk_get_by_id(CV1800B_CLK_ID_TRANSFORM(clk->id), &c);\n \ndiff --git a/drivers/clk/sophgo/clk-ip.c b/drivers/clk/sophgo/clk-ip.c\nindex 7ac631126721..78ba582b4096 100644\n--- a/drivers/clk/sophgo/clk-ip.c\n+++ b/drivers/clk/sophgo/clk-ip.c\n@@ -93,9 +93,9 @@ static ulong div_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val);\n }\n \n-static ulong div_set_rate(struct clk *clk, ulong rate)\n+static long div_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_div *div = to_cv1800b_clk_div(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tu32 val;\n@@ -136,9 +136,9 @@ static ulong bypass_div_get_rate(struct clk *clk)\n \n \treturn div_get_rate(clk);\n }\n \n-static ulong bypass_div_set_rate(struct clk *clk, ulong rate)\n+static long bypass_div_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_bypass_div *div = to_cv1800b_clk_bypass_div(clk);\n \n \tif (cv1800b_clk_getbit(div->div.base, &div->bypass))\n@@ -291,9 +291,9 @@ static ulong mux_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val);\n }\n \n-static ulong mux_set_rate(struct clk *clk, ulong rate)\n+static long mux_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_mux *mux = to_cv1800b_clk_mux(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tulong val;\n@@ -347,9 +347,9 @@ static ulong bypass_mux_get_rate(struct clk *clk)\n \n \treturn mux_get_rate(clk);\n }\n \n-static ulong bypass_mux_set_rate(struct clk *clk, ulong rate)\n+static long bypass_mux_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_bypass_mux *mux = to_cv1800b_clk_bypass_mux(clk);\n \n \tif (cv1800b_clk_getbit(mux->mux.base, &mux->bypass))\n@@ -432,9 +432,9 @@ static ulong mmux_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), val);\n }\n \n-static ulong mmux_set_rate(struct clk *clk, ulong rate)\n+static long mmux_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_mmux *mmux = to_cv1800b_clk_mmux(clk);\n \tint clk_sel = 1;\n \tulong parent_rate = clk_get_parent_rate(clk);\n@@ -561,9 +561,9 @@ static void aclk_determine_mn(ulong parent_rate, ulong rate, u32 *m, u32 *n)\n \t*m = tm / tcommon;\n \t*n = tn / tcommon;\n }\n \n-static ulong aclk_set_rate(struct clk *clk, ulong rate)\n+static long aclk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_audio *aclk = to_cv1800b_clk_audio(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tu32 m, n;\ndiff --git a/drivers/clk/sophgo/clk-pll.c b/drivers/clk/sophgo/clk-pll.c\nindex 6ef50f00171d..72dfead33dd1 100644\n--- a/drivers/clk/sophgo/clk-pll.c\n+++ b/drivers/clk/sophgo/clk-pll.c\n@@ -63,9 +63,9 @@ static ulong cv1800b_ipll_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_DOWN_ULL(parent_rate * div, pre_div * post_div);\n }\n \n-static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate)\n+static long cv1800b_ipll_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_ipll *pll = to_clk_ipll(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tu32 pre_div, post_div, div;\n@@ -187,9 +187,9 @@ static ulong cv1800b_find_syn(ulong rate, ulong parent_rate, ulong pre_div, ulon\n \t*syn = syn_min;\n \treturn new_rate;\n }\n \n-static ulong cv1800b_fpll_set_rate(struct clk *clk, ulong rate)\n+static long cv1800b_fpll_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct cv1800b_clk_fpll *pll = to_clk_fpll(clk);\n \tulong parent_rate = clk_get_parent_rate(clk);\n \tu32 pre_div, post_div, div;\ndiff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c\nindex d12dec9a1f86..e9299aceee17 100644\n--- a/drivers/clk/starfive/clk-jh7110-pll.c\n+++ b/drivers/clk/starfive/clk-jh7110-pll.c\n@@ -299,9 +299,9 @@ static ulong jh7110_pllx_recalc_rate(struct clk *clk)\n \n \treturn refclk;\n }\n \n-static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)\n+static long jh7110_pllx_set_rate(struct clk *clk, ulong drate)\n {\n \tstruct clk_jh7110_pllx *pll = to_clk_pllx(dev_get_clk_ptr(clk->dev));\n \tconst struct starfive_pllx_rate *rate;\n \ndiff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c\nindex 834f0d8379e3..fe581a422eb2 100644\n--- a/drivers/clk/stm32/clk-stm32-core.c\n+++ b/drivers/clk/stm32/clk-stm32-core.c\n@@ -165,9 +165,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)\n \n \treturn ops->get_rate(c);\n }\n \n-static ulong stm32_clk_set_rate(struct clk *clk, unsigned long clk_rate)\n+static long stm32_clk_set_rate(struct clk *clk, unsigned long clk_rate)\n {\n \tconst struct clk_ops_uboot *ops;\n \tstruct clk *c = NULL;\n \ndiff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c\nindex 6c3a369797d9..1cfa511ff088 100644\n--- a/drivers/clk/stm32/clk-stm32f.c\n+++ b/drivers/clk/stm32/clk-stm32f.c\n@@ -494,9 +494,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)\n \t\treturn -EINVAL;\n \t}\n }\n \n-static ulong stm32_set_rate(struct clk *clk, ulong rate)\n+static long stm32_set_rate(struct clk *clk, ulong rate)\n {\n #ifdef CONFIG_VIDEO_STM32\n \tstruct stm32_clk *priv = dev_get_priv(clk->dev);\n \tstruct stm32_rcc_regs *regs = priv->base;\ndiff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c\nindex a7d0b55e060b..74ce9b15eef6 100644\n--- a/drivers/clk/stm32/clk-stm32mp1.c\n+++ b/drivers/clk/stm32/clk-stm32mp1.c\n@@ -2155,9 +2155,9 @@ static int pll_set_output_rate(struct udevice *dev,\n \n \treturn 0;\n }\n \n-static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)\n+static long stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)\n {\n \tstruct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);\n \tint p;\n \ndiff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c\nindex 6e315f502aa5..fd2b9082a96b 100644\n--- a/drivers/clk/tegra/tegra-car-clk.c\n+++ b/drivers/clk/tegra/tegra-car-clk.c\n@@ -59,9 +59,9 @@ static ulong tegra_car_clk_get_rate(struct clk *clk)\n \n \treturn -1U;\n }\n \n-static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)\n+static long tegra_car_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tenum clock_id parent;\n \n \tdebug(\"%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\\n\", __func__, clk, rate,\ndiff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c\nindex 99e0a9f28d9c..90c91096c411 100644\n--- a/drivers/clk/tegra/tegra186-clk.c\n+++ b/drivers/clk/tegra/tegra186-clk.c\n@@ -27,9 +27,9 @@ static ulong tegra186_clk_get_rate(struct clk *clk)\n \n \treturn resp.clk_get_rate.rate;\n }\n \n-static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate)\n+static long tegra186_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct mrq_clk_request req;\n \tstruct mrq_clk_response resp;\n \tint ret;\ndiff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c\nindex 16188d56f73a..697a561f8030 100644\n--- a/drivers/clk/thead/clk-th1520-ap.c\n+++ b/drivers/clk/thead/clk-th1520-ap.c\n@@ -989,9 +989,9 @@ static ulong th1520_clk_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(c);\n }\n \n-static ulong th1520_clk_set_rate(struct clk *clk, ulong rate)\n+static long th1520_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk *c;\n \tint ret;\n \ndiff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c\nindex 1726233df173..df90d157bb07 100644\n--- a/drivers/clk/ti/clk-am3-dpll.c\n+++ b/drivers/clk/ti/clk-am3-dpll.c\n@@ -201,9 +201,9 @@ static void clk_ti_am3_dpll_ssc_program(struct clk *clk)\n \n \tclk_ti_writel(ctrl, &priv->clkmode_reg);\n }\n \n-static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)\n+static long clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);\n \tu32 v;\n \tulong round_rate;\ndiff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c\nindex f959b5633d64..4d216dded96b 100644\n--- a/drivers/clk/ti/clk-divider.c\n+++ b/drivers/clk/ti/clk-divider.c\n@@ -179,9 +179,9 @@ static ulong clk_ti_divider_round_rate(struct clk *clk, ulong rate)\n \n \treturn DIV_ROUND_UP(parent_rate, div);\n }\n \n-static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)\n+static long clk_ti_divider_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_ti_divider_priv *priv = dev_get_priv(clk->dev);\n \tulong parent_rate;\n \tint div;\ndiff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c\nindex 9766f50a2e4d..b47f7cd3a19e 100644\n--- a/drivers/clk/ti/clk-k3-pll.c\n+++ b/drivers/clk/ti/clk-k3-pll.c\n@@ -343,9 +343,9 @@ static void ti_pll_clk_bypass(struct ti_pll_clk *pll, bool bypass)\n \n \twritel(ctrl, pll->base + PLL_16FFT_CTRL);\n }\n \n-static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)\n+static long ti_pll_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct ti_pll_clk *pll = to_clk_pll(clk);\n \tu64 current_freq;\n \tu64 parent_freq = clk_get_parent_rate(clk);\ndiff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c\nindex cb7e016c637a..f2afc7e7ec91 100644\n--- a/drivers/clk/ti/clk-k3.c\n+++ b/drivers/clk/ti/clk-k3.c\n@@ -257,9 +257,9 @@ static ulong ti_clk_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(clkp);\n }\n \n-static ulong ti_clk_set_rate(struct clk *clk, ulong rate)\n+static long ti_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct ti_clk_data *data = dev_get_priv(clk->dev);\n \tstruct clk *clkp = data->map[clk->id].clk;\n \tint div = 1;\ndiff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c\nindex 60bdde35e510..1b29f2149b76 100644\n--- a/drivers/clk/ti/clk-mux.c\n+++ b/drivers/clk/ti/clk-mux.c\n@@ -99,9 +99,9 @@ static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)\n \tclk_ti_latch(&priv->reg, priv->latch);\n \treturn 0;\n }\n \n-static ulong clk_ti_mux_set_rate(struct clk *clk, ulong rate)\n+static long clk_ti_mux_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);\n \tstruct clk *parent;\n \tint index;\ndiff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c\nindex fdf49a759983..08637c136ec5 100644\n--- a/drivers/clk/ti/clk-sci.c\n+++ b/drivers/clk/ti/clk-sci.c\n@@ -83,9 +83,9 @@ static ulong ti_sci_clk_get_rate(struct clk *clk)\n \n \treturn current_freq;\n }\n \n-static ulong ti_sci_clk_set_rate(struct clk *clk, ulong rate)\n+static long ti_sci_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct ti_sci_clk_data *data = dev_get_priv(clk->dev);\n \tconst struct ti_sci_handle *sci = data->sci;\n \tconst struct ti_sci_clk_ops *cops = &sci->ops.clk_ops;\ndiff --git a/drivers/clk/uccf/clk-composite.c b/drivers/clk/uccf/clk-composite.c\nindex 0fdc8c2e6fec..a77646d4f3f3 100644\n--- a/drivers/clk/uccf/clk-composite.c\n+++ b/drivers/clk/uccf/clk-composite.c\n@@ -57,9 +57,9 @@ static unsigned long clk_composite_recalc_rate(struct clk *clk)\n \telse\n \t\treturn clk_get_parent_rate(clk);\n }\n \n-static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)\n+static long clk_composite_set_rate(struct clk *clk, unsigned long rate)\n {\n \tstruct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?\n \t\t(struct clk *)dev_get_clk_ptr(clk->dev) : clk);\n \tconst struct clk_ops_uboot *rate_ops = composite->rate_ops;\ndiff --git a/drivers/clk/uccf/clk-divider.c b/drivers/clk/uccf/clk-divider.c\nindex 8d65fd94c176..f5ed2a9974b3 100644\n--- a/drivers/clk/uccf/clk-divider.c\n+++ b/drivers/clk/uccf/clk-divider.c\n@@ -153,9 +153,9 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,\n \n \treturn min_t(unsigned int, value, clk_div_mask(width));\n }\n \n-static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)\n+static long clk_divider_set_rate(struct clk *clk, unsigned long rate)\n {\n \tstruct clk_divider *divider = to_clk_divider(clk);\n \tunsigned long parent_rate = clk_get_parent_rate(clk);\n \tint value;\ndiff --git a/drivers/clk/uccf/clk.c b/drivers/clk/uccf/clk.c\nindex f04b3b23dbd1..ee410db76932 100644\n--- a/drivers/clk/uccf/clk.c\n+++ b/drivers/clk/uccf/clk.c\n@@ -87,9 +87,9 @@ ulong ccf_clk_get_rate(struct clk *clk)\n \t\treturn err;\n \treturn clk_get_rate(c);\n }\n \n-ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate)\n+long ccf_clk_set_rate(struct clk *clk, unsigned long rate)\n {\n \tstruct clk *c;\n \tint err = clk_get_by_id(clk->id, &c);\n \ndiff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c\nindex 3a4c9f6687f7..f10c402a3e47 100644\n--- a/drivers/clk/uniphier/clk-uniphier-core.c\n+++ b/drivers/clk/uniphier/clk-uniphier-core.c\n@@ -172,9 +172,9 @@ static unsigned long uniphier_clk_get_rate(struct clk *clk)\n \n \treturn __uniphier_clk_get_rate(priv, data);\n }\n \n-static unsigned long __uniphier_clk_set_rate(\n+static long __uniphier_clk_set_rate(\n \t\t\t\t\tstruct uniphier_clk_priv *priv,\n \t\t\t\t\tconst struct uniphier_clk_data *data,\n \t\t\t\t\tunsigned long rate, bool set)\n {\n@@ -228,9 +228,9 @@ static unsigned long __uniphier_clk_set_rate(\n \treturn best_rate = __uniphier_clk_set_rate(priv, best_parent_data,\n \t\t\t\t\t\t   rate, true);\n }\n \n-static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)\n+static long uniphier_clk_set_rate(struct clk *clk, ulong rate)\n {\n \tstruct uniphier_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst struct uniphier_clk_data *data;\n \ndiff --git a/include/clk-uclass.h b/include/clk-uclass.h\nindex a26603bf2f0a..6272dbb35799 100644\n--- a/include/clk-uclass.h\n+++ b/include/clk-uclass.h\n@@ -33,9 +33,9 @@ struct clk_ops_uboot {\n \t\t\tstruct ofnode_phandle_args *args);\n \tint (*request)(struct clk *clock);\n \tulong (*round_rate)(struct clk *clk, ulong rate);\n \tulong (*get_rate)(struct clk *clk);\n-\tulong (*set_rate)(struct clk *clk, ulong rate);\n+\tlong (*set_rate)(struct clk *clk, ulong rate);\n \tint (*set_parent)(struct clk *clk, struct clk *parent);\n \tint (*enable)(struct clk *clk);\n \tint (*disable)(struct clk *clk);\n #if IS_ENABLED(CONFIG_CMD_CLK)\ndiff --git a/include/clk.h b/include/clk.h\nindex 90b42a618675..3cd080b43264 100644\n--- a/include/clk.h\n+++ b/include/clk.h\n@@ -501,9 +501,9 @@ ulong clk_round_rate(struct clk *clk, ulong rate);\n  * @rate:\tNew clock rate in Hz.\n  *\n  * Return: new rate, or -ve error code.\n  */\n-ulong clk_set_rate(struct clk *clk, ulong rate);\n+long clk_set_rate(struct clk *clk, ulong rate);\n \n /**\n  * clk_set_parent() - Set current clock parent.\n  * @clk:\tA clock struct that was previously successfully requested by\n",
    "prefixes": [
        "v2",
        "5/7"
    ]
}