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GET /api/patches/2218609/?format=api
{ "id": 2218609, "url": "http://patchwork.ozlabs.org/api/patches/2218609/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260401-casey-ccf-clk-prep-v2-3-16a78c8c62da@linaro.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401-casey-ccf-clk-prep-v2-3-16a78c8c62da@linaro.org>", "list_archive_url": null, "date": "2026-04-01T14:34:04", "name": "[v2,3/7] clk: rename clk_ops to clk_ops_uboot", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "368ed6cb39c8ba58b609f4c7193a1b047c5ed590", "submitter": { "id": 90679, "url": "http://patchwork.ozlabs.org/api/people/90679/?format=api", "name": "Casey Connolly", "email": "casey.connolly@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260401-casey-ccf-clk-prep-v2-3-16a78c8c62da@linaro.org/mbox/", "series": [ { "id": 498343, "url": "http://patchwork.ozlabs.org/api/series/498343/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498343", "date": "2026-04-01T14:34:02", "name": "clk: prepare for adding Linux CCF port", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498343/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218609/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218609/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org 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clk_ops to clk_ops_uboot", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260401-casey-ccf-clk-prep-v2-3-16a78c8c62da@linaro.org>", "References": "<20260401-casey-ccf-clk-prep-v2-0-16a78c8c62da@linaro.org>", "In-Reply-To": "<20260401-casey-ccf-clk-prep-v2-0-16a78c8c62da@linaro.org>", "To": "Tom Rini <trini@konsulko.com>, Lukasz Majewski <lukma@denx.de>,\n Marek Vasut <marex@denx.de>", "Cc": "Casey Connolly <casey.connolly@linaro.org>,\n Neil Armstrong <neil.armstrong@linaro.org>,\n Quentin Schulz <quentin.schulz@cherry.de>,\n Mattijs Korpershoek <mkorpershoek@kernel.org>, u-boot@lists.denx.de,\n u-boot-amlogic@groups.io, u-boot-qcom@groups.io", "X-Mailer": "b4 0.15-dev-47773", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=129058;\n i=casey.connolly@linaro.org; h=from:subject:message-id;\n bh=w/i3Dgl9enEsRv6+wLJ7FjaMxbF8tmgDMb4AmmiO8sc=;\n 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<u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "In preparation for supporting full CCF, rename U-Boot's clk_ops\nto clk_ops_uboot, these ops are specific to UCLASS_CLK and are too\nincompatible with full CCF.\n\nSigned-off-by: Casey Connolly <casey.connolly@linaro.org>\n---\n arch/arm/cpu/armv7/bcm281xx/clk-core.c | 8 ++++----\n arch/arm/cpu/armv7/bcm281xx/clk-core.h | 14 +++++++-------\n cmd/clk.c | 2 +-\n drivers/clk/adi/clk-adi-pll.c | 2 +-\n drivers/clk/adi/clk-shared.c | 2 +-\n drivers/clk/adi/clk.h | 2 +-\n drivers/clk/airoha/clk-airoha.c | 2 +-\n drivers/clk/altera/clk-agilex.c | 2 +-\n drivers/clk/altera/clk-agilex5.c | 2 +-\n drivers/clk/altera/clk-arria10.c | 2 +-\n drivers/clk/altera/clk-mem-n5x.c | 2 +-\n drivers/clk/altera/clk-n5x.c | 2 +-\n drivers/clk/aspeed/clk_ast2500.c | 2 +-\n drivers/clk/aspeed/clk_ast2600.c | 2 +-\n drivers/clk/at91/clk-generic.c | 2 +-\n drivers/clk/at91/clk-main.c | 8 ++++----\n drivers/clk/at91/clk-master.c | 6 +++---\n drivers/clk/at91/clk-peripheral.c | 4 ++--\n drivers/clk/at91/clk-programmable.c | 2 +-\n drivers/clk/at91/clk-sam9x60-pll.c | 6 +++---\n drivers/clk/at91/clk-sam9x60-usb.c | 2 +-\n drivers/clk/at91/clk-system.c | 2 +-\n drivers/clk/at91/clk-utmi.c | 4 ++--\n drivers/clk/at91/compat.c | 22 +++++++++++-----------\n drivers/clk/at91/pmc.c | 2 +-\n drivers/clk/at91/pmc.h | 2 +-\n drivers/clk/at91/sckc.c | 4 ++--\n drivers/clk/clk-cdce9xx.c | 2 +-\n drivers/clk/clk-gpio.c | 2 +-\n drivers/clk/clk-hsdk-cgu.c | 2 +-\n drivers/clk/clk-stub.c | 2 +-\n drivers/clk/clk-uclass.c | 22 +++++++++++-----------\n drivers/clk/clk-xlnx-clock-wizard.c | 2 +-\n drivers/clk/clk_bcm6345.c | 2 +-\n drivers/clk/clk_boston.c | 2 +-\n drivers/clk/clk_fixed_factor.c | 2 +-\n drivers/clk/clk_fixed_rate.c | 4 ++--\n drivers/clk/clk_k210.c | 2 +-\n drivers/clk/clk_octeon.c | 2 +-\n drivers/clk/clk_pic32.c | 2 +-\n drivers/clk/clk_sandbox.c | 2 +-\n drivers/clk/clk_scmi.c | 2 +-\n drivers/clk/clk_versaclock.c | 14 +++++++-------\n drivers/clk/clk_versal.c | 2 +-\n drivers/clk/clk_vexpress_osc.c | 2 +-\n drivers/clk/clk_zynq.c | 2 +-\n drivers/clk/clk_zynqmp.c | 2 +-\n drivers/clk/exynos/clk-exynos7420.c | 6 +++---\n drivers/clk/exynos/clk-pll.c | 4 ++--\n drivers/clk/exynos/clk.h | 2 +-\n drivers/clk/ics8n3qv01.c | 2 +-\n drivers/clk/imx/clk-composite-8m.c | 4 ++--\n drivers/clk/imx/clk-composite-93.c | 2 +-\n drivers/clk/imx/clk-fracn-gppll.c | 2 +-\n drivers/clk/imx/clk-gate-93.c | 2 +-\n drivers/clk/imx/clk-gate2.c | 2 +-\n drivers/clk/imx/clk-imx6q.c | 2 +-\n drivers/clk/imx/clk-imx6ul.c | 2 +-\n drivers/clk/imx/clk-imx8.c | 2 +-\n drivers/clk/imx/clk-imxrt1020.c | 2 +-\n drivers/clk/imx/clk-imxrt1170.c | 2 +-\n drivers/clk/imx/clk-pfd.c | 2 +-\n drivers/clk/imx/clk-pll14xx.c | 4 ++--\n drivers/clk/imx/clk-pllv3.c | 10 +++++-----\n drivers/clk/intel/clk_intel.c | 2 +-\n drivers/clk/mediatek/clk-mtk.c | 12 ++++++------\n drivers/clk/mediatek/clk-mtk.h | 10 +++++-----\n drivers/clk/meson/a1.c | 2 +-\n drivers/clk/meson/axg-ao.c | 2 +-\n drivers/clk/meson/axg.c | 2 +-\n drivers/clk/meson/clk-measure.c | 2 +-\n drivers/clk/meson/g12a-ao.c | 2 +-\n drivers/clk/meson/g12a.c | 2 +-\n drivers/clk/meson/gxbb.c | 2 +-\n drivers/clk/microchip/mpfs_clk_cfg.c | 2 +-\n drivers/clk/microchip/mpfs_clk_msspll.c | 2 +-\n drivers/clk/microchip/mpfs_clk_periph.c | 2 +-\n drivers/clk/mpc83xx_clk.c | 2 +-\n drivers/clk/mtmips/clk-mt7620.c | 2 +-\n drivers/clk/mtmips/clk-mt7621.c | 2 +-\n drivers/clk/mtmips/clk-mt7628.c | 2 +-\n drivers/clk/mvebu/armada-37xx-periph.c | 2 +-\n drivers/clk/mvebu/armada-37xx-tbg.c | 2 +-\n drivers/clk/nuvoton/clk_npcm.c | 2 +-\n drivers/clk/nuvoton/clk_npcm.h | 2 +-\n drivers/clk/owl/clk_owl.c | 2 +-\n drivers/clk/qcom/clock-qcom.c | 2 +-\n drivers/clk/qcom/clock-sm8550.c | 2 +-\n drivers/clk/qcom/clock-sm8650.c | 2 +-\n drivers/clk/qcom/clock-x1e80100.c | 2 +-\n drivers/clk/renesas/clk-rcar-gen2.c | 2 +-\n drivers/clk/renesas/clk-rcar-gen3.c | 2 +-\n drivers/clk/renesas/compound-clock.c | 2 +-\n drivers/clk/renesas/r9a06g032-clocks.c | 2 +-\n drivers/clk/renesas/rcar-gen2-cpg.h | 2 +-\n drivers/clk/renesas/rcar-gen3-cpg.h | 2 +-\n drivers/clk/renesas/rzg2l-cpg.c | 2 +-\n drivers/clk/rockchip/clk_px30.c | 4 ++--\n drivers/clk/rockchip/clk_rk3036.c | 2 +-\n drivers/clk/rockchip/clk_rk3066.c | 2 +-\n drivers/clk/rockchip/clk_rk3128.c | 2 +-\n drivers/clk/rockchip/clk_rk3188.c | 2 +-\n drivers/clk/rockchip/clk_rk322x.c | 2 +-\n drivers/clk/rockchip/clk_rk3288.c | 2 +-\n drivers/clk/rockchip/clk_rk3308.c | 2 +-\n drivers/clk/rockchip/clk_rk3328.c | 2 +-\n drivers/clk/rockchip/clk_rk3368.c | 2 +-\n drivers/clk/rockchip/clk_rk3399.c | 4 ++--\n drivers/clk/rockchip/clk_rk3528.c | 2 +-\n drivers/clk/rockchip/clk_rk3568.c | 4 ++--\n drivers/clk/rockchip/clk_rk3576.c | 2 +-\n drivers/clk/rockchip/clk_rk3588.c | 4 ++--\n drivers/clk/rockchip/clk_rv1108.c | 2 +-\n drivers/clk/rockchip/clk_rv1126.c | 4 ++--\n drivers/clk/sifive/sifive-prci.c | 2 +-\n drivers/clk/sophgo/clk-cv1800b.c | 2 +-\n drivers/clk/sophgo/clk-ip.c | 18 +++++++++---------\n drivers/clk/sophgo/clk-ip.h | 18 +++++++++---------\n drivers/clk/sophgo/clk-pll.c | 4 ++--\n drivers/clk/sophgo/clk-pll.h | 4 ++--\n drivers/clk/starfive/clk-jh7110-pll.c | 2 +-\n drivers/clk/starfive/clk.h | 2 +-\n drivers/clk/stm32/clk-stm32-core.c | 20 ++++++++++----------\n drivers/clk/stm32/clk-stm32-core.h | 2 +-\n drivers/clk/stm32/clk-stm32f.c | 2 +-\n drivers/clk/stm32/clk-stm32h7.c | 2 +-\n drivers/clk/stm32/clk-stm32mp1.c | 2 +-\n drivers/clk/sunxi/clk_sun6i_rtc.c | 2 +-\n drivers/clk/sunxi/clk_sunxi.c | 2 +-\n drivers/clk/tegra/tegra-car-clk.c | 2 +-\n drivers/clk/tegra/tegra186-clk.c | 2 +-\n drivers/clk/thead/clk-th1520-ap.c | 6 +++---\n drivers/clk/ti/clk-am3-dpll-x2.c | 2 +-\n drivers/clk/ti/clk-am3-dpll.c | 2 +-\n drivers/clk/ti/clk-ctrl.c | 2 +-\n drivers/clk/ti/clk-divider.c | 2 +-\n drivers/clk/ti/clk-gate.c | 2 +-\n drivers/clk/ti/clk-k3-pll.c | 2 +-\n drivers/clk/ti/clk-k3.c | 4 ++--\n drivers/clk/ti/clk-mux.c | 2 +-\n drivers/clk/ti/clk-sci.c | 2 +-\n drivers/clk/uccf/clk-composite.c | 18 +++++++++---------\n drivers/clk/uccf/clk-divider.c | 2 +-\n drivers/clk/uccf/clk-fixed-factor.c | 2 +-\n drivers/clk/uccf/clk-gate.c | 2 +-\n drivers/clk/uccf/clk-mux.c | 2 +-\n drivers/clk/uccf/clk.c | 2 +-\n drivers/clk/uccf/clk_sandbox_uccf.c | 6 +++---\n drivers/clk/uniphier/clk-uniphier-core.c | 2 +-\n drivers/phy/cadence/phy-cadence-sierra.c | 2 +-\n drivers/phy/cadence/phy-cadence-torrent.c | 2 +-\n drivers/phy/phy-stm32-usbphyc.c | 2 +-\n drivers/phy/phy-ti-am654.c | 2 +-\n drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 2 +-\n drivers/phy/ti/phy-j721e-wiz.c | 6 +++---\n drivers/power/domain/imx8mp-hsiomix.c | 2 +-\n include/clk-uclass.h | 4 ++--\n include/clk/sunxi.h | 2 +-\n include/linux/clk-provider.h | 24 ++++++++++++------------\n 159 files changed, 282 insertions(+), 282 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c\nindex 71b3a9277b17..6d82fe603dd2 100644\n--- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c\n+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c\n@@ -245,9 +245,9 @@ static unsigned long peri_clk_get_rate(struct clk *c)\n \treturn c->rate;\n }\n \n /* Peripheral clock operations */\n-struct clk_ops peri_clk_ops = {\n+struct clk_ops_uboot peri_clk_ops = {\n \t.enable = peri_clk_enable,\n \t.set_rate = peri_clk_set_rate,\n \t.get_rate = peri_clk_get_rate,\n };\n@@ -324,9 +324,9 @@ static unsigned long ccu_clk_get_rate(struct clk *c)\n \treturn c->rate;\n }\n \n /* CCU clock operations */\n-struct clk_ops ccu_clk_ops = {\n+struct clk_ops_uboot ccu_clk_ops = {\n \t.enable = ccu_clk_enable,\n \t.get_rate = ccu_clk_get_rate,\n };\n \n@@ -384,9 +384,9 @@ static unsigned long bus_clk_get_rate(struct clk *c)\n \treturn c->rate;\n }\n \n /* Bus clock operations */\n-struct clk_ops bus_clk_ops = {\n+struct clk_ops_uboot bus_clk_ops = {\n \t.enable = bus_clk_enable,\n \t.get_rate = bus_clk_get_rate,\n };\n \n@@ -397,9 +397,9 @@ static int ref_clk_enable(struct clk *c, int enable)\n \treturn 0;\n }\n \n /* Reference clock operations */\n-struct clk_ops ref_clk_ops = {\n+struct clk_ops_uboot ref_clk_ops = {\n \t.enable = ref_clk_enable,\n };\n \n /*\ndiff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.h b/arch/arm/cpu/armv7/bcm281xx/clk-core.h\nindex f0fbff081d02..0a583bf495a4 100644\n--- a/arch/arm/cpu/armv7/bcm281xx/clk-core.h\n+++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.h\n@@ -34,9 +34,9 @@ struct clk_lookup {\n extern struct clk_lookup arch_clk_tbl[];\n extern unsigned int arch_clk_tbl_array_size;\n \n /**\n- * struct clk_ops - standard clock operations\n+ * struct clk_ops_uboot - standard clock operations\n * @enable: enable/disable clock, see clk_enable() and clk_disable()\n * @set_rate: set the clock rate, see clk_set_rate().\n * @get_rate: get the clock rate, see clk_get_rate().\n * @round_rate: round a given clock rate, see clk_round_rate().\n@@ -46,9 +46,9 @@ extern unsigned int arch_clk_tbl_array_size;\n * don't have to keep setting the same fiels again. We leave\n * enable in struct clk.\n *\n */\n-struct clk_ops {\n+struct clk_ops_uboot {\n \tint (*enable) (struct clk *c, int enable);\n \tint (*set_rate) (struct clk *c, unsigned long rate);\n \tunsigned long (*get_rate) (struct clk *c);\n \tunsigned long (*round_rate) (struct clk *c, unsigned long rate);\n@@ -64,9 +64,9 @@ struct clk {\n \t/* programmable divider. 0 means fixed ratio to parent clock */\n \tunsigned long div;\n \n \tstruct clk_src *src;\n-\tstruct clk_ops *ops;\n+\tstruct clk_ops_uboot *ops;\n \n \tunsigned long ccu_clk_mgr_base;\n \tint sel;\n };\n@@ -482,10 +482,10 @@ static inline struct ref_clock *to_ref_clk(struct clk *clock)\n {\n \treturn container_of(clock, struct ref_clock, clk);\n }\n \n-extern struct clk_ops peri_clk_ops;\n-extern struct clk_ops ccu_clk_ops;\n-extern struct clk_ops bus_clk_ops;\n-extern struct clk_ops ref_clk_ops;\n+extern struct clk_ops_uboot peri_clk_ops;\n+extern struct clk_ops_uboot ccu_clk_ops;\n+extern struct clk_ops_uboot bus_clk_ops;\n+extern struct clk_ops_uboot ref_clk_ops;\n \n extern int clk_get_and_enable(char *clkstr);\ndiff --git a/cmd/clk.c b/cmd/clk.c\nindex 2fc834e5549c..1210a84ca2aa 100644\n--- a/cmd/clk.c\n+++ b/cmd/clk.c\n@@ -57,9 +57,9 @@ static void show_clks(struct udevice *dev, int depth, int last_flag)\n \n static int soc_clk_dump(void)\n {\n \tstruct udevice *dev;\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \n \tprintf(\" Rate Usecnt Name\\n\");\n \tprintf(\"------------------------------------------\\n\");\n \ndiff --git a/drivers/clk/adi/clk-adi-pll.c b/drivers/clk/adi/clk-adi-pll.c\nindex 34818cb1af00..44fc8842e758 100644\n--- a/drivers/clk/adi/clk-adi-pll.c\n+++ b/drivers/clk/adi/clk-adi-pll.c\n@@ -48,9 +48,9 @@ static unsigned long sc5xx_cgu_pll_get_rate(struct clk *clk)\n \t\treturn parent_rate * m * 2;\n \treturn parent_rate * m;\n }\n \n-static const struct clk_ops clk_sc5xx_cgu_pll_ops = {\n+static const struct clk_ops_uboot clk_sc5xx_cgu_pll_ops = {\n \t.get_rate = sc5xx_cgu_pll_get_rate,\n };\n \n struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,\ndiff --git a/drivers/clk/adi/clk-shared.c b/drivers/clk/adi/clk-shared.c\nindex afd5f46c8456..5d0b7eb34655 100644\n--- a/drivers/clk/adi/clk-shared.c\n+++ b/drivers/clk/adi/clk-shared.c\n@@ -38,9 +38,9 @@ static int adi_disable(struct clk *clk)\n \t//Not yet implemented\n \treturn 0;\n }\n \n-const struct clk_ops adi_clk_ops = {\n+const struct clk_ops_uboot adi_clk_ops = {\n \t.set_rate = adi_set_rate,\n \t.get_rate = adi_get_rate,\n \t.enable = adi_enable,\n \t.disable = adi_disable,\ndiff --git a/drivers/clk/adi/clk.h b/drivers/clk/adi/clk.h\nindex acd4e384746c..01e600b76a30 100644\n--- a/drivers/clk/adi/clk.h\n+++ b/drivers/clk/adi/clk.h\n@@ -64,9 +64,9 @@\n #define CDU_MUX_SHIFT 1\n #define CDU_MUX_WIDTH 2\n #define CDU_EN_BIT 0\n \n-extern const struct clk_ops adi_clk_ops;\n+extern const struct clk_ops_uboot adi_clk_ops;\n \n struct clk *sc5xx_cgu_pll(const char *name, const char *parent_name,\n \t\t\t void __iomem *base, u8 shift, u8 width, u32 m_offset, bool half_m);\n \ndiff --git a/drivers/clk/airoha/clk-airoha.c b/drivers/clk/airoha/clk-airoha.c\nindex 49dbca821355..200324a4fffd 100644\n--- a/drivers/clk/airoha/clk-airoha.c\n+++ b/drivers/clk/airoha/clk-airoha.c\n@@ -496,9 +496,9 @@ apply:\n \n \treturn rate;\n }\n \n-const struct clk_ops airoha_clk_ops = {\n+const struct clk_ops_uboot airoha_clk_ops = {\n \t.enable = airoha_clk_enable,\n \t.disable = airoha_clk_disable,\n \t.get_rate = airoha_clk_get_rate,\n \t.set_rate = airoha_clk_set_rate,\ndiff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c\nindex fdbf834bb2f6..beb428dd548e 100644\n--- a/drivers/clk/altera/clk-agilex.c\n+++ b/drivers/clk/altera/clk-agilex.c\n@@ -786,9 +786,9 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops socfpga_clk_ops = {\n+static struct clk_ops_uboot socfpga_clk_ops = {\n \t.enable\t\t= socfpga_clk_enable,\n \t.disable\t= socfpga_clk_disable,\n \t.get_rate\t= socfpga_clk_get_rate,\n };\ndiff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c\nindex fb1e72ffc5cd..2278a4a77809 100644\n--- a/drivers/clk/altera/clk-agilex5.c\n+++ b/drivers/clk/altera/clk-agilex5.c\n@@ -735,9 +735,9 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops socfpga_clk_ops = {\n+static struct clk_ops_uboot socfpga_clk_ops = {\n \t.enable\t\t= socfpga_clk_enable,\n \t.get_rate\t= socfpga_clk_get_rate,\n };\n \ndiff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c\nindex 1840f73beeec..f1ee995670cb 100644\n--- a/drivers/clk/altera/clk-arria10.c\n+++ b/drivers/clk/altera/clk-arria10.c\n@@ -169,9 +169,9 @@ static ulong socfpga_a10_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static struct clk_ops socfpga_a10_clk_ops = {\n+static struct clk_ops_uboot socfpga_a10_clk_ops = {\n \t.enable\t\t= socfpga_a10_clk_enable,\n \t.disable\t= socfpga_a10_clk_disable,\n \t.get_rate\t= socfpga_a10_clk_get_rate,\n };\ndiff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c\nindex b75f52d203b2..372635bab569 100644\n--- a/drivers/clk/altera/clk-mem-n5x.c\n+++ b/drivers/clk/altera/clk-mem-n5x.c\n@@ -115,9 +115,9 @@ static int socfpga_mem_clk_of_to_plat(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops socfpga_mem_clk_ops = {\n+static struct clk_ops_uboot socfpga_mem_clk_ops = {\n \t.enable\t\t= socfpga_mem_clk_enable\n };\n \n static const struct udevice_id socfpga_mem_clk_match[] = {\ndiff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c\nindex 9e4e7a1d9087..a1c7b0b53d19 100644\n--- a/drivers/clk/altera/clk-n5x.c\n+++ b/drivers/clk/altera/clk-n5x.c\n@@ -466,9 +466,9 @@ static int socfpga_clk_of_to_plat(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops socfpga_clk_ops = {\n+static struct clk_ops_uboot socfpga_clk_ops = {\n \t.enable\t\t= socfpga_clk_enable,\n \t.get_rate\t= socfpga_clk_get_rate,\n };\n \ndiff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c\nindex a330dcda4dcb..4d30ecb87d99 100644\n--- a/drivers/clk/aspeed/clk_ast2500.c\n+++ b/drivers/clk/aspeed/clk_ast2500.c\n@@ -533,9 +533,9 @@ static int ast2500_clk_enable(struct clk *clk)\n \n \treturn 0;\n }\n \n-struct clk_ops ast2500_clk_ops = {\n+struct clk_ops_uboot ast2500_clk_ops = {\n \t.get_rate = ast2500_clk_get_rate,\n \t.set_rate = ast2500_clk_set_rate,\n \t.enable = ast2500_clk_enable,\n };\ndiff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c\nindex 535010b79414..b9bbe41a592f 100644\n--- a/drivers/clk/aspeed/clk_ast2600.c\n+++ b/drivers/clk/aspeed/clk_ast2600.c\n@@ -1160,9 +1160,9 @@ static void ast2600_clk_dump(struct udevice *dev)\n \treturn 0;\n }\n #endif\n \n-struct clk_ops ast2600_clk_ops = {\n+struct clk_ops_uboot ast2600_clk_ops = {\n \t.get_rate = ast2600_clk_get_rate,\n \t.set_rate = ast2600_clk_set_rate,\n \t.enable = ast2600_clk_enable,\n #if IS_ENABLED(CONFIG_CMD_CLK)\ndiff --git a/drivers/clk/at91/clk-generic.c b/drivers/clk/at91/clk-generic.c\nindex c410cd2b5052..0424fb1b6f4e 100644\n--- a/drivers/clk/at91/clk-generic.c\n+++ b/drivers/clk/at91/clk-generic.c\n@@ -128,9 +128,9 @@ static ulong clk_gck_get_rate(struct clk *clk)\n \n \treturn parent_rate / (div + 1);\n }\n \n-static const struct clk_ops gck_ops = {\n+static const struct clk_ops_uboot gck_ops = {\n \t.enable = clk_gck_enable,\n \t.disable = clk_gck_disable,\n \t.set_parent = clk_gck_set_parent,\n \t.set_rate = clk_gck_set_rate,\ndiff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c\nindex 0542b0667883..5b802cdbdaba 100644\n--- a/drivers/clk/at91/clk-main.c\n+++ b/drivers/clk/at91/clk-main.c\n@@ -96,9 +96,9 @@ static int main_rc_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops main_rc_clk_ops = {\n+static const struct clk_ops_uboot main_rc_clk_ops = {\n \t.enable = main_rc_enable,\n \t.disable = main_rc_disable,\n \t.get_rate = clk_generic_get_rate,\n };\n@@ -182,9 +182,9 @@ static int clk_main_osc_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops main_osc_clk_ops = {\n+static const struct clk_ops_uboot main_osc_clk_ops = {\n \t.enable = clk_main_osc_enable,\n \t.disable = clk_main_osc_disable,\n \t.get_rate = clk_generic_get_rate,\n };\n@@ -250,9 +250,9 @@ static int clk_rm9200_main_enable(struct clk *clk)\n \n \treturn clk_main_probe_frequency(main->reg);\n }\n \n-static const struct clk_ops rm9200_main_clk_ops = {\n+static const struct clk_ops_uboot rm9200_main_clk_ops = {\n \t.enable = clk_rm9200_main_enable,\n };\n \n struct clk *at91_clk_rm9200_main(void __iomem *reg, const char *name,\n@@ -337,9 +337,9 @@ static int clk_sam9x5_main_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-static const struct clk_ops sam9x5_main_clk_ops = {\n+static const struct clk_ops_uboot sam9x5_main_clk_ops = {\n \t.enable = clk_sam9x5_main_enable,\n \t.set_parent = clk_sam9x5_main_set_parent,\n \t.get_rate = clk_generic_get_rate,\n };\ndiff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c\nindex 530205b8c6be..53652efc5740 100644\n--- a/drivers/clk/at91/clk-master.c\n+++ b/drivers/clk/at91/clk-master.c\n@@ -99,9 +99,9 @@ static ulong clk_master_pres_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_CLOSEST_ULL(rate, pres);\n }\n \n-static const struct clk_ops master_pres_ops = {\n+static const struct clk_ops_uboot master_pres_ops = {\n \t.enable = clk_master_enable,\n \t.get_rate = clk_master_pres_get_rate,\n };\n \n@@ -175,9 +175,9 @@ static ulong clk_master_div_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static const struct clk_ops master_div_ops = {\n+static const struct clk_ops_uboot master_div_ops = {\n \t.enable = clk_master_enable,\n \t.get_rate = clk_master_div_get_rate,\n };\n \n@@ -319,9 +319,9 @@ static ulong clk_sama7g5_master_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_CLOSEST(parent_rate, div);\n }\n \n-static const struct clk_ops sama7g5_master_ops = {\n+static const struct clk_ops_uboot sama7g5_master_ops = {\n \t.enable = clk_sama7g5_master_enable,\n \t.disable = clk_sama7g5_master_disable,\n \t.set_rate = clk_sama7g5_master_set_rate,\n \t.get_rate = clk_sama7g5_master_get_rate,\ndiff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c\nindex 08d7e7dddc9e..8f0c7524e4cc 100644\n--- a/drivers/clk/at91/clk-peripheral.c\n+++ b/drivers/clk/at91/clk-peripheral.c\n@@ -76,9 +76,9 @@ static int clk_peripheral_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops peripheral_ops = {\n+static const struct clk_ops_uboot peripheral_ops = {\n \t.enable = clk_peripheral_enable,\n \t.disable = clk_peripheral_disable,\n \t.get_rate = clk_generic_get_rate,\n };\n@@ -203,9 +203,9 @@ static ulong clk_sam9x5_peripheral_set_rate(struct clk *clk, ulong rate)\n \n \treturn parent_rate >> shift;\n }\n \n-static const struct clk_ops sam9x5_peripheral_ops = {\n+static const struct clk_ops_uboot sam9x5_peripheral_ops = {\n \t.enable = clk_sam9x5_peripheral_enable,\n \t.disable = clk_sam9x5_peripheral_disable,\n \t.get_rate = clk_sam9x5_peripheral_get_rate,\n \t.set_rate = clk_sam9x5_peripheral_set_rate,\ndiff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c\nindex d0b14656c4d6..9cf8e38af08c 100644\n--- a/drivers/clk/at91/clk-programmable.c\n+++ b/drivers/clk/at91/clk-programmable.c\n@@ -119,9 +119,9 @@ static ulong clk_programmable_set_rate(struct clk *clk, ulong rate)\n \n \treturn parent_rate >> shift;\n }\n \n-static const struct clk_ops programmable_ops = {\n+static const struct clk_ops_uboot programmable_ops = {\n \t.get_rate = clk_programmable_get_rate,\n \t.set_parent = clk_programmable_set_parent,\n \t.set_rate = clk_programmable_set_rate,\n };\ndiff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c\nindex 66f014727390..b896be5fe238 100644\n--- a/drivers/clk/at91/clk-sam9x60-pll.c\n+++ b/drivers/clk/at91/clk-sam9x60-pll.c\n@@ -244,9 +244,9 @@ static int sam9x60_frac_pll_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops sam9x60_frac_pll_ops = {\n+static const struct clk_ops_uboot sam9x60_frac_pll_ops = {\n \t.enable = sam9x60_frac_pll_enable,\n \t.disable = sam9x60_frac_pll_disable,\n \t.set_rate = sam9x60_frac_pll_set_rate,\n \t.get_rate = sam9x60_frac_pll_get_rate,\n@@ -371,16 +371,16 @@ static ulong sam9x60_fixed_div_pll_get_rate(struct clk *clk)\n \n \treturn parent_rate >> 1;\n }\n \n-static const struct clk_ops sam9x60_div_pll_ops = {\n+static const struct clk_ops_uboot sam9x60_div_pll_ops = {\n \t.enable = sam9x60_div_pll_enable,\n \t.disable = sam9x60_div_pll_disable,\n \t.set_rate = sam9x60_div_pll_set_rate,\n \t.get_rate = sam9x60_div_pll_get_rate,\n };\n \n-static const struct clk_ops sam9x60_fixed_div_pll_ops = {\n+static const struct clk_ops_uboot sam9x60_fixed_div_pll_ops = {\n \t.enable = sam9x60_div_pll_enable,\n \t.disable = sam9x60_div_pll_disable,\n \t.get_rate = sam9x60_fixed_div_pll_get_rate,\n };\ndiff --git a/drivers/clk/at91/clk-sam9x60-usb.c b/drivers/clk/at91/clk-sam9x60-usb.c\nindex 798fa9eb3cca..92bfd45f5353 100644\n--- a/drivers/clk/at91/clk-sam9x60-usb.c\n+++ b/drivers/clk/at91/clk-sam9x60-usb.c\n@@ -88,9 +88,9 @@ static ulong sam9x60_usb_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn parent_rate / usbdiv;\n }\n \n-static const struct clk_ops sam9x60_usb_ops = {\n+static const struct clk_ops_uboot sam9x60_usb_ops = {\n \t.set_parent = sam9x60_usb_clk_set_parent,\n \t.set_rate = sam9x60_usb_clk_set_rate,\n \t.get_rate = sam9x60_usb_clk_get_rate,\n };\ndiff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c\nindex 3545b0b24bd7..faa3ddba5d57 100644\n--- a/drivers/clk/at91/clk-system.c\n+++ b/drivers/clk/at91/clk-system.c\n@@ -68,9 +68,9 @@ static int clk_system_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops system_ops = {\n+static const struct clk_ops_uboot system_ops = {\n \t.enable = clk_system_enable,\n \t.disable = clk_system_disable,\n \t.get_rate = clk_generic_get_rate,\n };\ndiff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c\nindex 84784ae41ce8..db3d7d69f2cf 100644\n--- a/drivers/clk/at91/clk-utmi.c\n+++ b/drivers/clk/at91/clk-utmi.c\n@@ -112,9 +112,9 @@ static ulong clk_utmi_get_rate(struct clk *clk)\n \t/* UTMI clk rate is fixed. */\n \treturn UTMI_RATE;\n }\n \n-static const struct clk_ops utmi_ops = {\n+static const struct clk_ops_uboot utmi_ops = {\n \t.enable = clk_utmi_enable,\n \t.disable = clk_utmi_disable,\n \t.get_rate = clk_utmi_get_rate,\n };\n@@ -192,9 +192,9 @@ static int clk_utmi_sama7g5_enable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops sama7g5_utmi_ops = {\n+static const struct clk_ops_uboot sama7g5_utmi_ops = {\n \t.enable = clk_utmi_sama7g5_enable,\n \t.get_rate = clk_utmi_get_rate,\n };\n \ndiff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c\nindex 1d738f160b6e..5099fe3b8c62 100644\n--- a/drivers/clk/at91/compat.c\n+++ b/drivers/clk/at91/compat.c\n@@ -152,9 +152,9 @@ static ulong at91_slow_clk_get_rate(struct clk *clk)\n {\n \treturn CFG_SYS_AT91_SLOW_CLOCK;\n }\n \n-static struct clk_ops at91_slow_clk_ops = {\n+static struct clk_ops_uboot at91_slow_clk_ops = {\n \t.enable = at91_slow_clk_enable,\n \t.get_rate = at91_slow_clk_get_rate,\n };\n \n@@ -175,9 +175,9 @@ static ulong at91_master_clk_get_rate(struct clk *clk)\n {\n \treturn gd->arch.mck_rate_hz;\n }\n \n-static struct clk_ops at91_master_clk_ops = {\n+static struct clk_ops_uboot at91_master_clk_ops = {\n \t.get_rate = at91_master_clk_get_rate,\n };\n \n static const struct udevice_id at91_master_clk_match[] = {\n@@ -209,9 +209,9 @@ static ulong main_osc_clk_get_rate(struct clk *clk)\n {\n \treturn gd->arch.main_clk_rate_hz;\n }\n \n-static struct clk_ops main_osc_clk_ops = {\n+static struct clk_ops_uboot main_osc_clk_ops = {\n \t.enable = main_osc_clk_enable,\n \t.get_rate = main_osc_clk_get_rate,\n };\n \n@@ -250,9 +250,9 @@ static ulong plla_clk_get_rate(struct clk *clk)\n {\n \treturn gd->arch.plla_rate_hz;\n }\n \n-static struct clk_ops plla_clk_ops = {\n+static struct clk_ops_uboot plla_clk_ops = {\n \t.enable = plla_clk_enable,\n \t.get_rate = plla_clk_get_rate,\n };\n \n@@ -323,9 +323,9 @@ static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static struct clk_ops at91_plladiv_clk_ops = {\n+static struct clk_ops_uboot at91_plladiv_clk_ops = {\n \t.enable = at91_plladiv_clk_enable,\n \t.get_rate = at91_plladiv_clk_get_rate,\n \t.set_rate = at91_plladiv_clk_set_rate,\n };\n@@ -430,9 +430,9 @@ static int system_clk_enable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops system_clk_ops = {\n+static struct clk_ops_uboot system_clk_ops = {\n \t.of_xlate = at91_clk_of_xlate,\n \t.get_rate = system_clk_get_rate,\n \t.set_rate = system_clk_set_rate,\n \t.enable = system_clk_enable,\n@@ -526,9 +526,9 @@ static ulong periph_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(&clk_dev);\n }\n \n-static struct clk_ops periph_clk_ops = {\n+static struct clk_ops_uboot periph_clk_ops = {\n \t.of_xlate = at91_clk_of_xlate,\n \t.enable = periph_clk_enable,\n \t.get_rate = periph_get_rate,\n };\n@@ -632,9 +632,9 @@ static ulong utmi_clk_get_rate(struct clk *clk)\n \t/* UTMI clk rate is fixed. */\n \treturn UTMI_RATE;\n }\n \n-static struct clk_ops utmi_clk_ops = {\n+static struct clk_ops_uboot utmi_clk_ops = {\n \t.enable = utmi_clk_enable,\n \t.get_rate = utmi_clk_get_rate,\n };\n \n@@ -693,9 +693,9 @@ static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static struct clk_ops sama5d4_h32mx_clk_ops = {\n+static struct clk_ops_uboot sama5d4_h32mx_clk_ops = {\n \t.get_rate = sama5d4_h32mx_clk_get_rate,\n };\n \n static int sama5d4_h32mx_clk_probe(struct udevice *dev)\n@@ -841,9 +841,9 @@ static ulong generic_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static struct clk_ops generic_clk_ops = {\n+static struct clk_ops_uboot generic_clk_ops = {\n \t.of_xlate = at91_clk_of_xlate,\n \t.get_rate = generic_clk_get_rate,\n \t.set_rate = generic_clk_set_rate,\n };\n@@ -966,9 +966,9 @@ static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static struct clk_ops at91_usb_clk_ops = {\n+static struct clk_ops_uboot at91_usb_clk_ops = {\n \t.get_rate = at91_usb_clk_get_rate,\n \t.set_rate = at91_usb_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c\nindex aa4bc8fa47ad..2a7de0bf6ff1 100644\n--- a/drivers/clk/at91/pmc.c\n+++ b/drivers/clk/at91/pmc.c\n@@ -20,9 +20,9 @@ static int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)\n \n \treturn 0;\n }\n \n-const struct clk_ops at91_clk_ops = {\n+const struct clk_ops_uboot at91_clk_ops = {\n \t.of_xlate\t= at91_clk_of_xlate,\n \t.set_rate\t= ccf_clk_set_rate,\n \t.get_rate\t= ccf_clk_get_rate,\n \t.enable\t\t= ccf_clk_enable,\ndiff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h\nindex f38868d16655..638c9b769ceb 100644\n--- a/drivers/clk/at91/pmc.h\n+++ b/drivers/clk/at91/pmc.h\n@@ -97,9 +97,9 @@ struct pmc_clk_setup {\n extern const struct clk_programmable_layout at91rm9200_programmable_layout;\n extern const struct clk_programmable_layout at91sam9g45_programmable_layout;\n extern const struct clk_programmable_layout at91sam9x5_programmable_layout;\n \n-extern const struct clk_ops at91_clk_ops;\n+extern const struct clk_ops_uboot at91_clk_ops;\n \n struct clk *at91_clk_main_rc(void __iomem *reg, const char *name,\n \t\t\tconst char *parent_name);\n struct clk *at91_clk_main_osc(void __iomem *reg, const char *name,\ndiff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c\nindex 3fde8ea71382..9dba31562c6a 100644\n--- a/drivers/clk/at91/sckc.c\n+++ b/drivers/clk/at91/sckc.c\n@@ -41,9 +41,9 @@ static int sam9x60_sckc_of_xlate(struct clk *clk,\n \n \treturn 0;\n }\n \n-static const struct clk_ops sam9x60_sckc_ops = {\n+static const struct clk_ops_uboot sam9x60_sckc_ops = {\n \t.of_xlate = sam9x60_sckc_of_xlate,\n \t.get_rate = clk_generic_get_rate,\n };\n \n@@ -63,9 +63,9 @@ static int sam9x60_td_slck_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-static const struct clk_ops sam9x60_td_slck_ops = {\n+static const struct clk_ops_uboot sam9x60_td_slck_ops = {\n \t.get_rate = clk_generic_get_rate,\n \t.set_parent = sam9x60_td_slck_set_parent,\n };\n \ndiff --git a/drivers/clk/clk-cdce9xx.c b/drivers/clk/clk-cdce9xx.c\nindex 996cc30683ea..9689283cec48 100644\n--- a/drivers/clk/clk-cdce9xx.c\n+++ b/drivers/clk/clk-cdce9xx.c\n@@ -231,9 +231,9 @@ static const struct udevice_id cdce9xx_clk_of_match[] = {\n \t{ .compatible = \"ti,cdce949\", .data = (u32)&cdce949_chip_info },\n \t{ /* sentinel */ },\n };\n \n-static const struct clk_ops cdce9xx_clk_ops = {\n+static const struct clk_ops_uboot cdce9xx_clk_ops = {\n \t.request = cdce9xx_clk_request,\n \t.get_rate = cdce9xx_clk_get_rate,\n \t.set_rate = cdce9xx_clk_set_rate,\n };\ndiff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c\nindex 4ed143065754..6c2bc91c6a77 100644\n--- a/drivers/clk/clk-gpio.c\n+++ b/drivers/clk/clk-gpio.c\n@@ -41,9 +41,9 @@ static ulong clk_gpio_get_rate(struct clk *clk)\n \n \treturn clk_get_rate(priv->clk);\n }\n \n-const struct clk_ops clk_gpio_ops = {\n+const struct clk_ops_uboot clk_gpio_ops = {\n \t.enable\t\t= clk_gpio_enable,\n \t.disable\t= clk_gpio_disable,\n \t.get_rate\t= clk_gpio_get_rate,\n };\ndiff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c\nindex 53655059279e..4ff2b27205fd 100644\n--- a/drivers/clk/clk-hsdk-cgu.c\n+++ b/drivers/clk/clk-hsdk-cgu.c\n@@ -733,9 +733,9 @@ static int hsdk_cgu_disable(struct clk *sclk)\n \n \treturn -EINVAL;\n }\n \n-static const struct clk_ops hsdk_cgu_ops = {\n+static const struct clk_ops_uboot hsdk_cgu_ops = {\n \t.set_rate = hsdk_cgu_set_rate,\n \t.get_rate = hsdk_cgu_get_rate,\n \t.disable = hsdk_cgu_disable,\n };\ndiff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c\nindex 117266ac7789..ea77a4c720ae 100644\n--- a/drivers/clk/clk-stub.c\n+++ b/drivers/clk/clk-stub.c\n@@ -40,9 +40,9 @@ static int stub_clk_nop(struct clk *clk)\n {\n \treturn 0;\n }\n \n-static struct clk_ops stub_clk_ops = {\n+static struct clk_ops_uboot stub_clk_ops = {\n \t.set_rate = stub_clk_set_rate,\n \t.get_rate = stub_clk_get_rate,\n \t.enable = stub_clk_nop,\n \t.disable = stub_clk_nop,\ndiff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c\nindex c33f415917e9..8a7033386a74 100644\n--- a/drivers/clk/clk-uclass.c\n+++ b/drivers/clk/clk-uclass.c\n@@ -23,11 +23,11 @@\n #include <linux/bug.h>\n #include <linux/clk-provider.h>\n #include <linux/err.h>\n \n-static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)\n+static inline const struct clk_ops_uboot *clk_dev_ops(struct udevice *dev)\n {\n-\treturn (const struct clk_ops *)dev->driver->ops;\n+\treturn (const struct clk_ops_uboot *)dev->driver->ops;\n }\n \n struct clk *dev_get_clk_ptr(struct udevice *dev)\n {\n@@ -80,9 +80,9 @@ static int clk_get_by_index_tail(int ret, ofnode node,\n \t\t\t\t const char *list_name, int index,\n \t\t\t\t struct clk *clk)\n {\n \tstruct udevice *dev_clk;\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \n \tassert(clk);\n \tclk->dev = NULL;\n \tif (ret)\n@@ -465,9 +465,9 @@ int clk_release_all(struct clk *clk, unsigned int count)\n }\n \n int clk_request(struct udevice *dev, struct clk *clk)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \n \tdebug(\"%s(dev=%s, clk=%p)\\n\", __func__, dev_read_name(dev), clk);\n \tif (!clk)\n \t\treturn 0;\n@@ -482,9 +482,9 @@ int clk_request(struct udevice *dev, struct clk *clk)\n }\n \n ulong clk_get_rate(struct clk *clk)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \n \tdebug(\"%s(clk=%p)\\n\", __func__, clk);\n \tif (!clk_valid(clk))\n \t\treturn 0;\n@@ -516,9 +516,9 @@ struct clk *clk_get_parent(struct clk *clk)\n }\n \n ulong clk_get_parent_rate(struct clk *clk)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *pclk;\n \n \tdebug(\"%s(clk=%p)\\n\", __func__, clk);\n \tif (!clk_valid(clk))\n@@ -540,9 +540,9 @@ ulong clk_get_parent_rate(struct clk *clk)\n }\n \n ulong clk_round_rate(struct clk *clk, ulong rate)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \n \tdebug(\"%s(clk=%p, rate=%lu)\\n\", __func__, clk, rate);\n \tif (!clk_valid(clk))\n \t\treturn 0;\n@@ -587,9 +587,9 @@ static void clk_clean_rate_cache(struct clk *clk)\n }\n \n ulong clk_set_rate(struct clk *clk, ulong rate)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *clkp;\n \n \tdebug(\"%s(clk=%p, rate=%lu)\\n\", __func__, clk, rate);\n \tif (!clk_valid(clk))\n@@ -620,9 +620,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate)\n }\n \n int clk_set_parent(struct clk *clk, struct clk *parent)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tint ret;\n \n \tdebug(\"%s(clk=%p, parent=%p)\\n\", __func__, clk, parent);\n \tif (!clk_valid(clk))\n@@ -658,9 +658,9 @@ int clk_set_parent(struct clk *clk, struct clk *parent)\n }\n \n int clk_enable(struct clk *clk)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *clkp = NULL;\n \tint ret;\n \n \tdebug(\"%s(clk=%p name=%s)\\n\", __func__, clk, clk ? clk->dev->name : \"NULL\");\n@@ -719,9 +719,9 @@ int clk_enable_bulk(struct clk_bulk *bulk)\n }\n \n int clk_disable(struct clk *clk)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *clkp = NULL;\n \tint ret;\n \n \tdebug(\"%s(clk=%p name=%s)\\n\", __func__, clk, clk ? clk->dev->name : \"NULL\");\ndiff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c\nindex 4a3f50c638b1..18c5ae43789a 100644\n--- a/drivers/clk/clk-xlnx-clock-wizard.c\n+++ b/drivers/clk/clk-xlnx-clock-wizard.c\n@@ -104,9 +104,9 @@ static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static struct clk_ops clk_wzrd_ops = {\n+static struct clk_ops_uboot clk_wzrd_ops = {\n \t.enable = clk_wzrd_enable,\n \t.set_rate = clk_wzrd_set_rate,\n };\n \ndiff --git a/drivers/clk/clk_bcm6345.c b/drivers/clk/clk_bcm6345.c\nindex 0b41872b7192..ae72957bbda7 100644\n--- a/drivers/clk/clk_bcm6345.c\n+++ b/drivers/clk/clk_bcm6345.c\n@@ -41,9 +41,9 @@ static int bcm6345_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops bcm6345_clk_ops = {\n+static struct clk_ops_uboot bcm6345_clk_ops = {\n \t.disable = bcm6345_clk_disable,\n \t.enable = bcm6345_clk_enable,\n };\n \ndiff --git a/drivers/clk/clk_boston.c b/drivers/clk/clk_boston.c\nindex 71e030f463e1..e7b346ea18e0 100644\n--- a/drivers/clk/clk_boston.c\n+++ b/drivers/clk/clk_boston.c\n@@ -53,9 +53,9 @@ static ulong clk_boston_get_rate(struct clk *clk)\n \n \treturn (in_rate * mul * 1000000) / div;\n }\n \n-const struct clk_ops clk_boston_ops = {\n+const struct clk_ops_uboot clk_boston_ops = {\n \t.get_rate = clk_boston_get_rate,\n };\n \n static int clk_boston_probe(struct udevice *dev)\ndiff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c\nindex 1d740cf49f62..536639912f1f 100644\n--- a/drivers/clk/clk_fixed_factor.c\n+++ b/drivers/clk/clk_fixed_factor.c\n@@ -35,9 +35,9 @@ static ulong clk_fixed_factor_get_rate(struct clk *clk)\n \n \treturn rate * ff->mult;\n }\n \n-const struct clk_ops clk_fixed_factor_ops = {\n+const struct clk_ops_uboot clk_fixed_factor_ops = {\n \t.get_rate = clk_fixed_factor_get_rate,\n };\n \n static int clk_fixed_factor_of_to_plat(struct udevice *dev)\ndiff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c\nindex 681bd3db20ed..ee10cdc21613 100644\n--- a/drivers/clk/clk_fixed_rate.c\n+++ b/drivers/clk/clk_fixed_rate.c\n@@ -24,9 +24,9 @@ static int dummy_enable(struct clk *clk)\n {\n \treturn 0;\n }\n \n-const struct clk_ops clk_fixed_rate_ops = {\n+const struct clk_ops_uboot clk_fixed_rate_ops = {\n \t.get_rate = clk_fixed_rate_get_rate,\n \t.enable = dummy_enable,\n \t.disable = dummy_enable,\n };\n@@ -52,9 +52,9 @@ static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)\n {\n \treturn container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;\n }\n \n-const struct clk_ops clk_fixed_rate_raw_ops = {\n+const struct clk_ops_uboot clk_fixed_rate_raw_ops = {\n \t.get_rate = clk_fixed_rate_raw_get_rate,\n };\n \n static int clk_fixed_rate_of_to_plat(struct udevice *dev)\ndiff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c\nindex d1a6cde8f0f8..329fc5bffd18 100644\n--- a/drivers/clk/clk_k210.c\n+++ b/drivers/clk/clk_k210.c\n@@ -1289,9 +1289,9 @@ static void k210_clk_dump(struct udevice *dev)\n \tshow_clks(priv, K210_CLK_IN0, 1);\n }\n #endif\n \n-static const struct clk_ops k210_clk_ops = {\n+static const struct clk_ops_uboot k210_clk_ops = {\n \t.request = k210_clk_request,\n \t.set_rate = k210_clk_set_rate,\n \t.get_rate = k210_clk_get_rate,\n \t.set_parent = k210_clk_set_parent,\ndiff --git a/drivers/clk/clk_octeon.c b/drivers/clk/clk_octeon.c\nindex fa50265184f0..b2e6221b5bc7 100644\n--- a/drivers/clk/clk_octeon.c\n+++ b/drivers/clk/clk_octeon.c\n@@ -38,9 +38,9 @@ static ulong octeon_clk_get_rate(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops octeon_clk_ops = {\n+static struct clk_ops_uboot octeon_clk_ops = {\n \t.enable = octeon_clk_enable,\n \t.get_rate = octeon_clk_get_rate,\n };\n \ndiff --git a/drivers/clk/clk_pic32.c b/drivers/clk/clk_pic32.c\nindex 885aa8345165..0b8e2f7ad8ec 100644\n--- a/drivers/clk/clk_pic32.c\n+++ b/drivers/clk/clk_pic32.c\n@@ -417,9 +417,9 @@ static void pic32_dump(struct udevice *dev)\n \t}\n }\n #endif\n \n-static struct clk_ops pic32_pic32_clk_ops = {\n+static struct clk_ops_uboot pic32_pic32_clk_ops = {\n \t.set_rate = pic32_set_rate,\n \t.get_rate = pic32_get_rate,\n #if IS_ENABLED(CONFIG_CMD_CLK)\n \t.dump = pic32_dump,\ndiff --git a/drivers/clk/clk_sandbox.c b/drivers/clk/clk_sandbox.c\nindex c8c5a88c52d9..dceba88852ab 100644\n--- a/drivers/clk/clk_sandbox.c\n+++ b/drivers/clk/clk_sandbox.c\n@@ -105,9 +105,9 @@ static int sandbox_clk_request(struct clk *clk)\n \tpriv->requested[id] = true;\n \treturn 0;\n }\n \n-static struct clk_ops sandbox_clk_ops = {\n+static struct clk_ops_uboot sandbox_clk_ops = {\n \t.round_rate\t= sandbox_clk_round_rate,\n \t.get_rate\t= sandbox_clk_get_rate,\n \t.set_rate\t= sandbox_clk_set_rate,\n \t.enable\t\t= sandbox_clk_enable,\ndiff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c\nindex ee237ed6337c..16374560f2b7 100644\n--- a/drivers/clk/clk_scmi.c\n+++ b/drivers/clk/clk_scmi.c\n@@ -419,9 +419,9 @@ static int scmi_clk_set_parent(struct clk *clk, struct clk *parent)\n \t\t\"%s: SCMI CLOCK: the clock's parent cannot be changed by the agent.\\n\", __func__);\n \treturn 0;\n }\n \n-static const struct clk_ops scmi_clk_ops = {\n+static const struct clk_ops_uboot scmi_clk_ops = {\n \t.enable = scmi_clk_enable,\n \t.disable = scmi_clk_disable,\n \t.get_rate = scmi_clk_get_rate,\n \t.set_rate = scmi_clk_set_rate,\ndiff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c\nindex 19a787eaf0c5..35f7ded0137b 100644\n--- a/drivers/clk/clk_versaclock.c\n+++ b/drivers/clk/clk_versaclock.c\n@@ -276,9 +276,9 @@ static int vc5_mux_set_parent(struct clk *hw, unsigned char index)\n \n \treturn vc5_update_bits(vc5->i2c, VC5_PRIM_SRC_SHDN, mask, src);\n }\n \n-static const struct clk_ops vc5_mux_ops = {\n+static const struct clk_ops_uboot vc5_mux_ops = {\n \t.get_rate\t= vc5_mux_get_rate,\n };\n \n static unsigned long vc5_pfd_round_rate(struct clk *hw, unsigned long rate)\n@@ -357,9 +357,9 @@ static unsigned long vc5_pfd_set_rate(struct clk *hw, unsigned long rate)\n \n \treturn 0;\n }\n \n-static const struct clk_ops vc5_pfd_ops = {\n+static const struct clk_ops_uboot vc5_pfd_ops = {\n \t.round_rate\t= vc5_pfd_round_rate,\n \t.get_rate\t= vc5_pfd_recalc_rate,\n \t.set_rate\t= vc5_pfd_set_rate,\n };\n@@ -428,9 +428,9 @@ static unsigned long vc5_pll_set_rate(struct clk *hw, unsigned long rate)\n \n \treturn dm_i2c_write(vc5->i2c, VC5_FEEDBACK_INT_DIV, fb, 5);\n }\n \n-static const struct clk_ops vc5_pll_ops = {\n+static const struct clk_ops_uboot vc5_pll_ops = {\n \t.round_rate\t= vc5_pll_round_rate,\n \t.get_rate\t= vc5_pll_recalc_rate,\n \t.set_rate\t= vc5_pll_set_rate,\n };\n@@ -529,9 +529,9 @@ static unsigned long vc5_fod_set_rate(struct clk *hw, unsigned long rate)\n \n \treturn 0;\n }\n \n-static const struct clk_ops vc5_fod_ops = {\n+static const struct clk_ops_uboot vc5_fod_ops = {\n \t.round_rate\t= vc5_fod_round_rate,\n \t.get_rate\t= vc5_fod_recalc_rate,\n \t.set_rate\t= vc5_fod_set_rate,\n };\n@@ -635,22 +635,22 @@ static unsigned long vc5_clk_out_get_rate(struct clk *hw)\n {\n \treturn clk_get_parent_rate(hw);\n }\n \n-static const struct clk_ops vc5_clk_out_ops = {\n+static const struct clk_ops_uboot vc5_clk_out_ops = {\n \t.enable\t= vc5_clk_out_prepare,\n \t.disable\t= vc5_clk_out_unprepare,\n \t.set_rate\t= vc5_clk_out_set_rate,\n \t.get_rate\t= vc5_clk_out_get_rate,\n };\n \n-static const struct clk_ops vc5_clk_out_sel_ops = {\n+static const struct clk_ops_uboot vc5_clk_out_sel_ops = {\n \t.enable\t= vc5_clk_out_prepare,\n \t.disable\t= vc5_clk_out_unprepare,\n \t.get_rate\t= vc5_clk_out_get_rate,\n };\n \n-static const struct clk_ops vc5_clk_ops = {\n+static const struct clk_ops_uboot vc5_clk_ops = {\n \t.enable\t= vc5_clk_out_prepare,\n \t.disable\t= vc5_clk_out_unprepare,\n \t.set_rate\t= vc5_clk_out_set_rate,\n \t.get_rate\t= vc5_clk_out_get_rate,\ndiff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c\nindex 78a2410ca21c..14dadf859a1f 100644\n--- a/drivers/clk/clk_versal.c\n+++ b/drivers/clk/clk_versal.c\n@@ -801,9 +801,9 @@ static int versal_clk_enable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops versal_clk_ops = {\n+static struct clk_ops_uboot versal_clk_ops = {\n \t.set_rate = versal_clk_set_rate,\n \t.get_rate = versal_clk_get_rate,\n \t.enable = versal_clk_enable,\n #if IS_ENABLED(CONFIG_CMD_CLK)\ndiff --git a/drivers/clk/clk_vexpress_osc.c b/drivers/clk/clk_vexpress_osc.c\nindex 85ac92c908a7..a6f0ba595a23 100644\n--- a/drivers/clk/clk_vexpress_osc.c\n+++ b/drivers/clk/clk_vexpress_osc.c\n@@ -61,9 +61,9 @@ static ulong vexpress_osc_clk_set_rate(struct clk *clk, ulong rate)\n \treturn rate;\n }\n #endif\n \n-static struct clk_ops vexpress_osc_clk_ops = {\n+static struct clk_ops_uboot vexpress_osc_clk_ops = {\n \t.get_rate = vexpress_osc_clk_get_rate,\n #ifndef CONFIG_XPL_BUILD\n \t.set_rate = vexpress_osc_clk_set_rate,\n #endif\ndiff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c\nindex a8505f62bbad..229972fb505d 100644\n--- a/drivers/clk/clk_zynq.c\n+++ b/drivers/clk/clk_zynq.c\n@@ -499,9 +499,9 @@ static void zynq_clk_dump(struct udevice *dev)\n \t}\n }\n #endif\n \n-static struct clk_ops zynq_clk_ops = {\n+static struct clk_ops_uboot zynq_clk_ops = {\n \t.get_rate = zynq_clk_get_rate,\n #ifndef CONFIG_XPL_BUILD\n \t.set_rate = zynq_clk_set_rate,\n #endif\ndiff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c\nindex 765cae92241d..1f23b06553bf 100644\n--- a/drivers/clk/clk_zynqmp.c\n+++ b/drivers/clk/clk_zynqmp.c\n@@ -883,9 +883,9 @@ static int zynqmp_clk_enable(struct clk *clk)\n \n \treturn ret;\n }\n \n-static const struct clk_ops zynqmp_clk_ops = {\n+static const struct clk_ops_uboot zynqmp_clk_ops = {\n \t.set_rate = zynqmp_clk_set_rate,\n \t.get_rate = zynqmp_clk_get_rate,\n \t.enable = zynqmp_clk_enable,\n #if IS_ENABLED(CONFIG_CMD_CLK)\ndiff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c\nindex 7de4e688f036..8c8d2ce0d069 100644\n--- a/drivers/clk/exynos/clk-exynos7420.c\n+++ b/drivers/clk/exynos/clk-exynos7420.c\n@@ -103,9 +103,9 @@ static ulong exynos7420_topc_get_rate(struct clk *clk)\n \t\treturn 0;\n \t}\n }\n \n-static struct clk_ops exynos7420_clk_topc_ops = {\n+static struct clk_ops_uboot exynos7420_clk_topc_ops = {\n \t.get_rate\t= exynos7420_topc_get_rate,\n };\n \n static int exynos7420_clk_topc_probe(struct udevice *dev)\n@@ -154,9 +154,9 @@ static ulong exynos7420_top0_get_rate(struct clk *clk)\n \t\treturn 0;\n \t}\n }\n \n-static struct clk_ops exynos7420_clk_top0_ops = {\n+static struct clk_ops_uboot exynos7420_clk_top0_ops = {\n \t.get_rate\t= exynos7420_top0_get_rate,\n };\n \n static int exynos7420_clk_top0_probe(struct udevice *dev)\n@@ -206,9 +206,9 @@ static ulong exynos7420_peric1_get_rate(struct clk *clk)\n \n \treturn freq;\n }\n \n-static struct clk_ops exynos7420_clk_peric1_ops = {\n+static struct clk_ops_uboot exynos7420_clk_peric1_ops = {\n \t.get_rate\t= exynos7420_peric1_get_rate,\n };\n \n static const struct udevice_id exynos7420_clk_topc_compat[] = {\ndiff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c\nindex 4b67591af109..ec0f4511ebf9 100644\n--- a/drivers/clk/exynos/clk-pll.c\n+++ b/drivers/clk/exynos/clk-pll.c\n@@ -55,9 +55,9 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk)\n \tdo_div(fvco, (pdiv << sdiv));\n \treturn (unsigned long)fvco;\n }\n \n-static const struct clk_ops samsung_pll0822x_clk_min_ops = {\n+static const struct clk_ops_uboot samsung_pll0822x_clk_min_ops = {\n \t.get_rate = samsung_pll0822x_recalc_rate,\n };\n \n /*\n@@ -93,9 +93,9 @@ static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk)\n \n \treturn (unsigned long)fvco;\n }\n \n-static const struct clk_ops samsung_pll0831x_clk_min_ops = {\n+static const struct clk_ops_uboot samsung_pll0831x_clk_min_ops = {\n \t.get_rate = samsung_pll0831x_recalc_rate,\n };\n \n static struct clk *_samsung_clk_register_pll(void __iomem *base,\ndiff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h\nindex c25b7cb59d4f..c8d5d61991ee 100644\n--- a/drivers/clk/exynos/clk.h\n+++ b/drivers/clk/exynos/clk.h\n@@ -32,9 +32,9 @@ static int _name##_of_xlate(struct clk *clk,\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n \treturn 0;\t\t\t\t\t\t\t\\\n }\t\t\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-static const struct clk_ops _name##_clk_ops = {\t\t\t\t\\\n+static const struct clk_ops_uboot _name##_clk_ops = {\t\t\t\t\\\n \t.set_rate = ccf_clk_set_rate,\t\t\t\t\t\\\n \t.get_rate = ccf_clk_get_rate,\t\t\t\t\t\\\n \t.set_parent = ccf_clk_set_parent,\t\t\t\t\\\n \t.enable = ccf_clk_enable,\t\t\t\t\t\\\ndiff --git a/drivers/clk/ics8n3qv01.c b/drivers/clk/ics8n3qv01.c\nindex 9c61a84ea61f..04e6a349436a 100644\n--- a/drivers/clk/ics8n3qv01.c\n+++ b/drivers/clk/ics8n3qv01.c\n@@ -195,9 +195,9 @@ static int ics8n3qv01_disable(struct clk *clk)\n {\n \treturn 0;\n }\n \n-static const struct clk_ops ics8n3qv01_ops = {\n+static const struct clk_ops_uboot ics8n3qv01_ops = {\n \t.get_rate = ics8n3qv01_get_rate,\n \t.set_rate = ics8n3qv01_set_rate,\n \t.enable = ics8n3qv01_enable,\n \t.disable = ics8n3qv01_disable,\ndiff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c\nindex e1a3c0af308b..848c7b9d3fb1 100644\n--- a/drivers/clk/imx/clk-composite-8m.c\n+++ b/drivers/clk/imx/clk-composite-8m.c\n@@ -110,9 +110,9 @@ static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,\n \n \treturn clk_get_rate(&composite->clk);\n }\n \n-static const struct clk_ops imx8m_clk_composite_divider_ops = {\n+static const struct clk_ops_uboot imx8m_clk_composite_divider_ops = {\n \t.get_rate = imx8m_clk_composite_divider_recalc_rate,\n \t.set_rate = imx8m_clk_composite_divider_set_rate,\n };\n \n@@ -173,9 +173,9 @@ static int imx8m_clk_mux_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-const struct clk_ops imx8m_clk_mux_ops = {\n+const struct clk_ops_uboot imx8m_clk_mux_ops = {\n \t.get_rate = clk_generic_get_rate,\n \t.set_parent = imx8m_clk_mux_set_parent,\n };\n \ndiff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c\nindex 61692d34f926..b591db04c249 100644\n--- a/drivers/clk/imx/clk-composite-93.c\n+++ b/drivers/clk/imx/clk-composite-93.c\n@@ -77,9 +77,9 @@ static int imx93_clk_composite_gate_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops imx93_clk_composite_gate_ops = {\n+static const struct clk_ops_uboot imx93_clk_composite_gate_ops = {\n \t.enable = imx93_clk_composite_gate_enable,\n \t.disable = imx93_clk_composite_gate_disable,\n };\n \ndiff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c\nindex b3926564a226..b885c4bc01d4 100644\n--- a/drivers/clk/imx/clk-fracn-gppll.c\n+++ b/drivers/clk/imx/clk-fracn-gppll.c\n@@ -324,9 +324,9 @@ static int clk_fracn_gppll_unprepare(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_fracn_gppll_ops = {\n+static const struct clk_ops_uboot clk_fracn_gppll_ops = {\n \t.enable\t\t= clk_fracn_gppll_prepare,\n \t.disable\t= clk_fracn_gppll_unprepare,\n \t.get_rate\t= clk_fracn_gppll_recalc_rate,\n \t.set_rate\t= clk_fracn_gppll_set_rate,\ndiff --git a/drivers/clk/imx/clk-gate-93.c b/drivers/clk/imx/clk-gate-93.c\nindex d7f2640fbb7c..ff3ae5b57d36 100644\n--- a/drivers/clk/imx/clk-gate-93.c\n+++ b/drivers/clk/imx/clk-gate-93.c\n@@ -102,9 +102,9 @@ static ulong imx93_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn -ENODEV;\n }\n \n-static const struct clk_ops imx93_clk_gate_ops = {\n+static const struct clk_ops_uboot imx93_clk_gate_ops = {\n \t.enable = imx93_clk_gate_enable,\n \t.disable = imx93_clk_gate_disable,\n \t.get_rate = clk_generic_get_rate,\n \t.set_rate = imx93_clk_set_rate,\ndiff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c\nindex fa07b13249b6..b5cd1b31036e 100644\n--- a/drivers/clk/imx/clk-gate2.c\n+++ b/drivers/clk/imx/clk-gate2.c\n@@ -82,9 +82,9 @@ static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)\n \n \treturn -ENODEV;\n }\n \n-static const struct clk_ops clk_gate2_ops = {\n+static const struct clk_ops_uboot clk_gate2_ops = {\n \t.set_rate = clk_gate2_set_rate,\n \t.enable = clk_gate2_enable,\n \t.disable = clk_gate2_disable,\n \t.get_rate = clk_generic_get_rate,\ndiff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c\nindex b69355cefc76..a11db0a3ac40 100644\n--- a/drivers/clk/imx/clk-imx6q.c\n+++ b/drivers/clk/imx/clk-imx6q.c\n@@ -22,9 +22,9 @@ static int imx6q_clk_request(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops imx6q_clk_ops = {\n+static struct clk_ops_uboot imx6q_clk_ops = {\n \t.request = imx6q_clk_request,\n \t.set_rate = ccf_clk_set_rate,\n \t.get_rate = ccf_clk_get_rate,\n \t.enable = ccf_clk_enable,\ndiff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c\nindex 32fb949ffbcc..541e63e8717b 100644\n--- a/drivers/clk/imx/clk-imx6ul.c\n+++ b/drivers/clk/imx/clk-imx6ul.c\n@@ -24,9 +24,9 @@ static int imx6ul_clk_request(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops imx6ul_clk_ops = {\n+static struct clk_ops_uboot imx6ul_clk_ops = {\n \t.request = imx6ul_clk_request,\n \t.set_rate = ccf_clk_set_rate,\n \t.get_rate = ccf_clk_get_rate,\n \t.enable = ccf_clk_enable,\ndiff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c\nindex 96cf5fece75f..423b052cc5b6 100644\n--- a/drivers/clk/imx/clk-imx8.c\n+++ b/drivers/clk/imx/clk-imx8.c\n@@ -77,9 +77,9 @@ static void imx8_clk_dump(struct udevice *dev)\n \t}\n }\n #endif\n \n-static struct clk_ops imx8_clk_ops = {\n+static struct clk_ops_uboot imx8_clk_ops = {\n \t.set_rate = imx8_clk_set_rate,\n \t.get_rate = imx8_clk_get_rate,\n \t.enable = imx8_clk_enable,\n \t.disable = imx8_clk_disable,\ndiff --git a/drivers/clk/imx/clk-imxrt1020.c b/drivers/clk/imx/clk-imxrt1020.c\nindex c14afdaf2364..c2797237a002 100644\n--- a/drivers/clk/imx/clk-imxrt1020.c\n+++ b/drivers/clk/imx/clk-imxrt1020.c\n@@ -12,9 +12,9 @@\n #include <dt-bindings/clock/imxrt1020-clock.h>\n \n #include \"clk.h\"\n \n-static struct clk_ops imxrt1020_clk_ops = {\n+static struct clk_ops_uboot imxrt1020_clk_ops = {\n \t.set_rate = ccf_clk_set_rate,\n \t.get_rate = ccf_clk_get_rate,\n \t.enable = ccf_clk_enable,\n \t.disable = ccf_clk_disable,\ndiff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c\nindex bfd5dd6c4644..ed31cb2d09ef 100644\n--- a/drivers/clk/imx/clk-imxrt1170.c\n+++ b/drivers/clk/imx/clk-imxrt1170.c\n@@ -88,9 +88,9 @@ static int imxrt1170_clk_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn clk_set_parent(c, cp);\n }\n \n-static struct clk_ops imxrt1170_clk_ops = {\n+static struct clk_ops_uboot imxrt1170_clk_ops = {\n \t.set_rate = imxrt1170_clk_set_rate,\n \t.get_rate = imxrt1170_clk_get_rate,\n \t.enable = imxrt1170_clk_enable,\n \t.disable = imxrt1170_clk_disable,\ndiff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c\nindex 378cdff072fe..de26b1e3f83d 100644\n--- a/drivers/clk/imx/clk-pfd.c\n+++ b/drivers/clk/imx/clk-pfd.c\n@@ -73,9 +73,9 @@ static unsigned long clk_pfd_set_rate(struct clk *clk, unsigned long rate)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_pfd_ops = {\n+static const struct clk_ops_uboot clk_pfd_ops = {\n \t.get_rate\t= clk_pfd_recalc_rate,\n \t.set_rate\t= clk_pfd_set_rate,\n };\n \ndiff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c\nindex f9fcec18f9f8..0bb4d2c7e28c 100644\n--- a/drivers/clk/imx/clk-pll14xx.c\n+++ b/drivers/clk/imx/clk-pll14xx.c\n@@ -371,16 +371,16 @@ static int clk_pll14xx_unprepare(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_pll1416x_ops = {\n+static const struct clk_ops_uboot clk_pll1416x_ops = {\n \t.enable\t\t= clk_pll14xx_prepare,\n \t.disable\t= clk_pll14xx_unprepare,\n \t.set_rate\t= clk_pll1416x_set_rate,\n \t.get_rate\t= clk_pll1416x_recalc_rate,\n };\n \n-static const struct clk_ops clk_pll1443x_ops = {\n+static const struct clk_ops_uboot clk_pll1443x_ops = {\n \t.enable\t\t= clk_pll14xx_prepare,\n \t.disable\t= clk_pll14xx_unprepare,\n \t.set_rate\t= clk_pll1443x_set_rate,\n \t.get_rate\t= clk_pll1443x_recalc_rate,\ndiff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c\nindex 85b6a9809e8d..e907fd378c6d 100644\n--- a/drivers/clk/imx/clk-pllv3.c\n+++ b/drivers/clk/imx/clk-pllv3.c\n@@ -139,16 +139,16 @@ static int clk_pllv3_generic_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_pllv3_generic_ops = {\n+static const struct clk_ops_uboot clk_pllv3_generic_ops = {\n \t.get_rate\t= clk_pllv3_generic_get_rate,\n \t.enable\t\t= clk_pllv3_generic_enable,\n \t.disable\t= clk_pllv3_generic_disable,\n \t.set_rate\t= clk_pllv3_generic_set_rate,\n };\n \n-static const struct clk_ops clk_pllv3_genericv2_ops = {\n+static const struct clk_ops_uboot clk_pllv3_genericv2_ops = {\n \t.get_rate\t= clk_pllv3_genericv2_get_rate,\n \t.enable\t\t= clk_pllv3_generic_enable,\n \t.disable\t= clk_pllv3_generic_disable,\n \t.set_rate\t= clk_pllv3_genericv2_set_rate,\n@@ -192,9 +192,9 @@ static ulong clk_pllv3_sys_set_rate(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_pllv3_sys_ops = {\n+static const struct clk_ops_uboot clk_pllv3_sys_ops = {\n \t.enable\t\t= clk_pllv3_generic_enable,\n \t.disable\t= clk_pllv3_generic_disable,\n \t.get_rate\t= clk_pllv3_sys_get_rate,\n \t.set_rate\t= clk_pllv3_sys_set_rate,\n@@ -260,9 +260,9 @@ static ulong clk_pllv3_av_set_rate(struct clk *clk, ulong rate)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_pllv3_av_ops = {\n+static const struct clk_ops_uboot clk_pllv3_av_ops = {\n \t.enable\t\t= clk_pllv3_generic_enable,\n \t.disable\t= clk_pllv3_generic_disable,\n \t.get_rate\t= clk_pllv3_av_get_rate,\n \t.set_rate\t= clk_pllv3_av_set_rate,\n@@ -274,9 +274,9 @@ static ulong clk_pllv3_enet_get_rate(struct clk *clk)\n \n \treturn pll->ref_clock;\n }\n \n-static const struct clk_ops clk_pllv3_enet_ops = {\n+static const struct clk_ops_uboot clk_pllv3_enet_ops = {\n \t.enable\t= clk_pllv3_generic_enable,\n \t.disable\t= clk_pllv3_generic_disable,\n \t.get_rate\t= clk_pllv3_enet_get_rate,\n };\ndiff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c\nindex a677a7caac7c..1d473ebb4d90 100644\n--- a/drivers/clk/intel/clk_intel.c\n+++ b/drivers/clk/intel/clk_intel.c\n@@ -18,9 +18,9 @@ static ulong intel_clk_get_rate(struct clk *clk)\n \t\treturn -ENODEV;\n \t}\n }\n \n-static struct clk_ops intel_clk_ops = {\n+static struct clk_ops_uboot intel_clk_ops = {\n \t.get_rate\t= intel_clk_get_rate,\n };\n \n static const struct udevice_id intel_clk_ids[] = {\ndiff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c\nindex b4de38719e1c..7c55bc4defa8 100644\n--- a/drivers/clk/mediatek/clk-mtk.c\n+++ b/drivers/clk/mediatek/clk-mtk.c\n@@ -160,9 +160,9 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,\n \telse\n \t\tparent.dev = clk->dev;\n \n \targs.node = dev_ofnode(parent.dev);\n-\tret = ((struct clk_ops *)parent.dev->driver->ops)->of_xlate(&parent, &args);\n+\tret = ((struct clk_ops_uboot *)parent.dev->driver->ops)->of_xlate(&parent, &args);\n \tif (ret)\n \t\treturn ret;\n \n \treturn clk_get_rate(&parent);\n@@ -1177,9 +1177,9 @@ static void mtk_clk_gate_dump(struct udevice *dev)\n \t}\n }\n #endif\n \n-const struct clk_ops mtk_clk_apmixedsys_ops = {\n+const struct clk_ops_uboot mtk_clk_apmixedsys_ops = {\n \t.of_xlate = mtk_apmixedsys_of_xlate,\n \t.enable = mtk_apmixedsys_enable,\n \t.disable = mtk_apmixedsys_disable,\n \t.set_rate = mtk_apmixedsys_set_rate,\n@@ -1188,9 +1188,9 @@ const struct clk_ops mtk_clk_apmixedsys_ops = {\n \t.dump = mtk_apmixedsys_dump,\n #endif\n };\n \n-const struct clk_ops mtk_clk_fixed_pll_ops = {\n+const struct clk_ops_uboot mtk_clk_fixed_pll_ops = {\n \t.of_xlate = mtk_topckgen_of_xlate,\n \t.enable = mtk_dummy_enable,\n \t.disable = mtk_dummy_enable,\n \t.get_rate = mtk_topckgen_get_rate,\n@@ -1198,9 +1198,9 @@ const struct clk_ops mtk_clk_fixed_pll_ops = {\n \t.dump = mtk_topckgen_dump,\n #endif\n };\n \n-const struct clk_ops mtk_clk_topckgen_ops = {\n+const struct clk_ops_uboot mtk_clk_topckgen_ops = {\n \t.of_xlate = mtk_topckgen_of_xlate,\n \t.enable = mtk_topckgen_enable,\n \t.disable = mtk_topckgen_disable,\n \t.get_rate = mtk_topckgen_get_rate,\n@@ -1209,9 +1209,9 @@ const struct clk_ops mtk_clk_topckgen_ops = {\n \t.dump = mtk_topckgen_dump,\n #endif\n };\n \n-const struct clk_ops mtk_clk_infrasys_ops = {\n+const struct clk_ops_uboot mtk_clk_infrasys_ops = {\n \t.of_xlate = mtk_infrasys_of_xlate,\n \t.enable = mtk_clk_infrasys_enable,\n \t.disable = mtk_clk_infrasys_disable,\n \t.get_rate = mtk_infrasys_get_rate,\n@@ -1220,9 +1220,9 @@ const struct clk_ops mtk_clk_infrasys_ops = {\n \t.dump = mtk_infrasys_dump,\n #endif\n };\n \n-const struct clk_ops mtk_clk_gate_ops = {\n+const struct clk_ops_uboot mtk_clk_gate_ops = {\n \t.of_xlate = mtk_clk_gate_of_xlate,\n \t.enable = mtk_clk_gate_enable,\n \t.disable = mtk_clk_gate_disable,\n \t.get_rate = mtk_clk_gate_get_rate,\ndiff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h\nindex e618e982e8b9..3fef8b0d7bd6 100644\n--- a/drivers/clk/mediatek/clk-mtk.h\n+++ b/drivers/clk/mediatek/clk-mtk.h\n@@ -289,13 +289,13 @@ struct mtk_cg_priv {\n \tint num_gates;\n \tint gates_offs;\n };\n \n-extern const struct clk_ops mtk_clk_apmixedsys_ops;\n-extern const struct clk_ops mtk_clk_fixed_pll_ops;\n-extern const struct clk_ops mtk_clk_topckgen_ops;\n-extern const struct clk_ops mtk_clk_infrasys_ops;\n-extern const struct clk_ops mtk_clk_gate_ops;\n+extern const struct clk_ops_uboot mtk_clk_apmixedsys_ops;\n+extern const struct clk_ops_uboot mtk_clk_fixed_pll_ops;\n+extern const struct clk_ops_uboot mtk_clk_topckgen_ops;\n+extern const struct clk_ops_uboot mtk_clk_infrasys_ops;\n+extern const struct clk_ops_uboot mtk_clk_gate_ops;\n \n int mtk_common_clk_init(struct udevice *dev,\n \t\t\tconst struct mtk_clk_tree *tree);\n int mtk_common_clk_infrasys_init(struct udevice *dev,\ndiff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c\nindex a1b8d7914910..e87ad773da8f 100644\n--- a/drivers/clk/meson/a1.c\n+++ b/drivers/clk/meson/a1.c\n@@ -700,9 +700,9 @@ static void meson_clk_dump(struct udevice *dev)\n \t}\n }\n #endif\n \n-static struct clk_ops meson_clk_ops = {\n+static struct clk_ops_uboot meson_clk_ops = {\n \t.disable\t= meson_clk_disable,\n \t.enable\t\t= meson_clk_enable,\n \t.get_rate\t= meson_clk_get_rate,\n \t.set_rate\t= meson_clk_set_rate,\ndiff --git a/drivers/clk/meson/axg-ao.c b/drivers/clk/meson/axg-ao.c\nindex 6ccf52127b02..e105b8512c20 100644\n--- a/drivers/clk/meson/axg-ao.c\n+++ b/drivers/clk/meson/axg-ao.c\n@@ -63,9 +63,9 @@ static int meson_clk_request(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops meson_clk_ops = {\n+static struct clk_ops_uboot meson_clk_ops = {\n \t.disable\t= meson_clk_disable,\n \t.enable\t\t= meson_clk_enable,\n \t.request\t= meson_clk_request,\n };\ndiff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c\nindex c421a622a587..6ec9c4586ca2 100644\n--- a/drivers/clk/meson/axg.c\n+++ b/drivers/clk/meson/axg.c\n@@ -303,9 +303,9 @@ static int meson_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops meson_clk_ops = {\n+static struct clk_ops_uboot meson_clk_ops = {\n \t.disable\t= meson_clk_disable,\n \t.enable\t\t= meson_clk_enable,\n \t.get_rate\t= meson_clk_get_rate,\n };\ndiff --git a/drivers/clk/meson/clk-measure.c b/drivers/clk/meson/clk-measure.c\nindex f653fc635527..a89721638bcb 100644\n--- a/drivers/clk/meson/clk-measure.c\n+++ b/drivers/clk/meson/clk-measure.c\n@@ -590,9 +590,9 @@ static int meson_clk_msr_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops meson_clk_msr_ops = {\n+static struct clk_ops_uboot meson_clk_msr_ops = {\n \t.of_xlate = meson_clk_msr_xlate,\n \t.dump = meson_clk_msr_dump,\n };\n \ndiff --git a/drivers/clk/meson/g12a-ao.c b/drivers/clk/meson/g12a-ao.c\nindex 61d489c6e1c8..1f00744abacc 100644\n--- a/drivers/clk/meson/g12a-ao.c\n+++ b/drivers/clk/meson/g12a-ao.c\n@@ -63,9 +63,9 @@ static int meson_clk_request(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops meson_clk_ops = {\n+static struct clk_ops_uboot meson_clk_ops = {\n \t.disable\t= meson_clk_disable,\n \t.enable\t\t= meson_clk_enable,\n \t.request\t= meson_clk_request,\n };\ndiff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c\nindex a7a42b2edb6a..c0172e243274 100644\n--- a/drivers/clk/meson/g12a.c\n+++ b/drivers/clk/meson/g12a.c\n@@ -993,9 +993,9 @@ static int meson_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops meson_clk_ops = {\n+static struct clk_ops_uboot meson_clk_ops = {\n \t.disable\t= meson_clk_disable,\n \t.enable\t\t= meson_clk_enable,\n \t.get_rate\t= meson_clk_get_rate,\n \t.set_parent\t= meson_clk_set_parent,\ndiff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c\nindex 51f124869c9c..14c0d1f9158d 100644\n--- a/drivers/clk/meson/gxbb.c\n+++ b/drivers/clk/meson/gxbb.c\n@@ -947,9 +947,9 @@ static int meson_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops meson_clk_ops = {\n+static struct clk_ops_uboot meson_clk_ops = {\n \t.disable\t= meson_clk_disable,\n \t.enable\t\t= meson_clk_enable,\n \t.get_rate\t= meson_clk_get_rate,\n \t.set_parent\t= meson_clk_set_parent,\ndiff --git a/drivers/clk/microchip/mpfs_clk_cfg.c b/drivers/clk/microchip/mpfs_clk_cfg.c\nindex b64fb6b71931..294ee0f5cc0d 100644\n--- a/drivers/clk/microchip/mpfs_clk_cfg.c\n+++ b/drivers/clk/microchip/mpfs_clk_cfg.c\n@@ -137,9 +137,9 @@ int mpfs_clk_register_cfgs(struct clk *parent, struct regmap *regmap)\n \t}\n \treturn 0;\n }\n \n-const struct clk_ops mpfs_cfg_clk_ops = {\n+const struct clk_ops_uboot mpfs_cfg_clk_ops = {\n \t.set_rate = mpfs_cfg_clk_set_rate,\n \t.get_rate = mpfs_cfg_clk_recalc_rate,\n };\n \ndiff --git a/drivers/clk/microchip/mpfs_clk_msspll.c b/drivers/clk/microchip/mpfs_clk_msspll.c\nindex 02b4a3444671..489f6cc67d4b 100644\n--- a/drivers/clk/microchip/mpfs_clk_msspll.c\n+++ b/drivers/clk/microchip/mpfs_clk_msspll.c\n@@ -105,9 +105,9 @@ int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent)\n \n \treturn 0;\n }\n \n-const struct clk_ops mpfs_msspll_clk_ops = {\n+const struct clk_ops_uboot mpfs_msspll_clk_ops = {\n \t.get_rate = mpfs_clk_msspll_recalc_rate,\n };\n \n U_BOOT_DRIVER(mpfs_msspll_clock) = {\ndiff --git a/drivers/clk/microchip/mpfs_clk_periph.c b/drivers/clk/microchip/mpfs_clk_periph.c\nindex 706d6841ee49..ecdfa9c36359 100644\n--- a/drivers/clk/microchip/mpfs_clk_periph.c\n+++ b/drivers/clk/microchip/mpfs_clk_periph.c\n@@ -183,9 +183,9 @@ int mpfs_clk_register_periphs(struct udevice *dev, struct regmap *regmap)\n \n \treturn 0;\n }\n \n-const struct clk_ops mpfs_periph_clk_ops = {\n+const struct clk_ops_uboot mpfs_periph_clk_ops = {\n \t.enable = mpfs_periph_clk_enable,\n \t.disable = mpfs_periph_clk_disable,\n \t.get_rate = mpfs_periph_clk_recalc_rate,\n };\ndiff --git a/drivers/clk/mpc83xx_clk.c b/drivers/clk/mpc83xx_clk.c\nindex a43fff2e7ed9..e163959a7b75 100644\n--- a/drivers/clk/mpc83xx_clk.c\n+++ b/drivers/clk/mpc83xx_clk.c\n@@ -311,9 +311,9 @@ int get_serial_clock(void)\n \n \treturn priv->speed[MPC83XX_CLK_CSB];\n }\n \n-const struct clk_ops mpc83xx_clk_ops = {\n+const struct clk_ops_uboot mpc83xx_clk_ops = {\n \t.request = mpc83xx_clk_request,\n \t.get_rate = mpc83xx_clk_get_rate,\n \t.enable = mpc83xx_clk_enable,\n };\ndiff --git a/drivers/clk/mtmips/clk-mt7620.c b/drivers/clk/mtmips/clk-mt7620.c\nindex 57d2e2f04c64..812e7bb5a570 100644\n--- a/drivers/clk/mtmips/clk-mt7620.c\n+++ b/drivers/clk/mtmips/clk-mt7620.c\n@@ -104,9 +104,9 @@ static int mt7620_clk_disable(struct clk *clk)\n \n \treturn mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0);\n }\n \n-const struct clk_ops mt7620_clk_ops = {\n+const struct clk_ops_uboot mt7620_clk_ops = {\n \t.enable = mt7620_clk_enable,\n \t.disable = mt7620_clk_disable,\n \t.get_rate = mt7620_clk_get_rate,\n };\ndiff --git a/drivers/clk/mtmips/clk-mt7621.c b/drivers/clk/mtmips/clk-mt7621.c\nindex 03363b70d74e..6e780b7c9c45 100644\n--- a/drivers/clk/mtmips/clk-mt7621.c\n+++ b/drivers/clk/mtmips/clk-mt7621.c\n@@ -180,9 +180,9 @@ static int mt7621_clk_request(struct clk *clk)\n \t\treturn -EINVAL;\n \treturn 0;\n }\n \n-const struct clk_ops mt7621_clk_ops = {\n+const struct clk_ops_uboot mt7621_clk_ops = {\n \t.request = mt7621_clk_request,\n \t.enable = mt7621_clk_enable,\n \t.disable = mt7621_clk_disable,\n \t.get_rate = mt7621_clk_get_rate,\ndiff --git a/drivers/clk/mtmips/clk-mt7628.c b/drivers/clk/mtmips/clk-mt7628.c\nindex 2e263fb2cd28..a8cb5f7ae100 100644\n--- a/drivers/clk/mtmips/clk-mt7628.c\n+++ b/drivers/clk/mtmips/clk-mt7628.c\n@@ -100,9 +100,9 @@ static int mt7628_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-const struct clk_ops mt7628_clk_ops = {\n+const struct clk_ops_uboot mt7628_clk_ops = {\n \t.enable = mt7628_clk_enable,\n \t.disable = mt7628_clk_disable,\n \t.get_rate = mt7628_clk_get_rate,\n };\ndiff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c\nindex 30330393f760..b25b3df3b666 100644\n--- a/drivers/clk/mvebu/armada-37xx-periph.c\n+++ b/drivers/clk/mvebu/armada-37xx-periph.c\n@@ -598,9 +598,9 @@ static int armada_37xx_periph_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static const struct clk_ops armada_37xx_periph_clk_ops = {\n+static const struct clk_ops_uboot armada_37xx_periph_clk_ops = {\n \t.get_rate = armada_37xx_periph_clk_get_rate,\n \t.set_rate = armada_37xx_periph_clk_set_rate,\n \t.set_parent = armada_37xx_periph_clk_set_parent,\n \t.enable = armada_37xx_periph_clk_enable,\ndiff --git a/drivers/clk/mvebu/armada-37xx-tbg.c b/drivers/clk/mvebu/armada-37xx-tbg.c\nindex c1bab84c070e..598604f10c47 100644\n--- a/drivers/clk/mvebu/armada-37xx-tbg.c\n+++ b/drivers/clk/mvebu/armada-37xx-tbg.c\n@@ -134,9 +134,9 @@ static int armada_37xx_tbg_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static const struct clk_ops armada_37xx_tbg_clk_ops = {\n+static const struct clk_ops_uboot armada_37xx_tbg_clk_ops = {\n \t.get_rate = armada_37xx_tbg_clk_get_rate,\n };\n \n static const struct udevice_id armada_37xx_tbg_clk_ids[] = {\ndiff --git a/drivers/clk/nuvoton/clk_npcm.c b/drivers/clk/nuvoton/clk_npcm.c\nindex 18cb9cddbf38..ecb23431ecbd 100644\n--- a/drivers/clk/nuvoton/clk_npcm.c\n+++ b/drivers/clk/nuvoton/clk_npcm.c\n@@ -299,9 +299,9 @@ static int npcm_clk_request(struct clk *clk)\n \n \treturn 0;\n }\n \n-const struct clk_ops npcm_clk_ops = {\n+const struct clk_ops_uboot npcm_clk_ops = {\n \t.get_rate = npcm_clk_get_rate,\n \t.set_rate = npcm_clk_set_rate,\n \t.set_parent = npcm_clk_set_parent,\n \t.request = npcm_clk_request,\ndiff --git a/drivers/clk/nuvoton/clk_npcm.h b/drivers/clk/nuvoton/clk_npcm.h\nindex b4726d8381ea..0e5b1ba8b432 100644\n--- a/drivers/clk/nuvoton/clk_npcm.h\n+++ b/drivers/clk/nuvoton/clk_npcm.h\n@@ -100,7 +100,7 @@ struct npcm_clk_priv {\n \tstruct npcm_clk_data *clk_data;\n \tint num_clks;\n };\n \n-extern const struct clk_ops npcm_clk_ops;\n+extern const struct clk_ops_uboot npcm_clk_ops;\n \n #endif\ndiff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c\nindex 513112c1146c..832177b8547f 100644\n--- a/drivers/clk/owl/clk_owl.c\n+++ b/drivers/clk/owl/clk_owl.c\n@@ -237,9 +237,9 @@ static int owl_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static const struct clk_ops owl_clk_ops = {\n+static const struct clk_ops_uboot owl_clk_ops = {\n \t.enable = owl_clk_enable,\n \t.disable = owl_clk_disable,\n \t.get_rate = owl_clk_get_rate,\n \t.set_rate = owl_clk_set_rate,\ndiff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c\nindex 6b46d9db744b..6df8285cb301 100644\n--- a/drivers/clk/qcom/clock-qcom.c\n+++ b/drivers/clk/qcom/clock-qcom.c\n@@ -376,9 +376,9 @@ static void __maybe_unused msm_dump_clks(struct udevice *dev)\n \tdump_gplls(dev, priv->base);\n \tdump_rcgs(dev);\n }\n \n-static struct clk_ops msm_clk_ops = {\n+static struct clk_ops_uboot msm_clk_ops = {\n \t.set_rate = msm_clk_set_rate,\n \t.enable = msm_clk_enable,\n #if IS_ENABLED(CONFIG_CMD_CLK)\n \t.dump = msm_dump_clks,\ndiff --git a/drivers/clk/qcom/clock-sm8550.c b/drivers/clk/qcom/clock-sm8550.c\nindex 7c06489b9c4d..02d6e8d77345 100644\n--- a/drivers/clk/qcom/clock-sm8550.c\n+++ b/drivers/clk/qcom/clock-sm8550.c\n@@ -344,9 +344,9 @@ static int tcsrcc_sm8550_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops tcsrcc_sm8550_clk_ops = {\n+static struct clk_ops_uboot tcsrcc_sm8550_clk_ops = {\n \t.enable = tcsrcc_sm8550_clk_enable,\n \t.get_rate = tcsrcc_sm8550_clk_get_rate,\n };\n \ndiff --git a/drivers/clk/qcom/clock-sm8650.c b/drivers/clk/qcom/clock-sm8650.c\nindex 7c49e99c005c..fbd1a186d1ba 100644\n--- a/drivers/clk/qcom/clock-sm8650.c\n+++ b/drivers/clk/qcom/clock-sm8650.c\n@@ -342,9 +342,9 @@ static int tcsrcc_sm8650_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops tcsrcc_sm8650_clk_ops = {\n+static struct clk_ops_uboot tcsrcc_sm8650_clk_ops = {\n \t.enable = tcsrcc_sm8650_clk_enable,\n \t.get_rate = tcsrcc_sm8650_clk_get_rate,\n };\n \ndiff --git a/drivers/clk/qcom/clock-x1e80100.c b/drivers/clk/qcom/clock-x1e80100.c\nindex 542d6248d658..ee57a02564a3 100644\n--- a/drivers/clk/qcom/clock-x1e80100.c\n+++ b/drivers/clk/qcom/clock-x1e80100.c\n@@ -375,9 +375,9 @@ static int tcsrcc_x1e80100_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops tcsrcc_x1e80100_clk_ops = {\n+static struct clk_ops_uboot tcsrcc_x1e80100_clk_ops = {\n \t.enable = tcsrcc_x1e80100_clk_enable,\n \t.get_rate = tcsrcc_x1e80100_clk_get_rate,\n };\n \ndiff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c\nindex 9b6fce4675c0..e659ad39da7d 100644\n--- a/drivers/clk/renesas/clk-rcar-gen2.c\n+++ b/drivers/clk/renesas/clk-rcar-gen2.c\n@@ -259,9 +259,9 @@ static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)\n \n \treturn 0;\n }\n \n-const struct clk_ops gen2_clk_ops = {\n+const struct clk_ops_uboot gen2_clk_ops = {\n \t.enable\t\t= gen2_clk_enable,\n \t.disable\t= gen2_clk_disable,\n \t.get_rate\t= gen2_clk_get_rate,\n \t.set_rate\t= gen2_clk_set_rate,\ndiff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c\nindex 5745acf4023c..ae21f2a663f8 100644\n--- a/drivers/clk/renesas/clk-rcar-gen3.c\n+++ b/drivers/clk/renesas/clk-rcar-gen3.c\n@@ -451,9 +451,9 @@ static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)\n \n \treturn 0;\n }\n \n-const struct clk_ops gen3_clk_ops = {\n+const struct clk_ops_uboot gen3_clk_ops = {\n \t.enable\t\t= gen3_clk_enable,\n \t.disable\t= gen3_clk_disable,\n \t.get_rate\t= gen3_clk_get_rate,\n \t.set_rate\t= gen3_clk_set_rate,\ndiff --git a/drivers/clk/renesas/compound-clock.c b/drivers/clk/renesas/compound-clock.c\nindex 499a2598833c..2dc3e2e0deea 100644\n--- a/drivers/clk/renesas/compound-clock.c\n+++ b/drivers/clk/renesas/compound-clock.c\n@@ -47,9 +47,9 @@ static ulong clk_compound_rate_set_rate(struct clk *clk, ulong rate)\n {\n \treturn 0;\t/* Set rate is not forwarded to SCP */\n }\n \n-const struct clk_ops clk_compound_rate_ops = {\n+const struct clk_ops_uboot clk_compound_rate_ops = {\n \t.enable\t\t= clk_compound_rate_enable,\n \t.disable\t= clk_compound_rate_disable,\n \t.get_rate\t= clk_compound_rate_get_rate,\n \t.set_rate\t= clk_compound_rate_set_rate,\ndiff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c\nindex d207bf615cee..3ef98237ba15 100644\n--- a/drivers/clk/renesas/r9a06g032-clocks.c\n+++ b/drivers/clk/renesas/r9a06g032-clocks.c\n@@ -1048,9 +1048,9 @@ static int r9a06g032_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *a\n \n \treturn 0;\n }\n \n-static const struct clk_ops r9a06g032_clk_ops = {\n+static const struct clk_ops_uboot r9a06g032_clk_ops = {\n \t.enable\t\t= r9a06g032_clk_enable,\n \t.disable\t= r9a06g032_clk_disable,\n \t.get_rate\t= r9a06g032_clk_get_rate,\n \t.set_rate\t= r9a06g032_clk_set_rate,\ndiff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h\nindex ca7c3ed6b544..e1f075b03597 100644\n--- a/drivers/clk/renesas/rcar-gen2-cpg.h\n+++ b/drivers/clk/renesas/rcar-gen2-cpg.h\n@@ -42,7 +42,7 @@ struct gen2_clk_priv {\n \n int gen2_clk_probe(struct udevice *dev);\n int gen2_clk_remove(struct udevice *dev);\n \n-extern const struct clk_ops gen2_clk_ops;\n+extern const struct clk_ops_uboot gen2_clk_ops;\n \n #endif\ndiff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h\nindex 4efb9b6ceefd..318fa9a3c741 100644\n--- a/drivers/clk/renesas/rcar-gen3-cpg.h\n+++ b/drivers/clk/renesas/rcar-gen3-cpg.h\n@@ -165,7 +165,7 @@ struct gen3_clk_priv {\n };\n \n int gen3_cpg_bind(struct udevice *parent);\n \n-extern const struct clk_ops gen3_clk_ops;\n+extern const struct clk_ops_uboot gen3_clk_ops;\n \n #endif\ndiff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c\nindex 7fce1f70d138..03cb4f26d474 100644\n--- a/drivers/clk/renesas/rzg2l-cpg.c\n+++ b/drivers/clk/renesas/rzg2l-cpg.c\n@@ -396,9 +396,9 @@ static ulong rzg2l_cpg_clk_set_rate(struct clk *clk, ulong rate)\n {\n \treturn rzg2l_cpg_clk_set_rate_by_id(clk->dev, clk->id, rate);\n }\n \n-static const struct clk_ops rzg2l_cpg_clk_ops = {\n+static const struct clk_ops_uboot rzg2l_cpg_clk_ops = {\n \t.enable\t\t= rzg2l_cpg_clk_enable,\n \t.disable\t= rzg2l_cpg_clk_disable,\n \t.of_xlate\t= rzg2l_cpg_clk_of_xlate,\n \t.get_rate\t= rzg2l_cpg_clk_get_rate,\ndiff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c\nindex b5054e84c326..6e7f745102d5 100644\n--- a/drivers/clk/rockchip/clk_px30.c\n+++ b/drivers/clk/rockchip/clk_px30.c\n@@ -1424,9 +1424,9 @@ static int px30_clk_enable(struct clk *clk)\n \tdebug(\"%s: unsupported clk %ld\\n\", __func__, clk->id);\n \treturn -ENOENT;\n }\n \n-static struct clk_ops px30_clk_ops = {\n+static struct clk_ops_uboot px30_clk_ops = {\n \t.get_rate = px30_clk_get_rate,\n \t.set_rate = px30_clk_set_rate,\n #if CONFIG_IS_ENABLED(OF_REAL)\n \t.set_parent = px30_clk_set_parent,\n@@ -1738,9 +1738,9 @@ static ulong px30_pmuclk_set_rate(struct clk *clk, ulong rate)\n \n \treturn ret;\n }\n \n-static struct clk_ops px30_pmuclk_ops = {\n+static struct clk_ops_uboot px30_pmuclk_ops = {\n \t.get_rate = px30_pmuclk_get_rate,\n \t.set_rate = px30_pmuclk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c\nindex 274428f2b4bd..e575143341d9 100644\n--- a/drivers/clk/rockchip/clk_rk3036.c\n+++ b/drivers/clk/rockchip/clk_rk3036.c\n@@ -311,9 +311,9 @@ static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn new_rate;\n }\n \n-static struct clk_ops rk3036_clk_ops = {\n+static struct clk_ops_uboot rk3036_clk_ops = {\n \t.get_rate\t= rk3036_clk_get_rate,\n \t.set_rate\t= rk3036_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rk3066.c b/drivers/clk/rockchip/clk_rk3066.c\nindex f7dea7859f74..9b6f7a2b6b00 100644\n--- a/drivers/clk/rockchip/clk_rk3066.c\n+++ b/drivers/clk/rockchip/clk_rk3066.c\n@@ -624,9 +624,9 @@ static int rk3066_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops rk3066_clk_ops = {\n+static struct clk_ops_uboot rk3066_clk_ops = {\n \t.disable\t= rk3066_clk_disable,\n \t.enable\t= rk3066_clk_enable,\n \t.get_rate\t= rk3066_clk_get_rate,\n \t.set_rate\t= rk3066_clk_set_rate,\ndiff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c\nindex a07285593b55..4665f0d31152 100644\n--- a/drivers/clk/rockchip/clk_rk3128.c\n+++ b/drivers/clk/rockchip/clk_rk3128.c\n@@ -539,9 +539,9 @@ static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn new_rate;\n }\n \n-static struct clk_ops rk3128_clk_ops = {\n+static struct clk_ops_uboot rk3128_clk_ops = {\n \t.get_rate\t= rk3128_clk_get_rate,\n \t.set_rate\t= rk3128_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c\nindex d8b03e1d7ab3..1c75c2d9bf5b 100644\n--- a/drivers/clk/rockchip/clk_rk3188.c\n+++ b/drivers/clk/rockchip/clk_rk3188.c\n@@ -530,9 +530,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn new_rate;\n }\n \n-static struct clk_ops rk3188_clk_ops = {\n+static struct clk_ops_uboot rk3188_clk_ops = {\n \t.get_rate\t= rk3188_clk_get_rate,\n \t.set_rate\t= rk3188_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c\nindex 9b71fd863bad..f40fe68de45b 100644\n--- a/drivers/clk/rockchip/clk_rk322x.c\n+++ b/drivers/clk/rockchip/clk_rk322x.c\n@@ -467,9 +467,9 @@ static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)\n \tdebug(\"%s: unsupported clk %ld\\n\", __func__, clk->id);\n \treturn -ENOENT;\n }\n \n-static struct clk_ops rk322x_clk_ops = {\n+static struct clk_ops_uboot rk322x_clk_ops = {\n \t.get_rate\t= rk322x_clk_get_rate,\n \t.set_rate\t= rk322x_clk_set_rate,\n \t.set_parent\t= rk322x_clk_set_parent,\n };\ndiff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c\nindex a4ff1c41abb8..b672e728fb0a 100644\n--- a/drivers/clk/rockchip/clk_rk3288.c\n+++ b/drivers/clk/rockchip/clk_rk3288.c\n@@ -945,9 +945,9 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par\n \tdebug(\"%s: unsupported clk %ld\\n\", __func__, clk->id);\n \treturn -ENOENT;\n }\n \n-static struct clk_ops rk3288_clk_ops = {\n+static struct clk_ops_uboot rk3288_clk_ops = {\n \t.get_rate\t= rk3288_clk_get_rate,\n \t.set_rate\t= rk3288_clk_set_rate,\n #if CONFIG_IS_ENABLED(OF_REAL)\n \t.set_parent\t= rk3288_clk_set_parent,\ndiff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c\nindex e73bb6790af2..828d545f5fab 100644\n--- a/drivers/clk/rockchip/clk_rk3308.c\n+++ b/drivers/clk/rockchip/clk_rk3308.c\n@@ -1128,9 +1128,9 @@ static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *par\n \treturn -ENOENT;\n }\n #endif\n \n-static struct clk_ops rk3308_clk_ops = {\n+static struct clk_ops_uboot rk3308_clk_ops = {\n \t.get_rate = rk3308_clk_get_rate,\n \t.set_rate = rk3308_clk_set_rate,\n #if CONFIG_IS_ENABLED(OF_REAL)\n \t.set_parent = rk3308_clk_set_parent,\ndiff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c\nindex 7701a9734ee0..cb5df70bfaa0 100644\n--- a/drivers/clk/rockchip/clk_rk3328.c\n+++ b/drivers/clk/rockchip/clk_rk3328.c\n@@ -886,9 +886,9 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)\n \tdebug(\"%s: unsupported clk %ld\\n\", __func__, clk->id);\n \treturn -ENOENT;\n }\n \n-static struct clk_ops rk3328_clk_ops = {\n+static struct clk_ops_uboot rk3328_clk_ops = {\n \t.get_rate = rk3328_clk_get_rate,\n \t.set_rate = rk3328_clk_set_rate,\n \t.set_parent = rk3328_clk_set_parent,\n };\ndiff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c\nindex 630253fbb1df..9949ebaf23fe 100644\n--- a/drivers/clk/rockchip/clk_rk3368.c\n+++ b/drivers/clk/rockchip/clk_rk3368.c\n@@ -569,9 +569,9 @@ static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *par\n \tdebug(\"%s: unsupported clk %ld\\n\", __func__, clk->id);\n \treturn -ENOENT;\n }\n \n-static struct clk_ops rk3368_clk_ops = {\n+static struct clk_ops_uboot rk3368_clk_ops = {\n \t.get_rate = rk3368_clk_get_rate,\n \t.set_rate = rk3368_clk_set_rate,\n #if CONFIG_IS_ENABLED(OF_REAL)\n \t.set_parent = rk3368_clk_set_parent,\ndiff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c\nindex 6e87db18be07..976afc57f0b7 100644\n--- a/drivers/clk/rockchip/clk_rk3399.c\n+++ b/drivers/clk/rockchip/clk_rk3399.c\n@@ -1363,9 +1363,9 @@ static int rk3399_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops rk3399_clk_ops = {\n+static struct clk_ops_uboot rk3399_clk_ops = {\n \t.get_rate = rk3399_clk_get_rate,\n \t.set_rate = rk3399_clk_set_rate,\n #if CONFIG_IS_ENABLED(OF_REAL)\n \t.set_parent = rk3399_clk_set_parent,\n@@ -1651,9 +1651,9 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)\n \n \treturn ret;\n }\n \n-static struct clk_ops rk3399_pmuclk_ops = {\n+static struct clk_ops_uboot rk3399_pmuclk_ops = {\n \t.get_rate = rk3399_pmuclk_get_rate,\n \t.set_rate = rk3399_pmuclk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c\nindex d58557ff56de..f81ff829db9d 100644\n--- a/drivers/clk/rockchip/clk_rk3528.c\n+++ b/drivers/clk/rockchip/clk_rk3528.c\n@@ -1545,9 +1545,9 @@ static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn ret;\n };\n \n-static struct clk_ops rk3528_clk_ops = {\n+static struct clk_ops_uboot rk3528_clk_ops = {\n \t.get_rate = rk3528_clk_get_rate,\n \t.set_rate = rk3528_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c\nindex 533031caead6..e07838e2c82b 100644\n--- a/drivers/clk/rockchip/clk_rk3568.c\n+++ b/drivers/clk/rockchip/clk_rk3568.c\n@@ -458,9 +458,9 @@ static int rk3568_pmuclk_set_parent(struct clk *clk, struct clk *parent)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static struct clk_ops rk3568_pmuclk_ops = {\n+static struct clk_ops_uboot rk3568_pmuclk_ops = {\n \t.get_rate = rk3568_pmuclk_get_rate,\n \t.set_rate = rk3568_pmuclk_set_rate,\n \t.set_parent = rk3568_pmuclk_set_parent,\n };\n@@ -2855,9 +2855,9 @@ static int rk3568_clk_set_parent(struct clk *clk, struct clk *parent)\n \treturn 0;\n }\n #endif\n \n-static struct clk_ops rk3568_clk_ops = {\n+static struct clk_ops_uboot rk3568_clk_ops = {\n \t.get_rate = rk3568_clk_get_rate,\n \t.set_rate = rk3568_clk_set_rate,\n #if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))\n \t.set_parent = rk3568_clk_set_parent,\ndiff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c\nindex 125b08ee8322..60dc576bed4a 100644\n--- a/drivers/clk/rockchip/clk_rk3576.c\n+++ b/drivers/clk/rockchip/clk_rk3576.c\n@@ -2355,9 +2355,9 @@ static int rk3576_clk_set_parent(struct clk *clk, struct clk *parent)\n \treturn 0;\n }\n #endif\n \n-static struct clk_ops rk3576_clk_ops = {\n+static struct clk_ops_uboot rk3576_clk_ops = {\n \t.get_rate = rk3576_clk_get_rate,\n \t.set_rate = rk3576_clk_set_rate,\n #if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))\n \t.set_parent = rk3576_clk_set_parent,\ndiff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c\nindex 8c3a113526f9..3047f1630bcc 100644\n--- a/drivers/clk/rockchip/clk_rk3588.c\n+++ b/drivers/clk/rockchip/clk_rk3588.c\n@@ -1911,9 +1911,9 @@ static int rk3588_clk_set_parent(struct clk *clk, struct clk *parent)\n \treturn 0;\n }\n #endif\n \n-static struct clk_ops rk3588_clk_ops = {\n+static struct clk_ops_uboot rk3588_clk_ops = {\n \t.get_rate = rk3588_clk_get_rate,\n \t.set_rate = rk3588_clk_set_rate,\n #if (CONFIG_IS_ENABLED(OF_CONTROL)) || (!CONFIG_IS_ENABLED(OF_PLATDATA))\n \t.set_parent = rk3588_clk_set_parent,\n@@ -2139,9 +2139,9 @@ static int rk3588_scru_clk_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static const struct clk_ops rk3588_scru_clk_ops = {\n+static const struct clk_ops_uboot rk3588_scru_clk_ops = {\n \t.get_rate = rk3588_scru_clk_get_rate,\n \t.set_rate = rk3588_scru_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c\nindex 75202a66aa68..98e226ec61a0 100644\n--- a/drivers/clk/rockchip/clk_rv1108.c\n+++ b/drivers/clk/rockchip/clk_rv1108.c\n@@ -624,9 +624,9 @@ static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn new_rate;\n }\n \n-static const struct clk_ops rv1108_clk_ops = {\n+static const struct clk_ops_uboot rv1108_clk_ops = {\n \t.get_rate\t= rv1108_clk_get_rate,\n \t.set_rate\t= rv1108_clk_set_rate,\n };\n \ndiff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c\nindex aeeea9569147..caa1512719eb 100644\n--- a/drivers/clk/rockchip/clk_rv1126.c\n+++ b/drivers/clk/rockchip/clk_rv1126.c\n@@ -470,9 +470,9 @@ static int rv1126_pmuclk_set_parent(struct clk *clk, struct clk *parent)\n \t\treturn -ENOENT;\n \t}\n }\n \n-static struct clk_ops rv1126_pmuclk_ops = {\n+static struct clk_ops_uboot rv1126_pmuclk_ops = {\n \t.get_rate = rv1126_pmuclk_get_rate,\n \t.set_rate = rv1126_pmuclk_set_rate,\n \t.set_parent = rv1126_pmuclk_set_parent,\n };\n@@ -1699,9 +1699,9 @@ static int rv1126_clk_set_parent(struct clk *clk, struct clk *parent)\n \treturn 0;\n }\n #endif\n \n-static struct clk_ops rv1126_clk_ops = {\n+static struct clk_ops_uboot rv1126_clk_ops = {\n \t.get_rate = rv1126_clk_get_rate,\n \t.set_rate = rv1126_clk_set_rate,\n #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)\n \t.set_parent = rv1126_clk_set_parent,\ndiff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c\nindex de55504b5c90..dc84d4b6386d 100644\n--- a/drivers/clk/sifive/sifive-prci.c\n+++ b/drivers/clk/sifive/sifive-prci.c\n@@ -701,9 +701,9 @@ static int sifive_prci_probe(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops sifive_prci_ops = {\n+static struct clk_ops_uboot sifive_prci_ops = {\n \t.set_rate = sifive_prci_set_rate,\n \t.get_rate = sifive_prci_get_rate,\n \t.enable = sifive_prci_enable,\n \t.disable = sifive_prci_disable,\ndiff --git a/drivers/clk/sophgo/clk-cv1800b.c b/drivers/clk/sophgo/clk-cv1800b.c\nindex d946ea57a460..c8e5f7f53ea2 100644\n--- a/drivers/clk/sophgo/clk-cv1800b.c\n+++ b/drivers/clk/sophgo/clk-cv1800b.c\n@@ -730,9 +730,9 @@ static int cv1800b_clk_set_parent(struct clk *clk, struct clk *parent)\n \t\treturn err;\n \treturn clk_set_parent(c, p);\n }\n \n-const struct clk_ops cv1800b_clk_ops = {\n+const struct clk_ops_uboot cv1800b_clk_ops = {\n \t.enable = cv1800b_clk_enable,\n \t.disable = cv1800b_clk_disable,\n \t.get_rate = cv1800b_clk_get_rate,\n \t.set_rate = cv1800b_clk_set_rate,\ndiff --git a/drivers/clk/sophgo/clk-ip.c b/drivers/clk/sophgo/clk-ip.c\nindex d571fa671b08..7ac631126721 100644\n--- a/drivers/clk/sophgo/clk-ip.c\n+++ b/drivers/clk/sophgo/clk-ip.c\n@@ -47,9 +47,9 @@ static ulong gate_get_rate(struct clk *clk)\n {\n \treturn clk_get_parent_rate(clk);\n }\n \n-const struct clk_ops cv1800b_clk_gate_ops = {\n+const struct clk_ops_uboot cv1800b_clk_gate_ops = {\n \t.disable = gate_disable,\n \t.enable = gate_enable,\n \t.get_rate = gate_get_rate,\n };\n@@ -109,9 +109,9 @@ static ulong div_set_rate(struct clk *clk, ulong rate)\n \n \treturn DIV_ROUND_UP_ULL(parent_rate, val);\n }\n \n-const struct clk_ops cv1800b_clk_div_ops = {\n+const struct clk_ops_uboot cv1800b_clk_div_ops = {\n \t.disable = div_disable,\n \t.enable = div_enable,\n \t.get_rate = div_get_rate,\n \t.set_rate = div_set_rate,\n@@ -162,9 +162,9 @@ static int bypass_div_set_parent(struct clk *clk, struct clk *pclk)\n \tcv1800b_clk_clrbit(div->div.base, &div->bypass);\n \treturn 0;\n }\n \n-const struct clk_ops cv1800b_clk_bypass_div_ops = {\n+const struct clk_ops_uboot cv1800b_clk_bypass_div_ops = {\n \t.disable = div_disable,\n \t.enable = div_enable,\n \t.get_rate = bypass_div_get_rate,\n \t.set_rate = bypass_div_set_rate,\n@@ -202,9 +202,9 @@ static ulong fixed_div_get_rate(struct clk *clk)\n \n \treturn DIV_ROUND_UP_ULL(clk_get_parent_rate(clk), div->div);\n }\n \n-const struct clk_ops cv1800b_clk_fixed_div_ops = {\n+const struct clk_ops_uboot cv1800b_clk_fixed_div_ops = {\n \t.disable = fixed_div_disable,\n \t.enable = fixed_div_enable,\n \t.get_rate = fixed_div_get_rate,\n };\n@@ -246,9 +246,9 @@ static int bypass_fixed_div_set_parent(struct clk *clk, struct clk *pclk)\n \tcv1800b_clk_clrbit(div->div.base, &div->bypass);\n \treturn 0;\n }\n \n-const struct clk_ops cv1800b_clk_bypass_fixed_div_ops = {\n+const struct clk_ops_uboot cv1800b_clk_bypass_fixed_div_ops = {\n \t.disable = fixed_div_disable,\n \t.enable = fixed_div_enable,\n \t.get_rate = bypass_fixed_div_get_rate,\n \t.set_parent = bypass_fixed_div_set_parent,\n@@ -319,9 +319,9 @@ static int mux_set_parent(struct clk *clk, struct clk *pclk)\n \tcv1800b_clk_setfield(mux->base, &mux->mux, index);\n \treturn 0;\n }\n \n-const struct clk_ops cv1800b_clk_mux_ops = {\n+const struct clk_ops_uboot cv1800b_clk_mux_ops = {\n \t.disable = mux_disable,\n \t.enable = mux_enable,\n \t.get_rate = mux_get_rate,\n \t.set_rate = mux_set_rate,\n@@ -377,9 +377,9 @@ static int bypass_mux_set_parent(struct clk *clk, struct clk *pclk)\n \tcv1800b_clk_setfield(mux->mux.base, &mux->mux.mux, index);\n \treturn 0;\n }\n \n-const struct clk_ops cv1800b_clk_bypass_mux_ops = {\n+const struct clk_ops_uboot cv1800b_clk_bypass_mux_ops = {\n \t.disable = mux_disable,\n \t.enable = mux_enable,\n \t.get_rate = bypass_mux_get_rate,\n \t.set_rate = bypass_mux_set_rate,\n@@ -488,9 +488,9 @@ static int mmux_set_parent(struct clk *clk, struct clk *pclk)\n \tcv1800b_clk_setfield(mmux->base, &mmux->mux[clk_sel], index);\n \treturn 0;\n }\n \n-const struct clk_ops cv1800b_clk_mmux_ops = {\n+const struct clk_ops_uboot cv1800b_clk_mmux_ops = {\n \t.disable = mmux_disable,\n \t.enable = mmux_enable,\n \t.get_rate = mmux_get_rate,\n \t.set_rate = mmux_set_rate,\n@@ -578,9 +578,9 @@ static ulong aclk_set_rate(struct clk *clk, ulong rate)\n \n \treturn DIV_ROUND_UP_ULL(parent_rate * n, m * 2);\n }\n \n-const struct clk_ops cv1800b_clk_audio_ops = {\n+const struct clk_ops_uboot cv1800b_clk_audio_ops = {\n \t.disable = aclk_disable,\n \t.enable = aclk_enable,\n \t.get_rate = aclk_get_rate,\n \t.set_rate = aclk_set_rate,\ndiff --git a/drivers/clk/sophgo/clk-ip.h b/drivers/clk/sophgo/clk-ip.h\nindex 09d15d86dc9a..b2ad044523c8 100644\n--- a/drivers/clk/sophgo/clk-ip.h\n+++ b/drivers/clk/sophgo/clk-ip.h\n@@ -274,15 +274,15 @@ struct cv1800b_clk_audio {\n \t\t.n = CV1800B_CLK_REGFIELD(_n_offset, _n_shift,\t\t\\\n \t\t\t\t\t _n_width),\t\t\t\\\n \t}\n \n-extern const struct clk_ops cv1800b_clk_gate_ops;\n-extern const struct clk_ops cv1800b_clk_div_ops;\n-extern const struct clk_ops cv1800b_clk_bypass_div_ops;\n-extern const struct clk_ops cv1800b_clk_fixed_div_ops;\n-extern const struct clk_ops cv1800b_clk_bypass_fixed_div_ops;\n-extern const struct clk_ops cv1800b_clk_mux_ops;\n-extern const struct clk_ops cv1800b_clk_bypass_mux_ops;\n-extern const struct clk_ops cv1800b_clk_mmux_ops;\n-extern const struct clk_ops cv1800b_clk_audio_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_gate_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_div_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_bypass_div_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_fixed_div_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_bypass_fixed_div_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_mux_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_bypass_mux_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_mmux_ops;\n+extern const struct clk_ops_uboot cv1800b_clk_audio_ops;\n \n #endif /* __CLK_SOPHGO_IP_H__ */\ndiff --git a/drivers/clk/sophgo/clk-pll.c b/drivers/clk/sophgo/clk-pll.c\nindex c99aa0b4e440..6ef50f00171d 100644\n--- a/drivers/clk/sophgo/clk-pll.c\n+++ b/drivers/clk/sophgo/clk-pll.c\n@@ -111,9 +111,9 @@ static ulong cv1800b_ipll_set_rate(struct clk *clk, ulong rate)\n \n \treturn -EINVAL;\n }\n \n-const struct clk_ops cv1800b_ipll_ops = {\n+const struct clk_ops_uboot cv1800b_ipll_ops = {\n \t.enable = cv1800b_ipll_enable,\n \t.disable = cv1800b_ipll_disable,\n \t.get_rate = cv1800b_ipll_get_rate,\n \t.set_rate = cv1800b_ipll_set_rate,\n@@ -258,9 +258,9 @@ static int cv1800b_fpll_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-const struct clk_ops cv1800b_fpll_ops = {\n+const struct clk_ops_uboot cv1800b_fpll_ops = {\n \t.enable = cv1800b_ipll_enable,\n \t.disable = cv1800b_ipll_disable,\n \t.get_rate = cv1800b_fpll_get_rate,\n \t.set_rate = cv1800b_fpll_set_rate,\ndiff --git a/drivers/clk/sophgo/clk-pll.h b/drivers/clk/sophgo/clk-pll.h\nindex bea9bd8a4370..382209fd0e2e 100644\n--- a/drivers/clk/sophgo/clk-pll.h\n+++ b/drivers/clk/sophgo/clk-pll.h\n@@ -67,8 +67,8 @@ struct cv1800b_clk_fpll {\n \t\t\t.set = _syn_set_offset,\t\t\t\t\t\\\n \t\t},\t\t\t\t\t\t\t\t\\\n \t}\n \n-extern const struct clk_ops cv1800b_ipll_ops;\n-extern const struct clk_ops cv1800b_fpll_ops;\n+extern const struct clk_ops_uboot cv1800b_ipll_ops;\n+extern const struct clk_ops_uboot cv1800b_fpll_ops;\n \n #endif /* __clk_SOPHGO_PLL_H__ */\ndiff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c\nindex f8af17227c50..d12dec9a1f86 100644\n--- a/drivers/clk/starfive/clk-jh7110-pll.c\n+++ b/drivers/clk/starfive/clk-jh7110-pll.c\n@@ -313,9 +313,9 @@ static ulong jh7110_pllx_set_rate(struct clk *clk, ulong drate)\n \n \treturn jh7110_pllx_recalc_rate(clk);\n }\n \n-static const struct clk_ops jh7110_clk_pllx_ops = {\n+static const struct clk_ops_uboot jh7110_clk_pllx_ops = {\n \t.set_rate\t= jh7110_pllx_set_rate,\n \t.get_rate\t= jh7110_pllx_recalc_rate,\n };\n \ndiff --git a/drivers/clk/starfive/clk.h b/drivers/clk/starfive/clk.h\nindex 9d20ed0bbaba..c0bb740f5e13 100644\n--- a/drivers/clk/starfive/clk.h\n+++ b/drivers/clk/starfive/clk.h\n@@ -10,9 +10,9 @@\n /* the number of fixed clocks in DTS */\n #define JH7110_EXTCLK_END\t12\n \n #define _JH7110_CLK_OPS(_name)\t\t\t\t\t\\\n-static const struct clk_ops jh7110_##_name##_clk_ops = {\t\\\n+static const struct clk_ops_uboot jh7110_##_name##_clk_ops = {\t\\\n \t.set_rate = ccf_clk_set_rate,\t\t\t\t\\\n \t.get_rate = ccf_clk_get_rate,\t\t\t\t\\\n \t.set_parent = ccf_clk_set_parent,\t\t\t\\\n \t.enable = ccf_clk_enable,\t\t\t\t\\\ndiff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c\nindex cd6bdee5412f..834f0d8379e3 100644\n--- a/drivers/clk/stm32/clk-stm32-core.c\n+++ b/drivers/clk/stm32/clk-stm32-core.c\n@@ -120,16 +120,16 @@ ulong clk_stm32_get_rate_by_index(struct udevice *dev, int index)\n \n \treturn 0;\n }\n \n-static const struct clk_ops *clk_dev_ops(struct udevice *dev)\n+static const struct clk_ops_uboot *clk_dev_ops(struct udevice *dev)\n {\n-\treturn (const struct clk_ops *)dev->driver->ops;\n+\treturn (const struct clk_ops_uboot *)dev->driver->ops;\n }\n \n static int stm32_clk_endisable(struct clk *clk, bool enable)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *c = NULL;\n \n \tif (!clk->id || clk_get_by_id(clk->id, &c))\n \t\treturn -ENOENT;\n@@ -152,9 +152,9 @@ static int stm32_clk_disable(struct clk *clk)\n }\n \n static ulong stm32_clk_get_rate(struct clk *clk)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *c = NULL;\n \n \tif (!clk->id || clk_get_by_id(clk->id, &c))\n \t\treturn -ENOENT;\n@@ -167,9 +167,9 @@ static ulong stm32_clk_get_rate(struct clk *clk)\n }\n \n static ulong stm32_clk_set_rate(struct clk *clk, unsigned long clk_rate)\n {\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tstruct clk *c = NULL;\n \n \tif (!clk->id || clk_get_by_id(clk->id, &c))\n \t\treturn -ENOENT;\n@@ -180,9 +180,9 @@ static ulong stm32_clk_set_rate(struct clk *clk, unsigned long clk_rate)\n \n \treturn ops->set_rate(c, clk_rate);\n }\n \n-const struct clk_ops stm32_clk_ops = {\n+const struct clk_ops_uboot stm32_clk_ops = {\n \t.enable = stm32_clk_enable,\n \t.disable = stm32_clk_disable,\n \t.get_rate = stm32_clk_get_rate,\n \t.set_rate = stm32_clk_set_rate,\n@@ -238,9 +238,9 @@ static int clk_stm32_gate_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops clk_stm32_gate_ops = {\n+static const struct clk_ops_uboot clk_stm32_gate_ops = {\n \t.enable = clk_stm32_gate_enable,\n \t.disable = clk_stm32_gate_disable,\n \t.get_rate = clk_generic_get_rate,\n };\n@@ -303,13 +303,13 @@ clk_stm32_register_composite(struct udevice *dev,\n \tstruct clk_mux *mux = NULL;\n \tstruct clk_stm32_gate *gate = NULL;\n \tstruct clk_divider *div = NULL;\n \tstruct clk *mux_clk = NULL;\n-\tconst struct clk_ops *mux_ops = NULL;\n+\tconst struct clk_ops_uboot *mux_ops = NULL;\n \tstruct clk *gate_clk = NULL;\n-\tconst struct clk_ops *gate_ops = NULL;\n+\tconst struct clk_ops_uboot *gate_ops = NULL;\n \tstruct clk *div_clk = NULL;\n-\tconst struct clk_ops *div_ops = NULL;\n+\tconst struct clk_ops_uboot *div_ops = NULL;\n \tstruct stm32mp_rcc_priv *priv = dev_get_priv(dev);\n \tconst struct clk_stm32_clock_data *data = priv->clock_data;\n \tint i, ret;\n \ndiff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h\nindex 3134e33aa6c3..789420d7844c 100644\n--- a/drivers/clk/stm32/clk-stm32-core.h\n+++ b/drivers/clk/stm32/clk-stm32-core.h\n@@ -287,7 +287,7 @@ struct stm32_clk_composite_cfg {\n \t}, \\\n \t.setup\t\t= clk_stm32_register_composite, \\\n }\n \n-extern const struct clk_ops stm32_clk_ops;\n+extern const struct clk_ops_uboot stm32_clk_ops;\n \n ulong clk_stm32_get_rate_by_index(struct udevice *dev, int index);\ndiff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c\nindex fceb3c44b94e..6c3a369797d9 100644\n--- a/drivers/clk/stm32/clk-stm32f.c\n+++ b/drivers/clk/stm32/clk-stm32f.c\n@@ -716,9 +716,9 @@ static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)\n \n \treturn 0;\n }\n \n-static struct clk_ops stm32_clk_ops = {\n+static struct clk_ops_uboot stm32_clk_ops = {\n \t.of_xlate\t= stm32_clk_of_xlate,\n \t.enable\t\t= stm32_clk_enable,\n \t.get_rate\t= stm32_clk_get_rate,\n \t.set_rate\t= stm32_set_rate,\ndiff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c\nindex df82db69738a..611c7e4fb4af 100644\n--- a/drivers/clk/stm32/clk-stm32h7.c\n+++ b/drivers/clk/stm32/clk-stm32h7.c\n@@ -869,9 +869,9 @@ static int stm32_clk_of_xlate(struct clk *clk,\n \n \treturn 0;\n }\n \n-static struct clk_ops stm32_clk_ops = {\n+static struct clk_ops_uboot stm32_clk_ops = {\n \t.of_xlate\t= stm32_clk_of_xlate,\n \t.enable\t\t= stm32_clk_enable,\n \t.get_rate\t= stm32_clk_get_rate,\n };\ndiff --git a/drivers/clk/stm32/clk-stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c\nindex 823ce132d0b0..a7d0b55e060b 100644\n--- a/drivers/clk/stm32/clk-stm32mp1.c\n+++ b/drivers/clk/stm32/clk-stm32mp1.c\n@@ -2309,9 +2309,9 @@ static int stm32mp1_clk_probe(struct udevice *dev)\n \n \treturn result;\n }\n \n-static const struct clk_ops stm32mp1_clk_ops = {\n+static const struct clk_ops_uboot stm32mp1_clk_ops = {\n \t.enable = stm32mp1_clk_enable,\n \t.disable = stm32mp1_clk_disable,\n \t.get_rate = stm32mp1_clk_get_rate,\n \t.set_rate = stm32mp1_clk_set_rate,\ndiff --git a/drivers/clk/sunxi/clk_sun6i_rtc.c b/drivers/clk/sunxi/clk_sun6i_rtc.c\nindex 697b187a8235..a60e88500413 100644\n--- a/drivers/clk/sunxi/clk_sun6i_rtc.c\n+++ b/drivers/clk/sunxi/clk_sun6i_rtc.c\n@@ -11,9 +11,9 @@ static int clk_sun6i_rtc_enable(struct clk *clk)\n {\n \treturn 0;\n }\n \n-static const struct clk_ops clk_sun6i_rtc_ops = {\n+static const struct clk_ops_uboot clk_sun6i_rtc_ops = {\n \t.enable = clk_sun6i_rtc_enable,\n };\n \n static const struct udevice_id sun6i_rtc_ids[] = {\ndiff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c\nindex 842a0541bd60..315679f63a6a 100644\n--- a/drivers/clk/sunxi/clk_sunxi.c\n+++ b/drivers/clk/sunxi/clk_sunxi.c\n@@ -63,9 +63,9 @@ static int sunxi_clk_disable(struct clk *clk)\n {\n \treturn sunxi_set_gate(clk, false);\n }\n \n-struct clk_ops sunxi_clk_ops = {\n+struct clk_ops_uboot sunxi_clk_ops = {\n \t.enable = sunxi_clk_enable,\n \t.disable = sunxi_clk_disable,\n };\n \ndiff --git a/drivers/clk/tegra/tegra-car-clk.c b/drivers/clk/tegra/tegra-car-clk.c\nindex 880dd4f6ece9..6e315f502aa5 100644\n--- a/drivers/clk/tegra/tegra-car-clk.c\n+++ b/drivers/clk/tegra/tegra-car-clk.c\n@@ -99,9 +99,9 @@ static int tegra_car_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops tegra_car_clk_ops = {\n+static struct clk_ops_uboot tegra_car_clk_ops = {\n \t.request = tegra_car_clk_request,\n \t.get_rate = tegra_car_clk_get_rate,\n \t.set_rate = tegra_car_clk_set_rate,\n \t.enable = tegra_car_clk_enable,\ndiff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c\nindex ec52326c3b36..99e0a9f28d9c 100644\n--- a/drivers/clk/tegra/tegra186-clk.c\n+++ b/drivers/clk/tegra/tegra186-clk.c\n@@ -80,9 +80,9 @@ static int tegra186_clk_disable(struct clk *clk)\n \n \treturn tegra186_clk_en_dis(clk, CMD_CLK_DISABLE);\n }\n \n-static struct clk_ops tegra186_clk_ops = {\n+static struct clk_ops_uboot tegra186_clk_ops = {\n \t.get_rate = tegra186_clk_get_rate,\n \t.set_rate = tegra186_clk_set_rate,\n \t.enable = tegra186_clk_enable,\n \t.disable = tegra186_clk_disable,\ndiff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th1520-ap.c\nindex 6899e1b595a7..16188d56f73a 100644\n--- a/drivers/clk/thead/clk-th1520-ap.c\n+++ b/drivers/clk/thead/clk-th1520-ap.c\n@@ -223,9 +223,9 @@ static int ccu_div_enable(struct clk *clk)\n \n \treturn ccu_enable_helper(&cd->common, cd->enable);\n }\n \n-static const struct clk_ops ccu_div_ops = {\n+static const struct clk_ops_uboot ccu_div_ops = {\n \t.disable\t= ccu_div_disable,\n \t.enable\t\t= ccu_div_enable,\n \t.set_parent\t= ccu_div_set_parent,\n \t.get_rate\t= ccu_div_get_rate,\n@@ -294,9 +294,9 @@ static unsigned long ccu_pll_get_rate(struct clk *clk)\n \n \treturn rate;\n }\n \n-static const struct clk_ops clk_pll_ops = {\n+static const struct clk_ops_uboot clk_pll_ops = {\n \t.get_rate\t= ccu_pll_get_rate,\n };\n \n U_BOOT_DRIVER(th1520_clk_pll) = {\n@@ -1017,9 +1017,9 @@ static int th1520_clk_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn clk_set_parent(c, p);\n }\n \n-static const struct clk_ops th1520_clk_ops = {\n+static const struct clk_ops_uboot th1520_clk_ops = {\n \t.enable\t\t= th1520_clk_enable,\n \t.disable\t= th1520_clk_disable,\n \t.get_rate\t= th1520_clk_get_rate,\n \t.set_rate\t= th1520_clk_set_rate,\ndiff --git a/drivers/clk/ti/clk-am3-dpll-x2.c b/drivers/clk/ti/clk-am3-dpll-x2.c\nindex 1b0b9818cdd4..cd864c47f004 100644\n--- a/drivers/clk/ti/clk-am3-dpll-x2.c\n+++ b/drivers/clk/ti/clk-am3-dpll-x2.c\n@@ -29,9 +29,9 @@ static ulong clk_ti_am3_dpll_x2_get_rate(struct clk *clk)\n \tdev_dbg(clk->dev, \"rate=%ld\\n\", rate);\n \treturn rate;\n }\n \n-const struct clk_ops clk_ti_am3_dpll_x2_ops = {\n+const struct clk_ops_uboot clk_ti_am3_dpll_x2_ops = {\n \t.get_rate = clk_ti_am3_dpll_x2_get_rate,\n };\n \n static int clk_ti_am3_dpll_x2_remove(struct udevice *dev)\ndiff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c\nindex 21ec01f8dd9a..1726233df173 100644\n--- a/drivers/clk/ti/clk-am3-dpll.c\n+++ b/drivers/clk/ti/clk-am3-dpll.c\n@@ -274,9 +274,9 @@ static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)\n \tdev_dbg(clk->dev, \"rate=%lld\\n\", rate);\n \treturn rate;\n }\n \n-const struct clk_ops clk_ti_am3_dpll_ops = {\n+const struct clk_ops_uboot clk_ti_am3_dpll_ops = {\n \t.round_rate = clk_ti_am3_dpll_round_rate,\n \t.get_rate = clk_ti_am3_dpll_get_rate,\n \t.set_rate = clk_ti_am3_dpll_set_rate,\n };\ndiff --git a/drivers/clk/ti/clk-ctrl.c b/drivers/clk/ti/clk-ctrl.c\nindex c5c97dc35c4d..8e8bb60d91bf 100644\n--- a/drivers/clk/ti/clk-ctrl.c\n+++ b/drivers/clk/ti/clk-ctrl.c\n@@ -131,9 +131,9 @@ static int clk_ti_ctrl_of_to_plat(struct udevice *dev)\n \n \treturn 0;\n }\n \n-static struct clk_ops clk_ti_ctrl_ops = {\n+static struct clk_ops_uboot clk_ti_ctrl_ops = {\n \t.of_xlate = clk_ti_ctrl_of_xlate,\n \t.enable = clk_ti_ctrl_enable,\n \t.disable = clk_ti_ctrl_disable,\n \t.get_rate = clk_ti_ctrl_get_rate,\ndiff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c\nindex 40a742d7fdc4..f959b5633d64 100644\n--- a/drivers/clk/ti/clk-divider.c\n+++ b/drivers/clk/ti/clk-divider.c\n@@ -242,9 +242,9 @@ static int clk_ti_divider_request(struct clk *clk)\n \tclk->flags = priv->flags;\n \treturn 0;\n }\n \n-const struct clk_ops clk_ti_divider_ops = {\n+const struct clk_ops_uboot clk_ti_divider_ops = {\n \t.request = clk_ti_divider_request,\n \t.round_rate = clk_ti_divider_round_rate,\n \t.get_rate = clk_ti_divider_get_rate,\n \t.set_rate = clk_ti_divider_set_rate\ndiff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c\nindex 873ceb8a2ab7..fb0ccf480dee 100644\n--- a/drivers/clk/ti/clk-gate.c\n+++ b/drivers/clk/ti/clk-gate.c\n@@ -72,9 +72,9 @@ static int clk_ti_gate_of_to_plat(struct udevice *dev)\n \tpriv->invert_enable = dev_read_bool(dev, \"ti,set-bit-to-disable\");\n \treturn 0;\n }\n \n-static struct clk_ops clk_ti_gate_ops = {\n+static struct clk_ops_uboot clk_ti_gate_ops = {\n \t.enable = clk_ti_gate_enable,\n \t.disable = clk_ti_gate_disable,\n };\n \ndiff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c\nindex b775bd55faab..9766f50a2e4d 100644\n--- a/drivers/clk/ti/clk-k3-pll.c\n+++ b/drivers/clk/ti/clk-k3-pll.c\n@@ -498,9 +498,9 @@ static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)\n }\n \n \n \n-static const struct clk_ops ti_pll_clk_ops = {\n+static const struct clk_ops_uboot ti_pll_clk_ops = {\n \t.get_rate = ti_pll_clk_get_rate,\n \t.set_rate = ti_pll_clk_set_rate,\n \t.enable = ti_pll_clk_enable,\n \t.disable = ti_pll_clk_disable,\ndiff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c\nindex b38e559e45a6..cb7e016c637a 100644\n--- a/drivers/clk/ti/clk-k3.c\n+++ b/drivers/clk/ti/clk-k3.c\n@@ -263,9 +263,9 @@ static ulong ti_clk_set_rate(struct clk *clk, ulong rate)\n \tstruct ti_clk_data *data = dev_get_priv(clk->dev);\n \tstruct clk *clkp = data->map[clk->id].clk;\n \tint div = 1;\n \tulong child_rate;\n-\tconst struct clk_ops *ops;\n+\tconst struct clk_ops_uboot *ops;\n \tulong new_rate, rem;\n \tulong diff, new_diff;\n \tint freq_scale_up = rate >= ti_clk_get_rate(clk) ? 1 : 0;\n \n@@ -404,9 +404,9 @@ static const struct udevice_id ti_clk_of_match[] = {\n \t{ .compatible = \"ti,k2g-sci-clk\" },\n \t{ /* sentinel */ },\n };\n \n-static const struct clk_ops ti_clk_ops = {\n+static const struct clk_ops_uboot ti_clk_ops = {\n \t.of_xlate = ti_clk_of_xlate,\n \t.set_rate = ti_clk_set_rate,\n \t.get_rate = ti_clk_get_rate,\n \t.enable = ti_clk_enable,\ndiff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c\nindex db5393414318..60bdde35e510 100644\n--- a/drivers/clk/ti/clk-mux.c\n+++ b/drivers/clk/ti/clk-mux.c\n@@ -170,9 +170,9 @@ static int clk_ti_mux_request(struct clk *clk)\n \n \treturn clk_ti_mux_set_parent(clk, parent);\n }\n \n-static struct clk_ops clk_ti_mux_ops = {\n+static struct clk_ops_uboot clk_ti_mux_ops = {\n \t.request = clk_ti_mux_request,\n \t.round_rate = clk_ti_mux_round_rate,\n \t.get_rate = clk_ti_mux_get_rate,\n \t.set_rate = clk_ti_mux_set_rate,\ndiff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c\nindex e374bd3bcc20..fdf49a759983 100644\n--- a/drivers/clk/ti/clk-sci.c\n+++ b/drivers/clk/ti/clk-sci.c\n@@ -195,9 +195,9 @@ static const struct udevice_id ti_sci_clk_of_match[] = {\n \t{ .compatible = \"ti,k2g-sci-clk\" },\n \t{ /* sentinel */ },\n };\n \n-static struct clk_ops ti_sci_clk_ops = {\n+static struct clk_ops_uboot ti_sci_clk_ops = {\n \t.of_xlate = ti_sci_clk_of_xlate,\n \t.get_rate = ti_sci_clk_get_rate,\n \t.set_rate = ti_sci_clk_set_rate,\n \t.set_parent = ti_sci_clk_set_parent,\ndiff --git a/drivers/clk/uccf/clk-composite.c b/drivers/clk/uccf/clk-composite.c\nindex 207224b13208..0fdc8c2e6fec 100644\n--- a/drivers/clk/uccf/clk-composite.c\n+++ b/drivers/clk/uccf/clk-composite.c\n@@ -35,9 +35,9 @@ static u8 clk_composite_get_parent(struct clk *clk)\n static int clk_composite_set_parent(struct clk *clk, struct clk *parent)\n {\n \tstruct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?\n \t\t(struct clk *)dev_get_clk_ptr(clk->dev) : clk);\n-\tconst struct clk_ops *mux_ops = composite->mux_ops;\n+\tconst struct clk_ops_uboot *mux_ops = composite->mux_ops;\n \tstruct clk *mux = composite->mux;\n \n \tif (!mux || !mux_ops)\n \t\treturn -ENOSYS;\n@@ -48,9 +48,9 @@ static int clk_composite_set_parent(struct clk *clk, struct clk *parent)\n static unsigned long clk_composite_recalc_rate(struct clk *clk)\n {\n \tstruct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?\n \t\t(struct clk *)dev_get_clk_ptr(clk->dev) : clk);\n-\tconst struct clk_ops *rate_ops = composite->rate_ops;\n+\tconst struct clk_ops_uboot *rate_ops = composite->rate_ops;\n \tstruct clk *rate = composite->rate;\n \n \tif (rate && rate_ops)\n \t\treturn rate_ops->get_rate(rate);\n@@ -61,9 +61,9 @@ static unsigned long clk_composite_recalc_rate(struct clk *clk)\n static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)\n {\n \tstruct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?\n \t\t(struct clk *)dev_get_clk_ptr(clk->dev) : clk);\n-\tconst struct clk_ops *rate_ops = composite->rate_ops;\n+\tconst struct clk_ops_uboot *rate_ops = composite->rate_ops;\n \tstruct clk *clk_rate = composite->rate;\n \n \tif (rate && rate_ops && rate_ops->set_rate)\n \t\treturn rate_ops->set_rate(clk_rate, rate);\n@@ -74,9 +74,9 @@ static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)\n static int clk_composite_enable(struct clk *clk)\n {\n \tstruct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?\n \t\t(struct clk *)dev_get_clk_ptr(clk->dev) : clk);\n-\tconst struct clk_ops *gate_ops = composite->gate_ops;\n+\tconst struct clk_ops_uboot *gate_ops = composite->gate_ops;\n \tstruct clk *gate = composite->gate;\n \n \tif (gate && gate_ops)\n \t\treturn gate_ops->enable(gate);\n@@ -87,9 +87,9 @@ static int clk_composite_enable(struct clk *clk)\n static int clk_composite_disable(struct clk *clk)\n {\n \tstruct clk_composite *composite = to_clk_composite(clk_dev_binded(clk) ?\n \t\t(struct clk *)dev_get_clk_ptr(clk->dev) : clk);\n-\tconst struct clk_ops *gate_ops = composite->gate_ops;\n+\tconst struct clk_ops_uboot *gate_ops = composite->gate_ops;\n \tstruct clk *gate = composite->gate;\n \n \tif (gate && gate_ops)\n \t\treturn gate_ops->disable(gate);\n@@ -99,13 +99,13 @@ static int clk_composite_disable(struct clk *clk)\n \n struct clk *clk_register_composite(struct udevice *dev, const char *name,\n \t\t\t\t const char * const *parent_names,\n \t\t\t\t int num_parents, struct clk *mux,\n-\t\t\t\t const struct clk_ops *mux_ops,\n+\t\t\t\t const struct clk_ops_uboot *mux_ops,\n \t\t\t\t struct clk *rate,\n-\t\t\t\t const struct clk_ops *rate_ops,\n+\t\t\t\t const struct clk_ops_uboot *rate_ops,\n \t\t\t\t struct clk *gate,\n-\t\t\t\t const struct clk_ops *gate_ops,\n+\t\t\t\t const struct clk_ops_uboot *gate_ops,\n \t\t\t\t unsigned long flags)\n {\n \tstruct clk *clk;\n \tstruct clk_composite *composite;\n@@ -170,9 +170,9 @@ err:\n \tkfree(composite);\n \treturn clk;\n }\n \n-static const struct clk_ops clk_composite_ops = {\n+static const struct clk_ops_uboot clk_composite_ops = {\n \t.set_parent = clk_composite_set_parent,\n \t.get_rate = clk_composite_recalc_rate,\n \t.set_rate = clk_composite_set_rate,\n \t.enable = clk_composite_enable,\ndiff --git a/drivers/clk/uccf/clk-divider.c b/drivers/clk/uccf/clk-divider.c\nindex e692b9c2167d..8d65fd94c176 100644\n--- a/drivers/clk/uccf/clk-divider.c\n+++ b/drivers/clk/uccf/clk-divider.c\n@@ -177,9 +177,9 @@ static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)\n \n \treturn clk_get_rate(clk);\n }\n \n-const struct clk_ops clk_divider_ops = {\n+const struct clk_ops_uboot clk_divider_ops = {\n \t.get_rate = clk_divider_recalc_rate,\n \t.set_rate = clk_divider_set_rate,\n };\n \ndiff --git a/drivers/clk/uccf/clk-fixed-factor.c b/drivers/clk/uccf/clk-fixed-factor.c\nindex 4eb8be728e65..0fdfcdf2f90a 100644\n--- a/drivers/clk/uccf/clk-fixed-factor.c\n+++ b/drivers/clk/uccf/clk-fixed-factor.c\n@@ -32,9 +32,9 @@ static ulong clk_factor_recalc_rate(struct clk *clk)\n \tdo_div(rate, fix->div);\n \treturn (ulong)rate;\n }\n \n-const struct clk_ops ccf_clk_fixed_factor_ops = {\n+const struct clk_ops_uboot ccf_clk_fixed_factor_ops = {\n \t.get_rate = clk_factor_recalc_rate,\n };\n \n struct clk *clk_hw_register_fixed_factor(struct udevice *dev,\ndiff --git a/drivers/clk/uccf/clk-gate.c b/drivers/clk/uccf/clk-gate.c\nindex 256ff1089917..e5883aec2474 100644\n--- a/drivers/clk/uccf/clk-gate.c\n+++ b/drivers/clk/uccf/clk-gate.c\n@@ -110,9 +110,9 @@ int clk_gate_is_enabled(struct clk *clk)\n \n \treturn reg ? 1 : 0;\n }\n \n-const struct clk_ops clk_gate_ops = {\n+const struct clk_ops_uboot clk_gate_ops = {\n \t.enable = clk_gate_enable,\n \t.disable = clk_gate_disable,\n \t.get_rate = clk_generic_get_rate,\n };\ndiff --git a/drivers/clk/uccf/clk-mux.c b/drivers/clk/uccf/clk-mux.c\nindex d7411f8f2822..06836369be1d 100644\n--- a/drivers/clk/uccf/clk-mux.c\n+++ b/drivers/clk/uccf/clk-mux.c\n@@ -158,9 +158,9 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-const struct clk_ops clk_mux_ops = {\n+const struct clk_ops_uboot clk_mux_ops = {\n \t.get_rate = clk_generic_get_rate,\n \t.set_parent = clk_mux_set_parent,\n };\n \ndiff --git a/drivers/clk/uccf/clk.c b/drivers/clk/uccf/clk.c\nindex b8c2e8d531b9..f04b3b23dbd1 100644\n--- a/drivers/clk/uccf/clk.c\n+++ b/drivers/clk/uccf/clk.c\n@@ -132,9 +132,9 @@ int ccf_clk_disable(struct clk *clk)\n {\n \treturn ccf_clk_endisable(clk, false);\n }\n \n-const struct clk_ops ccf_clk_ops = {\n+const struct clk_ops_uboot ccf_clk_ops = {\n \t.set_rate = ccf_clk_set_rate,\n \t.get_rate = ccf_clk_get_rate,\n \t.set_parent = ccf_clk_set_parent,\n \t.enable = ccf_clk_enable,\ndiff --git a/drivers/clk/uccf/clk_sandbox_uccf.c b/drivers/clk/uccf/clk_sandbox_uccf.c\nindex 9c74ed940acd..9c7dc5007134 100644\n--- a/drivers/clk/uccf/clk_sandbox_uccf.c\n+++ b/drivers/clk/uccf/clk_sandbox_uccf.c\n@@ -46,9 +46,9 @@ static ulong clk_pllv3_get_rate(struct clk *clk)\n \n \treturn parent_rate * 24;\n }\n \n-static const struct clk_ops clk_pllv3_generic_ops = {\n+static const struct clk_ops_uboot clk_pllv3_generic_ops = {\n \t.get_rate = clk_pllv3_get_rate,\n };\n \n struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,\n@@ -106,9 +106,9 @@ static int clk_gate2_disable(struct clk *clk)\n \tgate->state = 0;\n \treturn 0;\n }\n \n-static const struct clk_ops clk_gate2_ops = {\n+static const struct clk_ops_uboot clk_gate2_ops = {\n \t.enable = clk_gate2_enable,\n \t.disable = clk_gate2_disable,\n \t.get_rate = clk_generic_get_rate,\n };\n@@ -160,9 +160,9 @@ static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)\n \treturn divider_recalc_rate(clk, parent_rate, val, divider->table,\n \t\t\t\t divider->flags, divider->width);\n }\n \n-static const struct clk_ops sandbox_clk_composite_divider_ops = {\n+static const struct clk_ops_uboot sandbox_clk_composite_divider_ops = {\n \t.get_rate = sandbox_clk_composite_divider_recalc_rate,\n };\n \n struct clk *sandbox_clk_composite(const char *name,\ndiff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c\nindex 33369c93916b..3a4c9f6687f7 100644\n--- a/drivers/clk/uniphier/clk-uniphier-core.c\n+++ b/drivers/clk/uniphier/clk-uniphier-core.c\n@@ -240,9 +240,9 @@ static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn __uniphier_clk_set_rate(priv, data, rate, true);\n }\n \n-static const struct clk_ops uniphier_clk_ops = {\n+static const struct clk_ops_uboot uniphier_clk_ops = {\n \t.enable = uniphier_clk_enable,\n \t.get_rate = uniphier_clk_get_rate,\n \t.set_rate = uniphier_clk_set_rate,\n };\ndiff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c\nindex bd7ab9d1b77e..5bc429511a1e 100644\n--- a/drivers/phy/cadence/phy-cadence-sierra.c\n+++ b/drivers/phy/cadence/phy-cadence-sierra.c\n@@ -554,9 +554,9 @@ static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn ret;\n }\n \n-static const struct clk_ops cdns_sierra_pll_mux_ops = {\n+static const struct clk_ops_uboot cdns_sierra_pll_mux_ops = {\n \t.set_parent = cdns_sierra_pll_mux_set_parent,\n };\n \n static int cdns_sierra_pll_mux_probe(struct udevice *dev)\ndiff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c\nindex 933533b2b0b7..9504b01375a1 100644\n--- a/drivers/phy/cadence/phy-cadence-torrent.c\n+++ b/drivers/phy/cadence/phy-cadence-torrent.c\n@@ -668,9 +668,9 @@ static int cdns_torrent_derived_refclk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops cdns_torrent_derived_refclk_ops = {\n+static const struct clk_ops_uboot cdns_torrent_derived_refclk_ops = {\n \t.of_xlate = cdns_torrent_derived_refclk_of_xlate,\n \t.enable = cdns_torrent_derived_refclk_enable,\n \t.disable = cdns_torrent_derived_refclk_disable,\n };\ndiff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c\nindex fcf8617ee9b3..d511b7c4285d 100644\n--- a/drivers/phy/phy-stm32-usbphyc.c\n+++ b/drivers/phy/phy-stm32-usbphyc.c\n@@ -683,9 +683,9 @@ static int stm32_usbphyc_clk48_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-const struct clk_ops usbphyc_clk48_ops = {\n+const struct clk_ops_uboot usbphyc_clk48_ops = {\n \t.get_rate = stm32_usbphyc_clk48_get_rate,\n \t.enable = stm32_usbphyc_clk48_enable,\n \t.disable = stm32_usbphyc_clk48_disable,\n };\ndiff --git a/drivers/phy/phy-ti-am654.c b/drivers/phy/phy-ti-am654.c\nindex c3d9972397aa..98362c59ac59 100644\n--- a/drivers/phy/phy-ti-am654.c\n+++ b/drivers/phy/phy-ti-am654.c\n@@ -176,9 +176,9 @@ static int serdes_am654_mux_clk_set_parent(struct clk *clk, struct clk *parent)\n \n \treturn 0;\n }\n \n-static struct clk_ops serdes_am654_mux_clk_ops = {\n+static struct clk_ops_uboot serdes_am654_mux_clk_ops = {\n \t.set_parent = serdes_am654_mux_clk_set_parent,\n };\n \n U_BOOT_DRIVER(serdes_am654_mux_clk) = {\ndiff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c\nindex 4ea6600ce7f5..66cc9c69b62d 100644\n--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c\n+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c\n@@ -246,9 +246,9 @@ int rockchip_usb2phy_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static struct clk_ops rockchip_usb2phy_clk_ops = {\n+static struct clk_ops_uboot rockchip_usb2phy_clk_ops = {\n \t.enable = rockchip_usb2phy_clk_enable,\n \t.disable = rockchip_usb2phy_clk_disable,\n \t.round_rate = rockchip_usb2phy_clk_round_rate\n };\ndiff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c\nindex 466e2a5d0b50..fb158072da0a 100644\n--- a/drivers/phy/ti/phy-j721e-wiz.c\n+++ b/drivers/phy/ti/phy-j721e-wiz.c\n@@ -400,9 +400,9 @@ static ulong wiz_div_clk_set_rate(struct clk *clk, ulong rate)\n \n \treturn parent_rate >> div;\n }\n \n-const struct clk_ops wiz_div_clk_ops = {\n+const struct clk_ops_uboot wiz_div_clk_ops = {\n \t.get_rate = wiz_div_clk_get_rate,\n \t.set_rate = wiz_div_clk_set_rate,\n };\n \n@@ -459,9 +459,9 @@ static int wiz_clk_xlate(struct clk *clk, struct ofnode_phandle_args *args)\n \n \treturn 0;\n }\n \n-static const struct clk_ops wiz_clk_mux_ops = {\n+static const struct clk_ops_uboot wiz_clk_mux_ops = {\n \t.set_parent = wiz_clk_mux_set_parent,\n \t.of_xlate = wiz_clk_xlate,\n };\n \n@@ -566,9 +566,9 @@ static int wiz_phy_en_refclk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops wiz_clk_ops = {\n+static const struct clk_ops_uboot wiz_clk_ops = {\n \t.set_parent = wiz_clk_set_parent,\n \t.of_xlate = wiz_clk_of_xlate,\n \t.enable = wiz_phy_en_refclk_enable,\n \t.disable = wiz_phy_en_refclk_disable,\ndiff --git a/drivers/power/domain/imx8mp-hsiomix.c b/drivers/power/domain/imx8mp-hsiomix.c\nindex 1ca43880ef56..145e98d122e7 100644\n--- a/drivers/power/domain/imx8mp-hsiomix.c\n+++ b/drivers/power/domain/imx8mp-hsiomix.c\n@@ -173,9 +173,9 @@ static int hsio_pll_clk_disable(struct clk *clk)\n \n \treturn 0;\n }\n \n-static const struct clk_ops hsio_pll_clk_ops = {\n+static const struct clk_ops_uboot hsio_pll_clk_ops = {\n \t.enable = hsio_pll_clk_enable,\n \t.disable = hsio_pll_clk_disable,\n };\n \ndiff --git a/include/clk-uclass.h b/include/clk-uclass.h\nindex 8c07e723cff6..a26603bf2f0a 100644\n--- a/include/clk-uclass.h\n+++ b/include/clk-uclass.h\n@@ -14,9 +14,9 @@\n \n struct ofnode_phandle_args;\n \n /**\n- * struct clk_ops - The functions that a clock driver must implement.\n+ * struct clk_ops_uboot - The functions that a clock driver must implement.\n * @of_xlate: Translate a client's device-tree (OF) clock specifier.\n * @request: Request a translated clock.\n * @round_rate: Adjust a rate to the exact rate a clock can provide.\n * @get_rate: Get current clock rate.\n@@ -27,9 +27,9 @@ struct ofnode_phandle_args;\n * @dump: Print clock information.\n *\n * The individual methods are described more fully below.\n */\n-struct clk_ops {\n+struct clk_ops_uboot {\n \tint (*of_xlate)(struct clk *clock,\n \t\t\tstruct ofnode_phandle_args *args);\n \tint (*request)(struct clk *clock);\n \tulong (*round_rate)(struct clk *clk, ulong rate);\ndiff --git a/include/clk/sunxi.h b/include/clk/sunxi.h\nindex c298195c51e6..3999d4e73ca3 100644\n--- a/include/clk/sunxi.h\n+++ b/include/clk/sunxi.h\n@@ -84,7 +84,7 @@ struct ccu_plat {\n \tvoid *base;\n \tconst struct ccu_desc *desc;\n };\n \n-extern struct clk_ops sunxi_clk_ops;\n+extern struct clk_ops_uboot sunxi_clk_ops;\n \n #endif /* _CLK_SUNXI_H */\ndiff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h\nindex 2d754fa42871..65f86421aa63 100644\n--- a/include/linux/clk-provider.h\n+++ b/include/linux/clk-provider.h\n@@ -78,9 +78,9 @@ struct clk_mux {\n \n };\n \n #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)\n-extern const struct clk_ops clk_mux_ops;\n+extern const struct clk_ops_uboot clk_mux_ops;\n u8 clk_mux_get_parent(struct clk *clk);\n int clk_mux_fetch_parent_index(struct clk *clk, struct clk *parent);\n \n /**\n@@ -110,9 +110,9 @@ struct clk_gate {\n \n #define CLK_GATE_SET_TO_DISABLE\t\tBIT(0)\n #define CLK_GATE_HIWORD_MASK\t\tBIT(1)\n \n-extern const struct clk_ops clk_gate_ops;\n+extern const struct clk_ops_uboot clk_gate_ops;\n struct clk *clk_register_gate(struct udevice *dev, const char *name,\n \t\t\t const char *parent_name, unsigned long flags,\n \t\t\t void __iomem *reg, u8 bit_idx,\n \t\t\t u8 clk_gate_flags, spinlock_t *lock);\n@@ -143,9 +143,9 @@ struct clk_divider {\n #define CLK_DIVIDER_HIWORD_MASK\t\tBIT(3)\n #define CLK_DIVIDER_ROUND_CLOSEST\tBIT(4)\n #define CLK_DIVIDER_READ_ONLY\t\tBIT(5)\n #define CLK_DIVIDER_MAX_AT_ZERO\t\tBIT(6)\n-extern const struct clk_ops clk_divider_ops;\n+extern const struct clk_ops_uboot clk_divider_ops;\n \n /**\n * clk_divider_get_table_div() - convert the register value to the divider\n *\n@@ -199,9 +199,9 @@ struct clk_fixed_factor {\n \tunsigned int\tmult;\n \tunsigned int\tdiv;\n };\n \n-extern const struct clk_ops clk_fixed_rate_ops;\n+extern const struct clk_ops_uboot clk_fixed_rate_ops;\n \n #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\\\n \t\t\t\t\t clk)\n \n@@ -216,28 +216,28 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,\n \t\t\t\t struct clk_fixed_rate *plat);\n \n struct clk_composite {\n \tstruct clk\tclk;\n-\tstruct clk_ops\tops;\n+\tstruct clk_ops_uboot\tops;\n \n \tstruct clk\t*mux;\n \tstruct clk\t*rate;\n \tstruct clk\t*gate;\n \n-\tconst struct clk_ops\t*mux_ops;\n-\tconst struct clk_ops\t*rate_ops;\n-\tconst struct clk_ops\t*gate_ops;\n+\tconst struct clk_ops_uboot\t*mux_ops;\n+\tconst struct clk_ops_uboot\t*rate_ops;\n+\tconst struct clk_ops_uboot\t*gate_ops;\n \n \tstruct udevice *dev;\n };\n \n #define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)\n \n struct clk *clk_register_composite(struct udevice *dev, const char *name,\n \t\tconst char * const *parent_names, int num_parents,\n-\t\tstruct clk *mux_clk, const struct clk_ops *mux_ops,\n-\t\tstruct clk *rate_clk, const struct clk_ops *rate_ops,\n-\t\tstruct clk *gate_clk, const struct clk_ops *gate_ops,\n+\t\tstruct clk *mux_clk, const struct clk_ops_uboot *mux_ops,\n+\t\tstruct clk *rate_clk, const struct clk_ops_uboot *rate_ops,\n+\t\tstruct clk *gate_clk, const struct clk_ops_uboot *gate_ops,\n \t\tunsigned long flags);\n \n int clk_register(struct clk *clk, const char *drv_name, const char *name,\n \t\t const char *parent_name);\n@@ -269,7 +269,7 @@ ulong ccf_clk_get_rate(struct clk *clk);\n ulong ccf_clk_set_rate(struct clk *clk, unsigned long rate);\n int ccf_clk_set_parent(struct clk *clk, struct clk *parent);\n int ccf_clk_enable(struct clk *clk);\n int ccf_clk_disable(struct clk *clk);\n-extern const struct clk_ops ccf_clk_ops;\n+extern const struct clk_ops_uboot ccf_clk_ops;\n \n #endif /* __LINUX_CLK_PROVIDER_H */\n", "prefixes": [ "v2", "3/7" ] }