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GET /api/patches/2218553/?format=api
{ "id": 2218553, "url": "http://patchwork.ozlabs.org/api/patches/2218553/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260401-hawi-pinctrl-v1-1-4718da24e531@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401-hawi-pinctrl-v1-1-4718da24e531@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T11:52:07", "name": "[1/2] dt-bindings: pinctrl: describe Hawi TLMM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7b4108d17426a39d45663808de35228c86201f54", "submitter": { "id": 89980, "url": "http://patchwork.ozlabs.org/api/people/89980/?format=api", "name": "Mukesh Ojha", "email": "mukesh.ojha@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260401-hawi-pinctrl-v1-1-4718da24e531@oss.qualcomm.com/mbox/", "series": [ { "id": 498325, "url": "http://patchwork.ozlabs.org/api/series/498325/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498325", "date": "2026-04-01T11:52:08", "name": "pinctrl: qcom: Introduce Pinctrl for Hawi", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498325/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218553/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218553/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34558-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=DArvxcAD;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=FsbBhQPv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260401-hawi-pinctrl-v1-1-4718da24e531@oss.qualcomm.com>", "References": "<20260401-hawi-pinctrl-v1-0-4718da24e531@oss.qualcomm.com>", "In-Reply-To": "<20260401-hawi-pinctrl-v1-0-4718da24e531@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>", "X-Mailer": "b4 0.14-dev-f7c49", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775044329; l=5116;\n i=mukesh.ojha@oss.qualcomm.com; s=20250708; h=from:subject:message-id;\n bh=DN2hdJkQfwOmkV73g25P6amt7YJJMBYy4ixSvMZeed0=;\n b=MvkLZJ7m5M1Y3895YsXu0qHuOgRR2PXaJKLD88QyTe5f3T16BTLu7qzFXL05VkVQkqaBFDUyu\n CFWZZrXOct3D7IzjwGoRnrWtKAAuSGO/1HX9ELKXzDVE+J38i1T/CZg", "X-Developer-Key": "i=mukesh.ojha@oss.qualcomm.com; a=ed25519;\n pk=eX8dr/7d4HJz/HEXZIpe3c+Ukopa/wZmxH+5YV3gdNc=", "X-Authority-Analysis": "v=2.4 cv=bfJmkePB c=1 sm=1 tr=0 ts=69cd06f2 cx=c_pps\n a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22\n a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=bT5XQOCXPleopHcqzpYA:9 a=QEXdDO2ut3YA:10\n a=2VI0MkxyNR6bbpdq8BZq:22 a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDEwOCBTYWx0ZWRfX3jbK/uEDp39/\n 715aN87XZIIMDSd3AHiDugyiNViUQw9cYyoPUzje9hHqTVJ3ybmTO1m9XGhcFP7ed6zKVbwj7DR\n FuUl8DlmFNxA2XK4ThphvYtiAFyTB202RhYHXRifJJcCiRRbFzSnO2gmH2GsM2vpgaoxg6jJGen\n DEpj/3bvGlCSnbl+mUQxclrm5FhfzOF6vQqXEEexufKko8L6AXlObcNVH+GdTh+WfrkpFrJm7q3\n Fk1WVnVXdthdur64X7wge2fPN5iIHxpiP5dBaEGERGuf9a2pFz2FdaGkxG0jTUYdj1lSuvrR6CQ\n 7DC+Bzo0axyqWCUb2JwYn9rNAp71QWPD4fhknsqUW9XQlO1AEB1ZJeIysaedJpBWWdslwpKwLOR\n X5LjIrq/mwRNkM1y+N5GO/FBFFzQGPNwQK9cc8Mii5m1OEJDIeKW2D+MaC/z3UwaM6Hxa3t666t\n Oa50dHr5CAPTQXgoQBw==", "X-Proofpoint-GUID": "UtPE3_HrdjXIRbqhkA1ypf7kFztzueQf", "X-Proofpoint-ORIG-GUID": "UtPE3_HrdjXIRbqhkA1ypf7kFztzueQf", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-01_03,2026-04-01_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0\n impostorscore=0 phishscore=0 bulkscore=0 priorityscore=1501 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010108" }, "content": "The Top Level Mode Multiplexer (TLMM) in the Hawi SoC provide GPIO and\npinctrl functionality for UFS, SDC and 226 GPIO pins.\n\nAdd a DeviceTree binding to describe the Hawi TLMM block.\n\nSigned-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>\n---\n .../bindings/pinctrl/qcom,hawi-tlmm.yaml | 123 +++++++++++++++++++++\n 1 file changed, 123 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml\nnew file mode 100644\nindex 000000000000..303bd7262aac\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml\n@@ -0,0 +1,123 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Technologies, Inc. Hawi TLMM block\n+\n+maintainers:\n+ - Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>\n+\n+description:\n+ Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,hawi-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 113\n+\n+ gpio-line-names:\n+ maxItems: 226\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-hawi-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-hawi-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-hawi-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$\"\n+ - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]\n+ minItems: 1\n+ maxItems: 36\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+ enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,\n+ audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda,\n+ cci_timer, coex_espmi_sclk, coex_espmi_sdata, coex_uart1_rx,\n+ coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot,\n+ egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0, i2chub0_se1,\n+ i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0_data, i2s0_sck,\n+ i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist,\n+ mdp_esync0, mdp_esync1, mdp_esync2, mdp_vsync, mdp_vsync_e,\n+ mdp_vsync_p, mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out,\n+ mdp_vsync3_out, mdp_vsync5_out, modem_pps_in, modem_pps_out,\n+ nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, nav_gpio4, nav_gpio5,\n+ nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,\n+ phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink_enable,\n+ qlink_request, qlink_wmss, qspi, qspi_clk, qspi_cs, qup1_se0,\n+ qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6,\n+ qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4_l0,\n+ qup2_se4_l1, qup2_se4_l2, qup2_se4_l3, qup3_se0_l0, qup3_se0_l1,\n+ qup3_se0_l2, qup3_se0_l3, qup3_se1, qup3_se2, qup3_se3, qup3_se4,\n+ qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_l0, qup4_se3_l1,\n+ qup4_se3_l2, qup4_se3_l3, qup4_se4_l0, qup4_se4_l1, qup4_se4_l2,\n+ qup4_se4_l3, rng_rosc, sd_write_protect, sdc4_clk,\n+ sdc4_cmd, sdc4_data, sys_throttle, tb_trig_sdc, tmess_rng,\n+ tsense_clm, tsense_pwm, uim0_clk, uim0_data, uim0_present,\n+ uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,\n+ usb0_hs, usb_phy, vfr, vsense_trigger_mirnat, wcn_sw_ctrl ]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@f100000 {\n+ compatible = \"qcom,hawi-tlmm\";\n+ reg = <0x0f100000 0x300000>;\n+ interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&tlmm 0 0 227>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+\n+ qup-uart7-state {\n+ pins = \"gpio62\", \"gpio63\";\n+ function = \"qup1_se7\";\n+ };\n+ };\n+...\n", "prefixes": [ "1/2" ] }