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GET /api/patches/2218483/?format=api
{ "id": 2218483, "url": "http://patchwork.ozlabs.org/api/patches/2218483/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260401-pcie-intel-gw-v3-4-63b008c5b7b2@dev.tdt.de/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401-pcie-intel-gw-v3-4-63b008c5b7b2@dev.tdt.de>", "list_archive_url": null, "date": "2026-04-01T09:31:40", "name": "[v3,4/7] PCI: intel-gw: Enable clock before phy init", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "06b764a98d01d546fbcc9e9d45361ce91302bb27", "submitter": { "id": 72238, "url": "http://patchwork.ozlabs.org/api/people/72238/?format=api", "name": "Florian Eckert", "email": "fe@dev.tdt.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260401-pcie-intel-gw-v3-4-63b008c5b7b2@dev.tdt.de/mbox/", "series": [ { "id": 498301, "url": "http://patchwork.ozlabs.org/api/series/498301/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498301", "date": "2026-04-01T09:31:36", "name": "PCI: intel-gw: Fixes to make the driver working again", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498301/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218483/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218483/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51666-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=temperror header.d=dev.tdt.de header.i=@dev.tdt.de header.a=rsa-sha256\n header.s=z1-selector1 header.b=pkp8mrrb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de;\n\ts=z1-selector1; t=1775035903;\n\tbh=eTw8E3ezVzDUqc+dP4JdW7vl/OP8CGUQKxaL+SejZ2g=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n\tb=pkp8mrrbEocjtIIeeWx7LvW2p+rex33JmWAdUFFo2Xt6lo1MxFHgGG8A39m2kRM8Z\n\t G+8bbTmNnSNh5Bd3OuhomSHK72YxqDkP7Od4Sjow88G9xHyRzbBqbYa02ksqe9bDS/\n\t A/1LKyHbCpeRWlvxX5MehNNieWSQEvyK2tFV+LcvHEccc4tAQwsbu0Ytz7flX2aUUE\n\t BGFU8wYR79A6aV+NKGqldlNDXDZvWQNganaZrCFD6cQTxxTnveuYEpKWVk4dUH/Fp4\n\t 0e5BPY9cRrNkUo2uOirRcxWxsuprJh+iEDd4hhYRyOkiLmMeOgaM9k6cIBkRwGEfgC\n\t Q0eUubrw0UUIw==", "From": "Florian Eckert <fe@dev.tdt.de>", "Date": "Wed, 01 Apr 2026 11:31:40 +0200", "Subject": "[PATCH v3 4/7] PCI: intel-gw: Enable clock before phy init", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20260401-pcie-intel-gw-v3-4-63b008c5b7b2@dev.tdt.de>", "References": "<20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de>", "In-Reply-To": "<20260401-pcie-intel-gw-v3-0-63b008c5b7b2@dev.tdt.de>", "To": "Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Johan Hovold <johan+linaro@kernel.org>,\n Sajid Dalvi <sdalvi@google.com>, Ajay Agarwal <ajayagarwal@google.com>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Rahul Tanwar <rtanwar@maxlinear.com>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Florian Eckert <fe@dev.tdt.de>,\n\tEckert.Florian@googlemail.com, ms@dev.tdt.de", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775035902; l=2080;\n i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id;\n bh=coHmsdtqcsW+dKyhuAd7vn7jGgDFbg9jYRqHLyenC9w=;\n b=upmlMIqhxzzCBzYMxjiufaXeChhcEK6DMbp8eW3nyfpQ7M1+fzt4eU9xZ55SaDbLFN01wVifK\n 9ljfiAJ+60WDY/2pEJ2kFQYvV3VVXGr3Yh4tS/9zZvC+foq3A8n9Hzb", "X-Developer-Key": "i=fe@dev.tdt.de; a=ed25519;\n pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk=", "X-purgate-ID": "151534::1775035904-3D7CA233-2D4E2C4D/0/0", "X-purgate": "clean", "X-purgate-type": "clean" }, "content": "To ensure that the boot sequence is correct, the dwc pcie core clock must\nbe switched on before phy init call [1]. This changes are based on patched\nkernel sources of the MaxLinear SDK.\n\n[1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/controller/dwc/pcie-intel-gw.c#L544\n\nSigned-off-by: Florian Eckert <fe@dev.tdt.de>\n---\n drivers/pci/controller/dwc/pcie-intel-gw.c | 19 ++++++++++---------\n 1 file changed, 10 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c\nindex e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0..6d9499d954674a26a74bff56b7fb5759767424c0 100644\n--- a/drivers/pci/controller/dwc/pcie-intel-gw.c\n+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c\n@@ -291,13 +291,9 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \n \tintel_pcie_core_rst_assert(pcie);\n \tintel_pcie_device_rst_assert(pcie);\n-\n-\tret = phy_init(pcie->phy);\n-\tif (ret)\n-\t\treturn ret;\n-\n \tintel_pcie_core_rst_deassert(pcie);\n \n+\t/* Controller clock must be provided earlier than PHY */\n \tret = clk_prepare_enable(pcie->core_clk);\n \tif (ret) {\n \t\tdev_err(pcie->pci.dev, \"Core clock enable failed: %d\\n\", ret);\n@@ -306,13 +302,17 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \n \tpci->atu_base = pci->dbi_base + 0xC0000;\n \n+\tret = phy_init(pcie->phy);\n+\tif (ret)\n+\t\tgoto phy_err;\n+\n \tintel_pcie_ltssm_disable(pcie);\n \tintel_pcie_link_setup(pcie);\n \tintel_pcie_init_n_fts(pci);\n \n \tret = dw_pcie_setup_rc(&pci->pp);\n \tif (ret)\n-\t\tgoto app_init_err;\n+\t\tgoto err;\n \n \tdw_pcie_upconfig_setup(pci);\n \n@@ -321,17 +321,18 @@ static int intel_pcie_host_setup(struct intel_pcie *pcie)\n \n \tret = dw_pcie_wait_for_link(pci);\n \tif (ret)\n-\t\tgoto app_init_err;\n+\t\tgoto err;\n \n \tintel_pcie_core_irq_enable(pcie);\n \n \treturn 0;\n \n-app_init_err:\n+err:\n+\tphy_exit(pcie->phy);\n+phy_err:\n \tclk_disable_unprepare(pcie->core_clk);\n clk_err:\n \tintel_pcie_core_rst_assert(pcie);\n-\tphy_exit(pcie->phy);\n \n \treturn ret;\n }\n", "prefixes": [ "v3", "4/7" ] }