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GET /api/patches/2218481/?format=api
{ "id": 2218481, "url": "http://patchwork.ozlabs.org/api/patches/2218481/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260401094226.2900532-12-shengjiu.wang@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20260401094226.2900532-12-shengjiu.wang@nxp.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20260401094226.2900532-12-shengjiu.wang@nxp.com/", "date": "2026-04-01T09:42:26", "name": "[v2,11/11] ASoC: fsl_easrc: Change the type for iec958 channel status controls", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2472ea31c4ed81e875a32d34c5cd6c3f603d8aa9", "submitter": { "id": 75958, "url": "http://patchwork.ozlabs.org/api/people/75958/?format=api", "name": "Shengjiu Wang", "email": "shengjiu.wang@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260401094226.2900532-12-shengjiu.wang@nxp.com/mbox/", "series": [ { "id": 498302, "url": "http://patchwork.ozlabs.org/api/series/498302/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=498302", "date": "2026-04-01T09:42:15", "name": "ASoC: fsl: fix mixer-test failures", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/498302/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218481/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/2218481/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-19139-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n header.s=selector1 header.b=XVipNUdY;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-19139-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=pass smtp.remote-ip=\"2a01:111:f403:c207::3\" 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envelope-from=shengjiu.wang@nxp.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=nxp.com", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=lcy5UmZqh/o0ySld2VRlYssBwZ+fCg5A6+bAmvQGrUI=;\n b=XVipNUdYnmSn1UvJFOQ2m94PMNgxFlsaO1ROslYW+PqfcKgVsR8v1e9/Rip7xOpsrBriL3ivD1X8EihB7AhPoIo3ja+vmfumyiq+OyPlgpl7ztTccb/PuK1eoeU+U6oS8sWQGmM2tpccA/iHlK3a8ecjd6u9QhCUU4+NkzUrqHu8hZ5tqLiawsdKBaxWVKiZZ1JHUkq6RLeqUgJ5Nrxgst2lQbObiyxnjxs1T/uh2tALcuMopwhPDwr2q+y0Ikvm68qVQzePOOmHzYYGUnAryYn6Q1olelaHcQ4yhg0e7YWtGjlicR6QkPmusc5zzKoQovLJ8btu8TWe+5XUsGzEIQ==", "From": "Shengjiu Wang <shengjiu.wang@nxp.com>", "To": "shengjiu.wang@gmail.com,\n\tXiubo.Lee@gmail.com,\n\tfestevam@gmail.com,\n\tnicoleotsuka@gmail.com,\n\tlgirdwood@gmail.com,\n\tbroonie@kernel.org,\n\tperex@perex.cz,\n\ttiwai@suse.com,\n\tlinux-sound@vger.kernel.org,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 11/11] ASoC: fsl_easrc: Change the type for iec958 channel\n status controls", "Date": "Wed, 1 Apr 2026 17:42:26 +0800", "Message-Id": "<20260401094226.2900532-12-shengjiu.wang@nxp.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20260401094226.2900532-1-shengjiu.wang@nxp.com>", "References": "<20260401094226.2900532-1-shengjiu.wang@nxp.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SI2PR02CA0029.apcprd02.prod.outlook.com\n (2603:1096:4:195::6) To AM0PR04MB7044.eurprd04.prod.outlook.com\n (2603:10a6:208:191::20)", "X-Mailing-List": "linuxppc-dev@lists.ozlabs.org", "List-Id": "<linuxppc-dev.lists.ozlabs.org>", "List-Help": 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(2024-03-25) on lists.ozlabs.org" }, "content": "Use the type SNDRV_CTL_ELEM_TYPE_IEC958 for iec958 channel status\ncontrols, the original type will cause mixer-test to iterate all 32bit\nvalues, which costs a lot of time. And using IEC958 type can reduce the\ncontrol numbers.\n\nAlso enable pm runtime before updating registers to make the regmap cache\ndata align with the value in hardware.\n\nFixes: 955ac624058f (\"ASoC: fsl_easrc: Add EASRC ASoC CPU DAI drivers\")\nSigned-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>\n---\n sound/soc/fsl/fsl_easrc.c | 118 +++++++++++++++++++++++++++-----------\n 1 file changed, 84 insertions(+), 34 deletions(-)", "diff": "diff --git a/sound/soc/fsl/fsl_easrc.c b/sound/soc/fsl/fsl_easrc.c\nindex 3086cb758beb..114a6c0b6b73 100644\n--- a/sound/soc/fsl/fsl_easrc.c\n+++ b/sound/soc/fsl/fsl_easrc.c\n@@ -78,17 +78,47 @@ static int fsl_easrc_iec958_get_bits(struct snd_kcontrol *kcontrol,\n \treturn 0;\n }\n \n+static int fsl_easrc_iec958_info(struct snd_kcontrol *kcontrol,\n+\t\t\t\t struct snd_ctl_elem_info *uinfo)\n+{\n+\tuinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;\n+\tuinfo->count = 1;\n+\treturn 0;\n+}\n+\n static int fsl_easrc_get_reg(struct snd_kcontrol *kcontrol,\n \t\t\t struct snd_ctl_elem_value *ucontrol)\n {\n \tstruct snd_soc_component *component = snd_kcontrol_chip(kcontrol);\n \tstruct soc_mreg_control *mc =\n \t\t(struct soc_mreg_control *)kcontrol->private_value;\n-\tunsigned int regval;\n+\tstruct fsl_asrc *easrc = snd_soc_component_get_drvdata(component);\n+\tunsigned int *regval = (unsigned int *)ucontrol->value.iec958.status;\n+\tint ret;\n+\n+\tret = regmap_read(easrc->regmap, REG_EASRC_CS0(mc->regbase), ®val[0]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(easrc->regmap, REG_EASRC_CS1(mc->regbase), ®val[1]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(easrc->regmap, REG_EASRC_CS2(mc->regbase), ®val[2]);\n+\tif (ret)\n+\t\treturn ret;\n \n-\tregval = snd_soc_component_read(component, mc->regbase);\n+\tret = regmap_read(easrc->regmap, REG_EASRC_CS3(mc->regbase), ®val[3]);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(easrc->regmap, REG_EASRC_CS4(mc->regbase), ®val[4]);\n+\tif (ret)\n+\t\treturn ret;\n \n-\tucontrol->value.integer.value[0] = regval;\n+\tret = regmap_read(easrc->regmap, REG_EASRC_CS5(mc->regbase), ®val[5]);\n+\tif (ret)\n+\t\treturn ret;\n \n \treturn 0;\n }\n@@ -100,22 +130,62 @@ static int fsl_easrc_set_reg(struct snd_kcontrol *kcontrol,\n \tstruct soc_mreg_control *mc =\n \t\t(struct soc_mreg_control *)kcontrol->private_value;\n \tstruct fsl_asrc *easrc = snd_soc_component_get_drvdata(component);\n-\tunsigned int regval = ucontrol->value.integer.value[0];\n-\tbool changed;\n+\tunsigned int *regval = (unsigned int *)ucontrol->value.iec958.status;\n+\tbool changed, changed_all = false;\n \tint ret;\n \n-\tret = regmap_update_bits_check(easrc->regmap, mc->regbase,\n-\t\t\t\t GENMASK(31, 0), regval, &changed);\n-\tif (ret != 0)\n+\tret = pm_runtime_resume_and_get(component->dev);\n+\tif (ret)\n \t\treturn ret;\n \n-\treturn changed;\n+\tret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS0(mc->regbase),\n+\t\t\t\t GENMASK(31, 0), regval[0], &changed);\n+\tif (ret != 0)\n+\t\tgoto err;\n+\tchanged_all |= changed;\n+\n+\tret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS1(mc->regbase),\n+\t\t\t\t GENMASK(31, 0), regval[1], &changed);\n+\tif (ret != 0)\n+\t\tgoto err;\n+\tchanged_all |= changed;\n+\n+\tret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS2(mc->regbase),\n+\t\t\t\t GENMASK(31, 0), regval[2], &changed);\n+\tif (ret != 0)\n+\t\tgoto err;\n+\tchanged_all |= changed;\n+\n+\tret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS3(mc->regbase),\n+\t\t\t\t GENMASK(31, 0), regval[3], &changed);\n+\tif (ret != 0)\n+\t\tgoto err;\n+\tchanged_all |= changed;\n+\n+\tret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS4(mc->regbase),\n+\t\t\t\t GENMASK(31, 0), regval[4], &changed);\n+\tif (ret != 0)\n+\t\tgoto err;\n+\tchanged_all |= changed;\n+\n+\tret = regmap_update_bits_check(easrc->regmap, REG_EASRC_CS5(mc->regbase),\n+\t\t\t\t GENMASK(31, 0), regval[5], &changed);\n+\tif (ret != 0)\n+\t\tgoto err;\n+\tchanged_all |= changed;\n+err:\n+\tpm_runtime_put_autosuspend(component->dev);\n+\n+\tif (ret != 0)\n+\t\treturn ret;\n+\telse\n+\t\treturn changed_all;\n }\n \n #define SOC_SINGLE_REG_RW(xname, xreg) \\\n {\t.iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = (xname), \\\n \t.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, \\\n-\t.info = snd_soc_info_xr_sx, .get = fsl_easrc_get_reg, \\\n+\t.info = fsl_easrc_iec958_info, .get = fsl_easrc_get_reg, \\\n \t.put = fsl_easrc_set_reg, \\\n \t.private_value = (unsigned long)&(struct soc_mreg_control) \\\n \t\t{ .regbase = xreg, .regcount = 1, .nbits = 32, \\\n@@ -146,30 +216,10 @@ static const struct snd_kcontrol_new fsl_easrc_snd_controls[] = {\n \tSOC_SINGLE_VAL_RW(\"Context 2 IEC958 Bits Per Sample\", 2),\n \tSOC_SINGLE_VAL_RW(\"Context 3 IEC958 Bits Per Sample\", 3),\n \n-\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS0\", REG_EASRC_CS0(0)),\n-\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS0\", REG_EASRC_CS0(1)),\n-\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS0\", REG_EASRC_CS0(2)),\n-\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS0\", REG_EASRC_CS0(3)),\n-\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS1\", REG_EASRC_CS1(0)),\n-\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS1\", REG_EASRC_CS1(1)),\n-\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS1\", REG_EASRC_CS1(2)),\n-\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS1\", REG_EASRC_CS1(3)),\n-\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS2\", REG_EASRC_CS2(0)),\n-\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS2\", REG_EASRC_CS2(1)),\n-\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS2\", REG_EASRC_CS2(2)),\n-\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS2\", REG_EASRC_CS2(3)),\n-\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS3\", REG_EASRC_CS3(0)),\n-\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS3\", REG_EASRC_CS3(1)),\n-\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS3\", REG_EASRC_CS3(2)),\n-\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS3\", REG_EASRC_CS3(3)),\n-\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS4\", REG_EASRC_CS4(0)),\n-\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS4\", REG_EASRC_CS4(1)),\n-\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS4\", REG_EASRC_CS4(2)),\n-\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS4\", REG_EASRC_CS4(3)),\n-\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS5\", REG_EASRC_CS5(0)),\n-\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS5\", REG_EASRC_CS5(1)),\n-\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS5\", REG_EASRC_CS5(2)),\n-\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS5\", REG_EASRC_CS5(3)),\n+\tSOC_SINGLE_REG_RW(\"Context 0 IEC958 CS\", 0),\n+\tSOC_SINGLE_REG_RW(\"Context 1 IEC958 CS\", 1),\n+\tSOC_SINGLE_REG_RW(\"Context 2 IEC958 CS\", 2),\n+\tSOC_SINGLE_REG_RW(\"Context 3 IEC958 CS\", 3),\n };\n \n /*\n", "prefixes": [ "v2", "11/11" ] }