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{
    "id": 2218405,
    "url": "http://patchwork.ozlabs.org/api/patches/2218405/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260401-waveshare-dsi-touch-v1-14-5e9119b5a014@oss.qualcomm.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260401-waveshare-dsi-touch-v1-14-5e9119b5a014@oss.qualcomm.com>",
    "list_archive_url": null,
    "date": "2026-04-01T07:26:33",
    "name": "[14/19] drm/panel: jadard-jd9365da-h3: support Waveshare DSI panels",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "13caf63dd5a69a4a469aaaa0252a85b9a065973a",
    "submitter": {
        "id": 90483,
        "url": "http://patchwork.ozlabs.org/api/people/90483/?format=api",
        "name": "Dmitry Baryshkov",
        "email": "dmitry.baryshkov@oss.qualcomm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260401-waveshare-dsi-touch-v1-14-5e9119b5a014@oss.qualcomm.com/mbox/",
    "series": [
        {
            "id": 498284,
            "url": "http://patchwork.ozlabs.org/api/series/498284/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498284",
            "date": "2026-04-01T07:26:23",
            "name": "drm/panel: support Waveshare DSI TOUCH kits",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/498284/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2218405/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2218405/checks/",
    "tags": {},
    "related": [],
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        ],
        "From": "Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>",
        "Date": "Wed, 01 Apr 2026 10:26:33 +0300",
        "Subject": "[PATCH 14/19] drm/panel: jadard-jd9365da-h3: support Waveshare DSI\n panels",
        "Precedence": "bulk",
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        "Message-Id": "<20260401-waveshare-dsi-touch-v1-14-5e9119b5a014@oss.qualcomm.com>",
        "References": "<20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>",
        "In-Reply-To": "<20260401-waveshare-dsi-touch-v1-0-5e9119b5a014@oss.qualcomm.com>",
        "To": "Neil Armstrong <neil.armstrong@linaro.org>,\n        Jessica Zhang <jesszhan0024@gmail.com>,\n        David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,\n        Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,\n        Maxime Ripard <mripard@kernel.org>,\n        Thomas Zimmermann <tzimmermann@suse.de>,\n Rob Herring <robh@kernel.org>,\n        Krzysztof Kozlowski <krzk+dt@kernel.org>,\n        Conor Dooley <conor+dt@kernel.org>,\n        Cong Yang <yangcong5@huaqin.corp-partner.google.com>,\n        Ondrej Jirman <megi@xff.cz>,\n        Javier Martinez Canillas <javierm@redhat.com>,\n        Jagan Teki <jagan@edgeble.ai>, Liam Girdwood <lgirdwood@gmail.com>,\n        Mark Brown <broonie@kernel.org>, Linus Walleij <linusw@kernel.org>,\n        Bartosz Golaszewski <brgl@kernel.org>",
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    },
    "content": "Add configuration for Waveshare DSI panels using JD9365 controller.\n\nSigned-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>\n---\n drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c | 1524 ++++++++++++++++++++--\n 1 file changed, 1440 insertions(+), 84 deletions(-)",
    "diff": "diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\nindex 11b7e07c1af8..e9a461239301 100644\n--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c\n@@ -21,6 +21,8 @@\n #include <linux/of.h>\n #include <linux/regulator/consumer.h>\n \n+#include <video/mipi_display.h>\n+\n struct jadard;\n \n struct jadard_panel_desc {\n@@ -1599,115 +1601,1469 @@ static const struct jadard_panel_desc taiguan_xti05101_01a_desc = {\n \t.enter_sleep_to_reset_down_delay_ms = 100,\n };\n \n-static int jadard_dsi_probe(struct mipi_dsi_device *dsi)\n+static int waveshare_3_4_c_init(struct jadard *jadard)\n {\n-\tstruct device *dev = &dsi->dev;\n-\tconst struct jadard_panel_desc *desc;\n-\tstruct jadard *jadard;\n-\tint ret;\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n \n-\tjadard = devm_drm_panel_alloc(dev, struct jadard, panel, &jadard_funcs,\n-\t\t\t\t      DRM_MODE_CONNECTOR_DSI);\n-\tif (IS_ERR(jadard))\n-\t\treturn PTR_ERR(jadard);\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n \n-\tdesc = of_device_get_match_data(dev);\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x64);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xc7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x0f);\n \n-\tif (desc->mode_flags)\n-\t\tdsi->mode_flags = desc->mode_flags;\n-\telse\n-\t\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO |\n-\t\t\t\t  MIPI_DSI_MODE_VIDEO_BURST |\n-\t\t\t\t  MIPI_DSI_MODE_NO_EOT_PACKET;\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x42);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n \n-\tdsi->format = desc->format;\n-\tdsi->lanes = desc->lanes;\n-\tif (!dsi->lanes) {\n-\t\tdsi->lanes = drm_of_get_data_lanes_count_remote(dsi->dev.of_node, 0, -1, 2, 4);\n-\t\tif (dsi->lanes < 0)\n-\t\t\treturn dsi->lanes;\n-\t}\n-\tdev_dbg(&dsi->dev, \"lanes: %d\\n\", dsi->lanes);\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xa6);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xd9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n \n-\tjadard->reset = devm_gpiod_get(dev, \"reset\", GPIOD_OUT_HIGH);\n-\tif (IS_ERR(jadard->reset))\n-\t\treturn dev_err_probe(&dsi->dev, PTR_ERR(jadard->reset),\n-\t\t\t\t\"failed to get our reset GPIO\\n\");\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n \n-\tjadard->vdd = devm_regulator_get(dev, \"vdd\");\n-\tif (IS_ERR(jadard->vdd))\n-\t\treturn dev_err_probe(&dsi->dev, PTR_ERR(jadard->vdd),\n-\t\t\t\t\"failed to get vdd regulator\\n\");\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(5);\n+\tmipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);\n \n-\tjadard->vccio = devm_regulator_get(dev, \"vccio\");\n-\tif (IS_ERR(jadard->vccio))\n-\t\treturn dev_err_probe(&dsi->dev, PTR_ERR(jadard->vccio),\n-\t\t\t\t\"failed to get vccio regulator\\n\");\n+\treturn dsi_ctx.accum_err;\n+}\n \n-\tret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation);\n-\tif (ret < 0)\n-\t\treturn dev_err_probe(dev, ret, \"failed to get orientation\\n\");\n+static const struct jadard_panel_desc waveshare_3_4_inch_c_desc = {\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (800 + 40 + 20 + 20) * (800 + 24 + 4 + 12) * 60 / 1000,\n \n-\tret = drm_panel_of_backlight(&jadard->panel);\n-\tif (ret)\n-\t\treturn ret;\n+\t\t.hdisplay\t= 800,\n+\t\t.hsync_start\t= 800 + 40,\n+\t\t.hsync_end\t= 800 + 40 + 20,\n+\t\t.htotal\t\t= 800 + 40 + 20 + 20,\n \n-\tjadard->panel.prepare_prev_first = true;\n+\t\t.vdisplay\t= 800,\n+\t\t.vsync_start\t= 800 + 24,\n+\t\t.vsync_end\t= 800 + 24 + 4,\n+\t\t.vtotal\t\t= 800 + 24 + 4 + 12,\n \n-\tdrm_panel_add(&jadard->panel);\n+\t\t.width_mm\t= 88,\n+\t\t.height_mm\t= 88,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.lanes = 2,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_3_4_c_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n \n-\tmipi_dsi_set_drvdata(dsi, jadard);\n-\tjadard->dsi = dsi;\n-\tjadard->desc = desc;\n+static int waveshare_4_0_c_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n \n-\tret = mipi_dsi_attach(dsi);\n-\tif (ret < 0)\n-\t\tdrm_panel_remove(&jadard->panel);\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n \n-\treturn ret;\n-}\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xd0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x64);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0xc7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x1b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x16);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x2f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x32);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x53);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x4c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x31);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x20);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x0f);\n \n-static void jadard_dsi_remove(struct mipi_dsi_device *dsi)\n-{\n-\tstruct jadard *jadard = mipi_dsi_get_drvdata(dsi);\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x42);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x5e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n \n-\tmipi_dsi_detach(dsi);\n-\tdrm_panel_remove(&jadard->panel);\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0xa6);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xd9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x33);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(5);\n+\tmipi_dsi_dcs_set_tear_on_multi(&dsi_ctx, MIPI_DSI_DCS_TEAR_MODE_VBLANK);\n+\n+\treturn dsi_ctx.accum_err;\n }\n \n-static const struct of_device_id jadard_of_match[] = {\n-\t{\n-\t\t.compatible = \"anbernic,rg-ds-display-bottom\",\n-\t\t.data = &anbernic_rgds_display_desc\n-\t},\n-\t{\n-\t\t.compatible = \"anbernic,rg-ds-display-top\",\n-\t\t.data = &anbernic_rgds_display_desc\n-\t},\n-\t{\n-\t\t.compatible = \"chongzhou,cz101b4001\",\n-\t\t.data = &cz101b4001_desc\n-\t},\n-\t{\n-\t\t.compatible = \"kingdisplay,kd101ne3-40ti\",\n-\t\t.data = &kingdisplay_kd101ne3_40ti_desc\n-\t},\n-\t{\n-\t\t.compatible = \"melfas,lmfbx101117480\",\n-\t\t.data = &melfas_lmfbx101117480_desc\n-\t},\n-\t{\n-\t\t.compatible = \"radxa,display-10hd-ad001\",\n-\t\t.data = &cz101b4001_desc\n+static const struct jadard_panel_desc waveshare_4_0_inch_c_desc = {\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 40 + 20 + 20) * (720 + 24 + 4 + 12) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 40,\n+\t\t.hsync_end\t= 720 + 40 + 20,\n+\t\t.htotal\t\t= 720 + 40 + 20 + 20,\n+\n+\t\t.vdisplay\t= 720,\n+\t\t.vsync_start\t= 720 + 24,\n+\t\t.vsync_end\t= 720 + 24 + 4,\n+\t\t.vtotal\t\t= 720 + 24 + 4 + 12,\n+\n+\t\t.width_mm\t= 88,\n+\t\t.height_mm\t= 88,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n \t},\n-\t{\n-\t\t.compatible = \"radxa,display-8hd-ad002\",\n-\t\t.data = &radxa_display_8hd_ad002_desc\n+\t.lanes = 2,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_4_0_c_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static int waveshare_8_0_a_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x7e);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x4e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xb7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xb7);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x70);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x63);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x54);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x56);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xf8);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x03);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x7b);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);\n+\tif (jadard->dsi->lanes != 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n+\t}\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(60);\n+\n+\treturn 0;\n+}\n+\n+static const struct drm_display_mode waveshare_8_0_a_mode = {\n+\t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 30 + 12 + 4) * 60 / 1000,\n+\n+\t.hdisplay\t= 800,\n+\t.hsync_start\t= 800 + 40,\n+\t.hsync_end\t= 800 + 40 + 20,\n+\t.htotal\t\t= 800 + 40 + 20 + 20,\n+\n+\t.vdisplay\t= 1280,\n+\t.vsync_start\t= 1280 + 30,\n+\t.vsync_end\t= 1280 + 30 + 12,\n+\t.vtotal\t\t= 1280 + 30 + 12 + 4,\n+\n+\t.width_mm\t= 107,\n+\t.height_mm\t= 172,\n+\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+};\n+\n+static const struct jadard_panel_desc waveshare_8_0_inch_a_desc = {\n+\t.mode_4ln = &waveshare_8_0_a_mode,\n+\t.mode_2ln = &waveshare_8_0_a_mode,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_8_0_a_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\t      MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static int waveshare_10_1_b_init(struct jadard *jadard);\n+\n+static const struct jadard_panel_desc waveshare_9_0_inch_b_desc = {\n+\t.mode_4ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 60,\n+\t\t.hsync_end\t= 720 + 60 + 60,\n+\t\t.htotal\t\t= 720 + 60 + 60 + 4,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 16,\n+\t\t.vsync_end\t= 1280 + 16 + 12,\n+\t\t.vtotal\t\t= 1280 + 16 + 12 + 4,\n+\n+\t\t.width_mm\t= 114,\n+\t\t.height_mm\t= 196,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 50,\n+\t\t.hsync_end\t= 720 + 50 + 50,\n+\t\t.htotal\t\t= 720 + 50 + 50 + 50,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 26,\n+\t\t.vsync_end\t= 1280 + 26 + 12,\n+\t\t.vtotal\t\t= 1280 + 26 + 12 + 4,\n+\n+\t\t.width_mm\t= 114,\n+\t\t.height_mm\t= 196,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_10_1_b_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static const struct drm_display_mode waveshare_10_1_a_mode = {\n+\t.clock\t\t= (800 + 40 + 20 + 20) * (1280 + 20 + 20 + 4) * 60 / 1000,\n+\n+\t.hdisplay\t= 800,\n+\t.hsync_start\t= 800 + 40,\n+\t.hsync_end\t= 800 + 40 + 20,\n+\t.htotal\t\t= 800 + 40 + 20 + 20,\n+\n+\t.vdisplay\t= 1280,\n+\t.vsync_start\t= 1280 + 20,\n+\t.vsync_end\t= 1280 + 20 + 20,\n+\t.vtotal\t\t= 1280 + 20 + 20 + 4,\n+\n+\t.width_mm\t= 135,\n+\t.height_mm\t= 216,\n+\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+};\n+\n+static int waveshare_10_1_a_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3b);\n+\telse {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x38);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x38);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xaf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xaf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x26);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x81);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x14);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x23);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0d);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x69);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6b);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5c);\n+\t} else  {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x6a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x5b);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2b);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x3d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x2a);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x43);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x63);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x44);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x52);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x4e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x20);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0f);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x59);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4c);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x48);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x3a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x26);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6b);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5c);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x6a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x5b);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4f);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2b);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x3d);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x2a);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x43);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x43);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x63);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x44);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x62);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x52);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x4e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x20);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0f);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x59);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4c);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x48);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x3a);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x26);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x02);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x02);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x37);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x37);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x42);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x77);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x77);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x49);\n+\tif (jadard->dsi->lanes == 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x01);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x01);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x1e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x1f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x17);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x37);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x37);\n+\t} else {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x41);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x40);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x5e);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x5f);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x57);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x77);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x77);\n+\t}\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x48);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x1f);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x37);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x30);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x16);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x34);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x1d);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xdd);\n+\tif (jadard->dsi->lanes == 4)\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x3f);\n+\telse\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2c);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x15);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x82);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x61);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);\n+\tif (jadard->dsi->lanes != 4) {\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n+\t\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n+\t}\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x0c);\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(60);\n+\n+\treturn dsi_ctx.accum_err;\n+}\n+\n+static const struct jadard_panel_desc waveshare_10_1_inch_a_desc = {\n+\t.mode_4ln = &waveshare_10_1_a_mode,\n+\t.mode_2ln = &waveshare_10_1_a_mode,\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_10_1_a_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static int waveshare_10_1_b_init(struct jadard *jadard)\n+{\n+\tstruct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tjadard_enable_standard_cmds(&dsi_ctx);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x3f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x74);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0xff);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x7e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x24);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xa9);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x38);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x65);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x52);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x3f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x34);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x27);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x24);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x65);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x52);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x3d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x14);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x28);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x25);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x23);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x3f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x2d);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x34);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x27);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x24);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x18);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x00);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x50);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x77);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x57);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x47);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x46);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x45);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x44);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x4b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x4a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x49);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x41);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x5f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x15);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x15);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x17);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x0a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x0b);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x11);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x1f);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x07);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x66);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x55);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x13);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x66);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x08);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xe3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xd5);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x21);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x00);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x06);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x66);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x04);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0e);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xb3);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x58);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x0f);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x05);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1d);\n+\n+\tjd9365da_switch_page(&dsi_ctx, 0x00);\n+\tmipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);\n+\tmsleep(120);\n+\tmipi_dsi_dcs_set_display_on_multi(&dsi_ctx);\n+\tmsleep(5);\n+\tmipi_dsi_dcs_write_seq_multi(&dsi_ctx, MIPI_DCS_SET_TEAR_ON);\n+\n+\treturn 0;\n+}\n+\n+static const struct jadard_panel_desc waveshare_10_1_inch_b_desc = {\n+\t.mode_4ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 60 + 60 + 4) * (1280 + 16 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 60,\n+\t\t.hsync_end\t= 720 + 60 + 60,\n+\t\t.htotal\t\t= 720 + 60 + 60 + 4,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 16,\n+\t\t.vsync_end\t= 1280 + 16 + 12,\n+\t\t.vtotal\t\t= 1280 + 16 + 12 + 4,\n+\n+\t\t.width_mm\t= 125,\n+\t\t.height_mm\t= 222,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.mode_2ln = &(const struct drm_display_mode) {\n+\t\t.clock\t\t= (720 + 50 + 50 + 50) * (1280 + 26 + 12 + 4) * 60 / 1000,\n+\n+\t\t.hdisplay\t= 720,\n+\t\t.hsync_start\t= 720 + 50,\n+\t\t.hsync_end\t= 720 + 50 + 50,\n+\t\t.htotal\t\t= 720 + 50 + 50 + 50,\n+\n+\t\t.vdisplay\t= 1280,\n+\t\t.vsync_start\t= 1280 + 26,\n+\t\t.vsync_end\t= 1280 + 26 + 12,\n+\t\t.vtotal\t\t= 1280 + 26 + 12 + 4,\n+\n+\t\t.width_mm\t= 125,\n+\t\t.height_mm\t= 222,\n+\t\t.type\t\t= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,\n+\t},\n+\t.format = MIPI_DSI_FMT_RGB888,\n+\t.init = waveshare_10_1_b_init,\n+\t.mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |\n+\t\tMIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,\n+};\n+\n+static int jadard_dsi_probe(struct mipi_dsi_device *dsi)\n+{\n+\tstruct device *dev = &dsi->dev;\n+\tconst struct jadard_panel_desc *desc;\n+\tstruct jadard *jadard;\n+\tint ret;\n+\n+\tjadard = devm_drm_panel_alloc(dev, struct jadard, panel, &jadard_funcs,\n+\t\t\t\t      DRM_MODE_CONNECTOR_DSI);\n+\tif (IS_ERR(jadard))\n+\t\treturn PTR_ERR(jadard);\n+\n+\tdesc = of_device_get_match_data(dev);\n+\n+\tif (desc->mode_flags)\n+\t\tdsi->mode_flags = desc->mode_flags;\n+\telse\n+\t\tdsi->mode_flags = MIPI_DSI_MODE_VIDEO |\n+\t\t\t\t  MIPI_DSI_MODE_VIDEO_BURST |\n+\t\t\t\t  MIPI_DSI_MODE_NO_EOT_PACKET;\n+\n+\tdsi->format = desc->format;\n+\tdsi->lanes = desc->lanes;\n+\tif (!dsi->lanes) {\n+\t\tdsi->lanes = drm_of_get_data_lanes_count_remote(dsi->dev.of_node, 0, -1, 2, 4);\n+\t\tif (dsi->lanes < 0)\n+\t\t\treturn dsi->lanes;\n+\t}\n+\tdev_dbg(&dsi->dev, \"lanes: %d\\n\", dsi->lanes);\n+\n+\tjadard->reset = devm_gpiod_get(dev, \"reset\", GPIOD_OUT_HIGH);\n+\tif (IS_ERR(jadard->reset))\n+\t\treturn dev_err_probe(&dsi->dev, PTR_ERR(jadard->reset),\n+\t\t\t\t\"failed to get our reset GPIO\\n\");\n+\n+\tjadard->vdd = devm_regulator_get(dev, \"vdd\");\n+\tif (IS_ERR(jadard->vdd))\n+\t\treturn dev_err_probe(&dsi->dev, PTR_ERR(jadard->vdd),\n+\t\t\t\t\"failed to get vdd regulator\\n\");\n+\n+\tjadard->vccio = devm_regulator_get(dev, \"vccio\");\n+\tif (IS_ERR(jadard->vccio))\n+\t\treturn dev_err_probe(&dsi->dev, PTR_ERR(jadard->vccio),\n+\t\t\t\t\"failed to get vccio regulator\\n\");\n+\n+\tret = of_drm_get_panel_orientation(dev->of_node, &jadard->orientation);\n+\tif (ret < 0)\n+\t\treturn dev_err_probe(dev, ret, \"failed to get orientation\\n\");\n+\n+\tret = drm_panel_of_backlight(&jadard->panel);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tjadard->panel.prepare_prev_first = true;\n+\n+\tdrm_panel_add(&jadard->panel);\n+\n+\tmipi_dsi_set_drvdata(dsi, jadard);\n+\tjadard->dsi = dsi;\n+\tjadard->desc = desc;\n+\n+\tret = mipi_dsi_attach(dsi);\n+\tif (ret < 0)\n+\t\tdrm_panel_remove(&jadard->panel);\n+\n+\treturn ret;\n+}\n+\n+static void jadard_dsi_remove(struct mipi_dsi_device *dsi)\n+{\n+\tstruct jadard *jadard = mipi_dsi_get_drvdata(dsi);\n+\n+\tmipi_dsi_detach(dsi);\n+\tdrm_panel_remove(&jadard->panel);\n+}\n+\n+static const struct of_device_id jadard_of_match[] = {\n+\t{\n+\t\t.compatible = \"anbernic,rg-ds-display-bottom\",\n+\t\t.data = &anbernic_rgds_display_desc\n+\t},\n+\t{\n+\t\t.compatible = \"anbernic,rg-ds-display-top\",\n+\t\t.data = &anbernic_rgds_display_desc\n+\t},\n+\t{\n+\t\t.compatible = \"chongzhou,cz101b4001\",\n+\t\t.data = &cz101b4001_desc\n+\t},\n+\t{\n+\t\t.compatible = \"kingdisplay,kd101ne3-40ti\",\n+\t\t.data = &kingdisplay_kd101ne3_40ti_desc\n+\t},\n+\t{\n+\t\t.compatible = \"melfas,lmfbx101117480\",\n+\t\t.data = &melfas_lmfbx101117480_desc\n+\t},\n+\t{\n+\t\t.compatible = \"radxa,display-10hd-ad001\",\n+\t\t.data = &cz101b4001_desc\n+\t},\n+\t{\n+\t\t.compatible = \"radxa,display-8hd-ad002\",\n+\t\t.data = &radxa_display_8hd_ad002_desc\n \t},\n \t{\n \t\t.compatible = \"taiguanck,xti05101-01a\",\n \t\t.data = &taiguan_xti05101_01a_desc\n \t},\n+\t{\n+\t\t.compatible = \"waveshare,3.4-dsi-touch-c\",\n+\t\t.data = &waveshare_3_4_inch_c_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,4.0-dsi-touch-c\",\n+\t\t.data = &waveshare_4_0_inch_c_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,8.0-dsi-touch-a\",\n+\t\t.data = &waveshare_8_0_inch_a_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,9.0-dsi-touch-b\",\n+\t\t.data = &waveshare_9_0_inch_b_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,10.1-dsi-touch-a\",\n+\t\t.data = &waveshare_10_1_inch_a_desc\n+\t},\n+\t{\n+\t\t.compatible = \"waveshare,10.1-dsi-touch-b\",\n+\t\t.data = &waveshare_10_1_inch_b_desc\n+\t},\n \t{ /* sentinel */ }\n };\n MODULE_DEVICE_TABLE(of, jadard_of_match);\n",
    "prefixes": [
        "14/19"
    ]
}