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{ "id": 2218378, "url": "http://patchwork.ozlabs.org/api/patches/2218378/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260401064256.152228-1-naveen.siddegowda@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401064256.152228-1-naveen.siddegowda@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-01T06:42:56", "name": "[Aarch64] : Use fmov for some low-lane FP SIMD constant vectors [PR113856]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1ea6ea18484894ea1a6f353ddc08dbb09486904c", "submitter": { "id": 93028, "url": "http://patchwork.ozlabs.org/api/people/93028/?format=api", "name": "Naveen", "email": "naveen.siddegowda@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260401064256.152228-1-naveen.siddegowda@oss.qualcomm.com/mbox/", "series": [ { "id": 498280, "url": "http://patchwork.ozlabs.org/api/series/498280/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=498280", "date": "2026-04-01T06:42:56", "name": "[Aarch64] : Use fmov for some low-lane FP SIMD constant vectors [PR113856]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498280/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218378/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218378/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], 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Mar 2026 23:43:10 -0700 (PDT)" ], "From": "Naveen <naveen.siddegowda@oss.qualcomm.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "Naveen <naveen.siddegowda@oss.qualcomm.com>", "Subject": "[PATCH] [Aarch64]: Use fmov for some low-lane FP SIMD constant\n vectors [PR113856]", "Date": "Tue, 31 Mar 2026 23:42:56 -0700", "Message-Id": "<20260401064256.152228-1-naveen.siddegowda@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAxMDA1NyBTYWx0ZWRfX4abLux2pZHGw\n HpdD1qdjFC6Smqdsr9zYPw19QJpVltNDzcPHoOnjRav9KMkEIYUqhWGYVVRSMpwBpChlAGpg8CF\n JWSj9ts2gA6xsVNNnhGq9og4ToWOHd+MDiQGNfBj44Tbm3BiubEzPTPMRiCQJaCD98yrl6EdmNQ\n fLj4I2GxefCCHIZXsbtrMuqImNWIe4fXW36AiphAtsex7fv7q7injTo/QQSPAT4/1AN067mnVBN\n dFB3he7po7wNZ45D3va06vdXs5BGcqu1h4vI05d05yg7OHwn7no9nU49L1BbQVRrrFLUAj3kfHe\n e9ucFlPTgVdYJQ1eVhL/qDxP8tLD9k2J9qRHq3jpXCLu5WeKqsEyfxgse+82b+sj+R4gjVfIr5W\n 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authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604010057", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Extend AdvSIMD constant materialization to recognize vectors where only\nthe low element is a representable floating-point constant and all other\nelements are zero.\nBootstrapped and tested on aarch64-linux-gnu.\n\nPR target/113856\n\ngcc/ChangeLog:\n\n * config/aarch64/aarch64-protos.h\n\t (aarch64_output_simd_mov_imm_low): New.\n\t (aarch64_const_vec_fmov_p): New.\n\t* config/aarch64/aarch64-simd.md (mov<mode>): Do not expand constant\n\tvectors handled by aarch64_const_vec_fmov_p into VDUP.\n\t(*aarch64_simd_mov<VDMOV:mode>): Add Dc alternatives for FMOV based\n\tSIMD constant moves.\n\t(*aarch64_simd_mov<VQMOV:mode>): Likewise.\n\t* config/aarch64/aarch64.cc (aarch64_const_vec_fmov_p): New function.\n\t(aarch64_output_simd_mov_imm_low): New function.\n\t* config/aarch64/constraints.md (Dc): New constraint.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.target/aarch64/pr113856.c: New test.\n\nSigned-off-by: Naveen SiddeGowda <naveen.siddegowda@oss.qualcomm.com>\n---\n gcc/config/aarch64/aarch64-protos.h | 2 +\n gcc/config/aarch64/aarch64-simd.md | 5 +-\n gcc/config/aarch64/aarch64.cc | 77 +++++++++++++++++++++\n gcc/config/aarch64/constraints.md | 7 ++\n gcc/testsuite/gcc.target/aarch64/pr113856.c | 67 ++++++++++++++++++\n 5 files changed, 157 insertions(+), 1 deletion(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/pr113856.c", "diff": "diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex 3f359b0069d..b172263a9ae 100644\n--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -952,8 +952,10 @@ char *aarch64_output_simd_and_imm (rtx, unsigned);\n char *aarch64_output_simd_xor_imm (rtx, unsigned);\n char *aarch64_output_fmov (rtx);\n \n+char *aarch64_output_simd_mov_imm_low (rtx *);\n char *aarch64_output_sve_mov_immediate (rtx);\n char *aarch64_output_sve_ptrues (rtx);\n+bool aarch64_const_vec_fmov_p (rtx);\n bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);\n bool aarch64_regno_ok_for_base_p (int, bool);\n bool aarch64_regno_ok_for_index_p (int, bool);\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex c314e85927d..2e142b1e1ee 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -79,7 +79,8 @@\n \t}\n else if (!aarch64_simd_imm_zero (operands[1], <MODE>mode)\n \t && !aarch64_simd_special_constant_p (operands[1], <MODE>mode)\n-\t && !aarch64_simd_valid_mov_imm (operands[1]))\n+\t && !aarch64_simd_valid_mov_imm (operands[1])\n+\t && !aarch64_const_vec_fmov_p (operands[1]))\n \t{\n \t rtx x;\n \t /* Expand into VDUP. */\n@@ -183,6 +184,7 @@\n [?r, w ; neon_to_gp<q> , * , *] fmov\\t%x0, %d1\n [?w, r ; f_mcr , * , *] fmov\\t%d0, %1\n [?r, r ; mov_reg , * , *] mov\\t%0, %1\n+ [w , Dc; fmov , * , *] << aarch64_output_simd_mov_imm_low (operands);\n [w , Dn; neon_move<q> , simd , *] << aarch64_output_simd_mov_imm (operands[1], 64);\n [w , Dz; f_mcr , * , *] fmov\\t%d0, xzr\n [w , Dx; neon_move , simd , 8] #\n@@ -212,6 +214,7 @@\n [?r , w ; multiple , * , 8] #\n [?w , r ; multiple , * , 8] #\n [?r , r ; multiple , * , 8] #\n+ [w , Dc; fmov , * , 4] << aarch64_output_simd_mov_imm_low (operands);\n [w , Dn; neon_move<q> , simd, 4] << aarch64_output_simd_mov_imm (operands[1], 128);\n [w , Dz; fmov , * , 4] fmov\\t%d0, xzr\n [w , Dx; neon_move , simd, 8] #\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 197d4f27269..b6c6c20eb2f 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -24630,6 +24630,83 @@ aarch64_simd_valid_mov_imm (rtx op)\n return aarch64_simd_valid_imm (op, NULL, AARCH64_CHECK_MOV);\n }\n \n+\n+/* Return true if OP is a V2SF constant vector of the form { c, 0 }\n+ or a V4SF constant vector of the form { c, 0, 0, 0 }. */\n+bool\n+aarch64_const_vec_fmov_p (rtx op)\n+{\n+ if (!CONST_VECTOR_P (op))\n+ return false;\n+\n+ machine_mode mode = GET_MODE (op);\n+ scalar_mode inner_mode = GET_MODE_INNER (mode);\n+\n+ if (inner_mode != E_HFmode\n+ && inner_mode != E_SFmode\t\n+ && inner_mode != E_DFmode)\n+ return false;\n+\n+ unsigned int nunits = GET_MODE_NUNITS (mode).to_constant ();\n+ unsigned int const_idx = BYTES_BIG_ENDIAN ? nunits - 1 : 0;\n+\n+ rtx elt = CONST_VECTOR_ELT (op, const_idx);\n+ if (!CONST_DOUBLE_P (elt))\n+ return false;\n+\n+ REAL_VALUE_TYPE r = *CONST_DOUBLE_REAL_VALUE (elt);\n+ if (!aarch64_real_float_const_representable_p (r))\n+ return false;\n+\n+ for (unsigned int i = 0; i < nunits; ++i)\n+ {\t \n+ if (i == const_idx)\n+\tcontinue;\n+\n+ rtx x = CONST_VECTOR_ELT (op, i);\n+ if (!rtx_equal_p (x, CONST0_RTX (inner_mode))\n+\t && !(CONST_INT_P (x) && INTVAL (x) == 0))\n+\treturn false;\n+ }\t \n+\n+ return true;\n+}\n+\n+/* Output a move of either a V2SF constant of the form { c, 0 } or V4SF\n+ constant of the form { c, 0, 0, 0 }. */\n+char *\n+aarch64_output_simd_mov_imm_low (rtx *operands)\n+{\n+ machine_mode mode = GET_MODE (operands[1]);\n+ scalar_mode inner_mode = GET_MODE_INNER (mode);\n+ unsigned int nunits = GET_MODE_NUNITS (mode).to_constant ();\n+ unsigned int const_idx = BYTES_BIG_ENDIAN ? nunits - 1 : 0;\n+ rtx elt = CONST_VECTOR_ELT (operands[1], const_idx);\n+ rtx xop[2];\n+ \n+ xop[0] = lowpart_subreg (inner_mode, operands[0], mode);\n+ xop[1] = elt;\n+\n+ switch (inner_mode)\n+ {\n+ case E_HFmode:\n+\toutput_asm_insn (\"fmov\\t%h0, %1\", xop);\n+\tbreak;\n+\n+ case E_SFmode:\n+\toutput_asm_insn (\"fmov\\t%s0, %1\", xop);\n+\tbreak;\n+\n+ case E_DFmode:\n+\toutput_asm_insn (\"fmov\\t%d0, %1\", xop);\n+\tbreak;\n+\n+ default:\n+\tgcc_unreachable ();\n+ }\n+ return \"\";\n+}\n+\n /* Return true if OP is a valid SIMD orr immediate for SVE or AdvSIMD. */\n bool\n aarch64_simd_valid_orr_imm (rtx op)\ndiff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\nindex 3d166fe3a17..34a30274dbf 100644\n--- a/gcc/config/aarch64/constraints.md\n+++ b/gcc/config/aarch64/constraints.md\n@@ -503,6 +503,13 @@\n (and (match_code \"const_vector\")\n (match_test \"aarch64_simd_valid_xor_imm (op)\")))\n \n+(define_constraint \"Dc\"\n+ \"@internal\n+ A constraint that matches a V2SF constant vector of the form { c, 0 }\\\n+ or a V4SF constant of the form { c, 0, 0, 0 }.\"\n+ (and (match_code \"const_vector\")\n+ (match_test \"aarch64_const_vec_fmov_p (op)\")))\n+\n (define_constraint \"Dn\"\n \"@internal\n A constraint that matches vector of immediates.\"\ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr113856.c b/gcc/testsuite/gcc.target/aarch64/pr113856.c\nnew file mode 100644\nindex 00000000000..8bc632a5bc1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr113856.c\n@@ -0,0 +1,67 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 \" } */\n+/* { dg-additional-options \"-march=armv8-a+fp16\" } */\n+\n+/* Check that V2SF {1.0f, 0.0f } and V4SF {1.0f, 1.0f, 0.0f, 0.0f } are\n+ materialized with FMOV rather than a literal pool load. */\n+\n+typedef float vect64_float __attribute__((vector_size(8)));\n+typedef float vect128_float __attribute__((vector_size(16)));\n+typedef _Float16 vect64_half __attribute__((vector_size(8)));\n+typedef _Float16 vect128_half __attribute__((vector_size(16)));\n+typedef double vect128_double __attribute__((vector_size(16)));\n+\n+vect64_float\n+f1 (float a)\n+{\n+ return (vect64_float) { 1.0f, 0.0f };\n+}\n+\n+vect64_float\n+f2 (float a)\n+{\n+ return (vect64_float) { 1.0f, 1.0f };\n+}\n+\n+vect128_float\n+f3 (void)\n+{\n+ return (vect128_float) { 1.0f, 0.0f, 0.0f, 0.0f };\n+}\n+\n+vect64_half\n+f4 (void)\n+{\n+ return (vect64_half) { (_Float16) 1.0, (_Float16) 0.0, (_Float16) 0.0,\n+\t\t(_Float16) 0.0 };\n+}\n+\n+vect128_half\n+f5 (void)\n+{\n+ return (vect128_half) { (_Float16) 1.0, (_Float16) 0.0, (_Float16) 0.0,\n+\t\t(_Float16) 0.0, (_Float16) 0.0, (_Float16) 0.0,\n+\t \t(_Float16) 0.0, (_Float16) 0.0 };\n+}\n+\n+vect128_double\n+f6 (void)\n+{\n+ return (vect128_double) { 1.0, 0.0 };\n+}\n+\n+/* f1: New case, should use scalar-FMOV based SIMD materialization. */\n+/* f3: V4SF low-half initialized from FMOV form. */\n+/* { dg-final { scan-assembler-times {\\tfmov\\ts0, 1\\.0} 2 } } */\n+\n+/* f2: Existing case, should use scalar-FMOV based SIMD materialization. */\n+/* { dg-final { scan-assembler-times {\\tfmov\\tv[0-9]+\\.2s, 1\\.0} 1 } } */\n+\n+/* f4, f5: V4HF, V8HF initialized from FMOV form. */\n+/* { dg-final { scan-assembler-times {\\tfmov\\th0, 1\\.0} 2 } } */\n+\n+/* f6: V2DF initialized from FMOV form. */\n+/* { dg-final { scan-assembler-times {\\tfmov\\td0, 1\\.0} 1 } } */\n+\n+/* None of them should need a literal pool load. */\n+/* { dg-final { scan-assembler-not {\\tldr\\tq[0-9]+,} } } */\n", "prefixes": [ "Aarch64" ] }