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GET /api/patches/2218334/?format=api
{ "id": 2218334, "url": "http://patchwork.ozlabs.org/api/patches/2218334/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-8-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-8-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:27", "name": "[07/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ssidsize\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c236d2e74260a0fd463af00a884ffd674861efe1", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-8-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218334/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218334/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=iFo0SG/2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=1CKyUIMXDzJF5aucpTAwxnQjNq4xMCLeMToE7QIWk0g=;\n b=l3S4gfZQTRdTzZ9AtD1H7FVxOdGH2Gvsv/gWL+Ys8m3SU63vdb14oZOM9ck+x1j4UBhWHjnK3w8oQaeG045QpN4UWfni85Ub8Q3OLLyBmmn+aNlSJ5HQvHA3KfFyWfjufoAIZU7TB/weAXttmjuySf/CaRLdCRMMNMobqnpKeffAyct/iANjLyqeTRwho0i+RwdqL4Ufm/mGKCkJsg7MDLDoQIEPhLqSauNAPngP9hGDJG9qozkTgdSjT9RMj30T5DFqAmdm/3YLtxnY9BRmmPlgFisMQlhIfpkTLaqdVGSqELy+EVJ1zOqXC3RsIX18KaVESeGhmSk5yylGDz0nNA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=1CKyUIMXDzJF5aucpTAwxnQjNq4xMCLeMToE7QIWk0g=;\n b=iFo0SG/2rwv4hSM16ukxPH4Kos84+oW8s93r274PePS3bNM06nBZH/Vr+P+GhdBenPVik08Ihl1oRjc/k6h16MspKPm6DGxFT/U7JbzkrHef2++Ma+LAxY2kWFZzUTQVrtnAwJf5DX14hwKAILUwNgNIsSh7MyTX97H5l/NWAJK6PKFhApQR2+hN4OJ7KsN6iB+jRd+jqtyZ9zxxOK3JTQ3tOdodOlx2jZCzyMIKl24jmSgTRfvMBoy0oL6F6prGay4uBtsuJ1Th+T0lm2F49b/x/aMg+1LqKor616k1iq2BMtkYCYPL0Q5VAr4maHh/7oSTNgWkFmyA5rLa3YCWIQ==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 07/11] hw/arm/smmuv3-accel: Implement \"auto\" value for\n \"ssidsize\"", "Date": "Tue, 31 Mar 2026 18:02:27 -0700", "Message-ID": "<20260401010231.4166776-8-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BY5PR20CA0032.namprd20.prod.outlook.com\n (2603:10b6:a03:1f4::45) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0e5faa3e-37c9-454c-1df6-08de8f8a63a4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n CuqAhJkl0xHhBIfTQz34ZqCTxjMj+nQ4qhmV/W/O8JTbu9pRC3x4npgsxkMC/ya8uewyhZgMwoBFJ1OF3MKKq7IGHpjwOTE9jEpOJS4VYXaTEaAQzOmk6dh8yd0wAS2ifEMSixZxgyeNbSmvFU/8UO2C37QWPPV208XSAgmdZa1e7vV+3cjWBIFQHeVyqXgcVnXpmEepnSg450OoUed4tdxF55lb2V1l5vK6nPeIb4O+TbQfINT+TKI8GP/S4vvZoKjZ0mWr5Kzdpw2uj6/6p+DZY7bfgLSIjqj2rVNvOXFHLyH+Ue7d3KgornC9UKMRqV9oD9Q4XK3yARCB981xQN5ZkiljIQL96d2QTj15WN1s8MwPTkEKy7SKReYkmqpDlmbLhdQ6h+18rS+jPe/8Vr8+d9IY+qpeODweOsD/aYN8ZiW3G943WVCiXlxJJXdJwe5mUQbcXoZJDGUEJ7jfLubHPH7BArIpGoCKWLFUlk72pknbf/FNz7mLmIaidwUTTUBuPI79VFfKyq9mTuozaqJcx438zGWcsT8UrlzIPSLvscut25GerS+CfrS3TLUUR8sOmSE3PfUlauq3DAAzNxYId346faKNCrBtVbdgpp3yHZtPouLhW1g65UzHCnjvwugU8onS/HEj4gJVnQmCbnDUVJa3sVRGjIxrNHbRIb8NPrIYLGPUR+iHMmMUI+6p5X/0EnPgBDJDShDT0BBM1bEhR2hcvC58pj97e6AwbWQ=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using IOMMU_GET_HW_INFO,\nretrieving SSID size from IDR1. When the auto SSID size is resolved\nto a non-zero value, PASID capability is advertised to the vIOMMU\nand accelerated use cases such as Shared Virtual Addressing (SVA)\nare supported.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 14 ++++++++++++--\n hw/arm/smmuv3.c | 11 +++++------\n 2 files changed, 17 insertions(+), 8 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 9e7ec6a930..03393fd7ba 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -56,6 +56,13 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[3], IDR3, RIL));\n }\n \n+ /* Update SSIDSIZE if auto from info */\n+ if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n+ /* Store for get_viommu_flags() to determine PASID support */\n+ s->idr[1] = FIELD_DP32(s->idr[1], IDR1, SSIDSIZE,\n+ FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -828,7 +835,9 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opaque)\n SMMUState *bs = opaque;\n SMMUv3State *s = ARM_SMMUV3(bs);\n \n- if (s->ssidsize > SSID_SIZE_MODE_0) {\n+ if (s->ssidsize > SSID_SIZE_MODE_0 ||\n+ (s->ssidsize == SSID_SIZE_MODE_AUTO &&\n+ FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) {\n flags |= VIOMMU_FLAG_PASID_SUPPORTED;\n }\n return flags;\n@@ -952,7 +961,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n smmuv3_accel_as_init(s);\n \n if (s->ats == ON_OFF_AUTO_AUTO ||\n- s->ril == ON_OFF_AUTO_AUTO) {\n+ s->ril == ON_OFF_AUTO_AUTO ||\n+ s->ssidsize == SSID_SIZE_MODE_AUTO) {\n s->s_accel->auto_mode = true;\n }\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 74cc81ae32..67c499d22b 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -627,7 +627,10 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,\n }\n \n /* Multiple context descriptors require SubstreamID support */\n- if (s->ssidsize == SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) != 0) {\n+ if ((s->ssidsize == SSID_SIZE_MODE_0 ||\n+ (s->ssidsize == SSID_SIZE_MODE_AUTO &&\n+ !FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) &&\n+ STE_S1CDMAX(ste) != 0) {\n qemu_log_mask(LOG_UNIMP,\n \"SMMUv3: multiple S1 context descriptors require SubstreamID support. \"\n \"Configure ssidsize > 0 (requires accel=on)\\n\");\n@@ -1973,10 +1976,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n- error_setg(errp, \"ssidsize auto mode is not supported\");\n- return false;\n- }\n if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {\n error_setg(errp, \"QEMU SMMUv3 model only implements 44 and 48 bit\"\n \"OAS; other OasMode values are not supported\");\n@@ -2197,7 +2196,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\n \"Valid range is 0-20, where 0 disables SubstreamID support. \"\n \"Defaults to 0. A value greater than 0 is required to enable \"\n- \"PASID support. ssidsize=auto is not supported.\");\n+ \"PASID support.\");\n }\n \n static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu,\n", "prefixes": [ "07/11" ] }