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GET /api/patches/2218333/?format=api
{ "id": 2218333, "url": "http://patchwork.ozlabs.org/api/patches/2218333/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-11-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-11-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:30", "name": "[10/11] hw/arm/smmuv3: Change the default oas to match the host", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a52c3d318bceadefdbf72fdc98f69c3a31c40bfa", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-11-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218333/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218333/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=dES8I0Vy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=LoFdal64FHyXKqtIyH3+rBVT33AyJXXXAxuQAq3z/Qs=;\n b=YbbVMjHW7/OD53FhMe1Qt74uYBBuf2Gq3zz8Fl4WHakDy9xa7vHdMuauKhQ1VxUnzabmH7moeuakOltsMIXP1RLt3T494RwBLVFOG5MD74gq/rPLy3nfhK7aCCcwFS5F4CsGfqCWjfXn5FuC8LztpH5k90xyKezv6CeYRiSJbV9IZqnoxNZVYYnvEolbP1NPTTU8LpFjInYN/HO0KZOQEXZ+DbCSj5NhwsQ9il9Ax3gs0ONGcfytH2DNVQd4qWJTAuN6p64t85a2yY0w6J9O6oxxHYoIJF316qzoizI4otUsTK4TTiLiEkIsZ0mm1QYwwNhFRKzLn7PJZ/Z3VRh3VQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=LoFdal64FHyXKqtIyH3+rBVT33AyJXXXAxuQAq3z/Qs=;\n b=dES8I0VySzmU/TmM5zWaaMR+H2YEl545tN5PEFEUE28ipuLY91IgwCIQEK7dJlm5DPHtYn5hBGX/BkI9QmHu19NI4DCGpueoFqTxMqaS4RPum1gyh2LMTaYDI8zDe7pF7JkQwb0ymfA2u9b3sw5/2r2suPBwZYPqRyz2ckIUw37XRvqOp5YIO3oXZ018LRNZCCIueGUd5DV58Zeh6J2hVR9HBcr1fmE2IZxy8XXZMhVTEbn6K/ImmwdEEIyvIqc4mBIIDnOJJ1w8stBGcRE49bD8Wp3ypSNh/SWOYcBT3YQAvD30qreSXunNwLixKSd1peLyk6QZNj8vtMmqyVW/yw==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 10/11] hw/arm/smmuv3: Change the default oas to match the host", "Date": "Tue, 31 Mar 2026 18:02:30 -0700", "Message-ID": "<20260401010231.4166776-11-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ2PR07CA0010.namprd07.prod.outlook.com\n (2603:10b6:a03:505::27) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|IA1PR12MB6626:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d923dc0e-d9bf-4cfa-a31d-08de8f8a66e5", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|376014|366016|7416014|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n N48SjpCeacCYHELNgl/RbChKXQUNQqDuHQIGR/GVhMwS4bndcoMFdcqJy8DSjhc65VHBsUO+BcGgcWPj9W6TsTtJkLtgH7r4KBWjLKSSiFB5ULqwEEEqMkMfoGn/NkqrGWgQ11qdkgjQvWPhqlha1nB38aRVA/XesjDGde8dyodueebb3Q3IXNXPrwcYGXCxghDPozo6rU/wBSzPGPBAZZqFsyfvf/6Otkaw+t3KadqqfwDgp2GPRChlnY39PCpF68o2f0DqpJsMb5arhBb7c1ZOUYykk+RfD4efrabCPW630E57EM7CrZwnU0wAefHNEMJV7aETTlLWY3IanKMNUdptw6bxzTzxJlvIl8zy4//aCXmB+xK9CRE7yzOCxrHbwvsi66cNHqOcYOAEGdYRQHJJeREptuCQOBT8ykGHWbz95VtQwhdleMK87fm6rnfQpiGOuMvO0uov5W+tVnOID1Qpx3vHeH15eO1jA06nVk98wd6XUPsiXViweVUmLXAMofxmMf5oSrvB/sg/HymZSE+aQHk2YjQlqwqI2noGEieauBjy9c1HjhBxVWoV0YYipntUjt9aTZ6T/T52dKh5D8LJE4osFWk0eWVNVBRAouMSl8FmjTtxOumr37QhuqmfiKpbSPEoSe0Tl3X4ySAHJfk74p+v9dvyX3p0XAV0XgAL6Tadf1L5Wg3Pp4gG4g1yySWrcn1FXhQnd8UpZJyPEHuJJ88BrGPmgknxFs1ogsU=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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The default Output Address Size used\nto be 44-bit, but we change it to match what the host IOMMU properties\nreport so that users do not have to introspect host IDR5 for the OAS.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3.c | 4 ++--\n hw/core/machine.c | 1 +\n 2 files changed, 3 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 0ab6d1e762..7d537b7947 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -2155,7 +2155,7 @@ static const Property smmuv3_properties[] = {\n /* RIL can be turned off for accel cases */\n DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_AUTO),\n DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_AUTO),\n- DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_44),\n+ DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_AUTO),\n DEFINE_PROP_SSIDSIZE_MODE(\"ssidsize\", SMMUv3State, ssidsize,\n SSID_SIZE_MODE_AUTO),\n };\n@@ -2190,7 +2190,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"platform has ATS support before enabling this.\");\n object_class_property_set_description(klass, \"oas\",\n \"Specify Output Address Size (for accel=on). Supported values \"\n- \"are 44 or 48 bits. Defaults to 44 bits.\");\n+ \"are 44 or 48 bits. Defaults to auto.\");\n object_class_property_set_description(klass, \"ssidsize\",\n \"Number of bits used to represent SubstreamIDs (SSIDs). \"\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\ndiff --git a/hw/core/machine.c b/hw/core/machine.c\nindex aa208a2d9a..a668bb2ec3 100644\n--- a/hw/core/machine.c\n+++ b/hw/core/machine.c\n@@ -43,6 +43,7 @@ GlobalProperty hw_compat_11_0[] = {\n { TYPE_ARM_SMMUV3, \"ats\", \"off\" },\n { TYPE_ARM_SMMUV3, \"ril\", \"on\" },\n { TYPE_ARM_SMMUV3, \"ssidsize\", \"0\" },\n+ { TYPE_ARM_SMMUV3, \"oas\", \"44\" },\n };\n \n GlobalProperty hw_compat_10_2[] = {\n", "prefixes": [ "10/11" ] }