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GET /api/patches/2218332/?format=api
{ "id": 2218332, "url": "http://patchwork.ozlabs.org/api/patches/2218332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-6-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-6-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:25", "name": "[05/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b5a91bd605a338d92973c8fa00ec9c62d566b814", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-6-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218332/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218332/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=TK3mivj3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=6aySk0OJTchi+yg9EwJ87Trx5A1gAhiHymmBSpQO1j8=;\n b=P5pQYkM5prMQ7HLXuyYwxFtC3DpZIOsg7KmGjXFS4PdP79xsZaHGHAHvAXgpgT9+8zCRvQhTfD0Bk13b+3ef8dS/DbyHhnBvLPdwHfWfzUlI/SNDIFqyYbZpoJKpHnZhbiWxVZGL6hKV8p0DF4b8tvWGr7oCb9jJYx5+/GXgvEUsKEG9esaU8g/QuQYKFzGn8QbPAMAVKCRh0xMoxheUwS9Tfpb7KlH7f+dN8OrupXDBLwVYman7+jKy5ZlIflkI+97pD+1I7MwVKJSLPUEtkiJ34Anfk1cGD2Tny+ymaF2aM5yhZP16PXlFjS941vIMaMG1ZlLsvf8XRodl986vow==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=6aySk0OJTchi+yg9EwJ87Trx5A1gAhiHymmBSpQO1j8=;\n b=TK3mivj3LLs2ce0DucuyX+hDJyClfZRI22ca/OPzTdkF4wWszCEMuIni5eBwhoMNSKwuEU9qG+yijgoTwKAa4QtAhVsbee8scy8PFz/8G1wvozhr53LGctp8nFmI8zBwpJ/SFaeAsl8qyWmWz6ZtIBHCCkFjE8kQXzLRpvrRDtz9o7fQhv269MWNwLabtKhbc44FDlczdQvOdi/WxnUyGhJz7KBEujct37LtX06zxSKjnn0aWbV2odFfONmfzwnz48AgVMu/CF96JDMFRGuGfOvAnucdQ4Z0nqytVMKwP2eUNVufYUP1JehVxr2oIMDbD9mvli3TQzNbFkf69kDErQ==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 05/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ril\"", "Date": "Tue, 31 Mar 2026 18:02:25 -0700", "Message-ID": "<20260401010231.4166776-6-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ2PR07CA0011.namprd07.prod.outlook.com\n (2603:10b6:a03:505::20) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "fa383eba-d1ab-429f-a337-08de8f8a61a5", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n dsaI0HjAuVEmqDRmDoi5PcI0SPy9ZkJ/uDJgbLwA81i6s5MuTQ0JISAGp0uewHcq02It7v0zHlq/Rwfd4HR3WANgJyJRwEaBvfYcPGfvt/7pQFTZ7onK6GKwyrlSjw0aL3pqbHXi4X3RP2f/ArsYY9pYQ4PIsTCQV5s9tJ+XfjINp9WtWgW4RbdzdBMY2Hx8FZM4/8lXL9Q1F0WsbnD/cPZg7MH2lZMt4g5r3icTIuxWdcMH4cY52UNo9Y7aLswgVgOrA551XxZpbNNJEAwe8NNUFpCpsZqfkqGEoSU3USBZp6dn/CSR3/LGqHIy34izJfVpigDbmJI5x2x2jawVLePaLRDyhXkwtlTFmsSmB/mifbc935yhtbzs+yG/brkI+nHJCN99Gh2WuSWtFLiwSN8jrZwZY20WIJrWX1AO0N9Je9nt1AMqb1UUTSIt2Jul6ozOziGVk/z39zh2dzUsSBlSALz0Tbc0cVyxnWxwjlvJzZDp/eLW6WyTvMSIez9Fr49r4uxwZinKkk4NGsif+Y5tIKlH9l/2+v8LlYKZwHR8cAXdOOGoxPaJY5Dp2pgsyMy3SgJFg+9uTAke6gVaZ/pgcEm8NQvOUxHDL+6XCmZ/tjz1athMlptTlA2ppL+mJh50UcaPvbjiRB7ClQjfCzXUWC7yj+kREH89Mx3bzXLWVx9mlqAaFlU14WLSsF4boZ5S0/zXANNbvNjNaiNu3FJcox34y3mjxEtNBXbbSXE=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using\nIOMMU_GET_HW_INFO, retrieving RIL capability from IDR3.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 9 ++++++++-\n hw/arm/smmuv3.c | 7 +------\n 2 files changed, 9 insertions(+), 7 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex a835c8f220..9e7ec6a930 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -50,6 +50,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[0], IDR0, ATS));\n }\n \n+ /* Update RIL if auto from info */\n+ if (s->ril == ON_OFF_AUTO_AUTO) {\n+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL,\n+ FIELD_EX32(info->idr[3], IDR3, RIL));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -945,7 +951,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n \n- if (s->ats == ON_OFF_AUTO_AUTO) {\n+ if (s->ats == ON_OFF_AUTO_AUTO ||\n+ s->ril == ON_OFF_AUTO_AUTO) {\n s->s_accel->auto_mode = true;\n }\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex f353865187..a2d2f0e3bc 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1973,10 +1973,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ril == ON_OFF_AUTO_AUTO) {\n- error_setg(errp, \"ril auto mode is not supported\");\n- return false;\n- }\n if (s->ssidsize == SSID_SIZE_MODE_AUTO) {\n error_setg(errp, \"ssidsize auto mode is not supported\");\n return false;\n@@ -2188,8 +2184,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Enable SMMUv3 accelerator support. Allows host SMMUv3 to be \"\n \"configured in nested mode for vfio-pci dev assignment\");\n object_class_property_set_description(klass, \"ril\",\n- \"Disable range invalidation support (for accel=on). ril=auto \"\n- \"is not supported.\");\n+ \"Disable range invalidation support (for accel=on).\");\n object_class_property_set_description(klass, \"ats\",\n \"Enable/disable ATS support (for accel=on). Please ensure host \"\n \"platform has ATS support before enabling this.\");\n", "prefixes": [ "05/11" ] }