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GET /api/patches/2218330/?format=api
{ "id": 2218330, "url": "http://patchwork.ozlabs.org/api/patches/2218330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-3-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-3-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:22", "name": "[02/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ats\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5fa029665c4c8f4b1f44afb196361fdefbdb8f2e", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-3-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218330/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218330/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=SFk22OUy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=asJ++HujhCYmlgrxevq5JAeO4nXpw9UTaCt/Te75i2Y=;\n b=CzhssPaY/B41GIunKBlFVeYYUxcQd4N9R8uDZGy/aKyExy3woLeKb9aJ6rXWLiAW/SxW/F7+77BVDOBjAvqYyUo7cmfs3AQ2x6NWgCrGFebbqmFacRfPuiZbCZrHN6vGu+lRaGsEIJK2Z9SAhnTNk00OSrLOWNOBks79t+vjm3Sb4VBlBF+9r4TkOR3olq6zOaoQpasUtSl92k6UeG61rWbI7RG1Duz/23Nl1CvCyCQufeRmaEpulBBlB0gGDZhXi2Bgkoe98GarPxf0n9Ni4LitfhhARS3WUix5wPBQHvUaczKaCDVmQU5cTr47dnjU3B+/lLFpr3aKY0Upv9HrdA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=asJ++HujhCYmlgrxevq5JAeO4nXpw9UTaCt/Te75i2Y=;\n b=SFk22OUyefzj9w+o0LeAedsPbEaHYpfyQrm9YAFrRcy09EUuEyT92syG43l2VQbyAXyNgAfjBm7zCYkDviOxPyyiZ6NQruimjyKlLfNIPNXWsjBKVg4KSgEMUFwCBG/KKMhelrtzAyAwSiP4mkTgxGpMCL3G+pUcvIrvZNgaAA9zsQ2+dYdsRbK7DCKNKiADWE02JOaSuwlucDWqaLPo3bw6jVQEQRj8mJW3QajFND0F4LSk84uCWAG6sqxmuHmUgPmKTsNTW2q1Qk6NqXSaocc8I5PRnTX4/ROjEFORRA5MF2nY5gFwQP5IdwD1cWOsX/OwB7iqWKHsZsEcmVmuaw==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 02/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"ats\"", "Date": "Tue, 31 Mar 2026 18:02:22 -0700", "Message-ID": "<20260401010231.4166776-3-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ2PR07CA0017.namprd07.prod.outlook.com\n (2603:10b6:a03:505::17) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "585d2132-2368-445e-15f4-08de8f8a5e58", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n bseVslCo216q+7DoO3MaSPz6XqketOILbXJnEy9D6UGjMMaYCoeg6Zg6OItwYR3kDI4ZpU9fplXthMVCmzIznJN5xKyDiVez2sYto5gVjzX2ZtTFK2d77yeHTGkJZwH5sT3NRbz4lhrRBbyhgyavuP9yjhtUVt13hY+1hGVWNgM3yx/R5zfxm3CjlRrkR4BDfncT6woUGewLPIhbcsYDlUT2+Hb2ITeypTuOLZktlidtN5TFTWrjqHzVGXT8jcaVTkNSCDzhWOQLonR4q35FcxZ0NuS3vCYkNfCj6326QZs0aTIvKm+jP8P4kenSxYhm2bBXw9RxypC9gwykjEo5hc4siuLSmapxUiIAvbh0Jl0F5kkkdJZk1AOJTq0U51d8Fm+7YMQU2uANQzqKeRfW1TNjYCjlv9NmK+fU3FLQULj4X7nU++zCEZU1Qk5usc8I8EH0/2IQZK4LdYdOv2mtzHuFzdIendHCQ+1SlaVJWIqb3CjrnveWzCIqkU+E3bcWOd6VJJlkVehmc7+7goszmddvDlfFsledNotK4nIAPx2Sxp/swmbeMWkds5C93dAX7t5mNNA+9PJFJMZuydCbnxQ0Ev2MVrgYVzv9VR1M65AI//UbwVXhyBkKP2DjVtV8Ygb/umS2J7ffB1J+fEpfHZL6k4PLa0QFohEt2bsCsJ0NrQvrZd0MriMp89JNJE3Z1dAN0AOXd3M943h8WmrgSVsEQqZx9CUgWM7VNSJP6AM=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using\nIOMMU_GET_HW_INFO, retrieving ATS capability from IDR0.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 10 ++++++++++\n hw/arm/smmuv3.c | 7 +------\n 2 files changed, 11 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex a0146c8d31..a835c8f220 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -44,6 +44,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n return;\n }\n \n+ /* Update ATS if auto from info */\n+ if (s->ats == ON_OFF_AUTO_AUTO) {\n+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS,\n+ FIELD_EX32(info->idr[0], IDR0, ATS));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -938,4 +944,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n s->s_accel = g_new0(SMMUv3AccelState, 1);\n bs->iommu_ops = &smmuv3_accel_ops;\n smmuv3_accel_as_init(s);\n+\n+ if (s->ats == ON_OFF_AUTO_AUTO) {\n+ s->s_accel->auto_mode = true;\n+ }\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 09ea08eb18..f3603554e3 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1973,10 +1973,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->ats == ON_OFF_AUTO_AUTO) {\n- error_setg(errp, \"ats auto mode is not supported\");\n- return false;\n- }\n if (s->ril == ON_OFF_AUTO_AUTO) {\n error_setg(errp, \"ril auto mode is not supported\");\n return false;\n@@ -2196,8 +2192,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"is not supported.\");\n object_class_property_set_description(klass, \"ats\",\n \"Enable/disable ATS support (for accel=on). Please ensure host \"\n- \"platform has ATS support before enabling this. ats=auto is not \"\n- \"supported.\");\n+ \"platform has ATS support before enabling this.\");\n object_class_property_set_description(klass, \"oas\",\n \"Specify Output Address Size (for accel=on). Supported values \"\n \"are 44 or 48 bits. Defaults to 44 bits. oas=auto is not \"\n", "prefixes": [ "02/11" ] }