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GET /api/patches/2218328/?format=api
{ "id": 2218328, "url": "http://patchwork.ozlabs.org/api/patches/2218328/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-7-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-7-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:26", "name": "[06/11] hw/arm/smmuv3: Change the default ril support to match the host", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a1fd8991ffabf86217c6dfba74066e1df62e749f", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-7-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218328/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218328/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=JEwzaj4s;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=7dBj2IM5wVx7ZccbLxxA53xxhQtH+qa5Tb5FKlU+FkU=;\n b=O34CgSiGXDdN7bREdshtVcDj5UucKV/Frt0mNvQUXFF8A+uvQKh2xbrDBED8wSbzzAGMlYQr7fPIQDCQaPDlCaeUwDsjjM62+5Yr25GQozm9p5m8rDi5w/x4ZwqGnJlsTmEpzxDnJAxRYdQJIIdJ8k02bYrDPdpg0xAO38HDIpRofN92pd02MScBfdF8rpTE4ExqNwMQ7z5hPZ6N5DZFSKdT/Ym5oQnc0sj2jr7IQA5hCcUPKgR69ycsB0JaIo/NFiHdWT4M3FiTfEoUSnfPIAHKAMIf3HASzoja1nWPkyoLjQtD/fHLg6FjXwKDGY0MdVx1g9cR3OrybBeShWAfLw==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=7dBj2IM5wVx7ZccbLxxA53xxhQtH+qa5Tb5FKlU+FkU=;\n b=JEwzaj4sLhFMPoIpT8eOeEJLjtesqgBrNotr7bM4enO8DD0S3wuM8XREcMh8u6vVNLGZY7xnMDIWyO0oJ7/58doiVLewmBgozXKRRbz7jvwlsLntojDAKoUjGKJCFN1kI/Wxw7emR2T991gfpTTKVPY0j5krTclbF1Cdi/7R142q2Za0/yVmdzO71FVB3US7uEq4XfIDvanIreaMeratpsYwo6bw0tDBu3ME5SBLpXeE+78Dj0Mj1pEqMy1PWn6MzAIY7i92POsUI6LM1O29zoPcTeLHeJNnLPmexb5PweOaqkLRvtCq+2redIW/MB0dZSty8BRIxpK402a5mm9SDg==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 06/11] hw/arm/smmuv3: Change the default ril support to match\n the host", "Date": "Tue, 31 Mar 2026 18:02:26 -0700", "Message-ID": "<20260401010231.4166776-7-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BY5PR03CA0021.namprd03.prod.outlook.com\n (2603:10b6:a03:1e0::31) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a2b10eb4-4835-4a6b-3426-08de8f8a62a1", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n 8ue1O8W12aUJ69e1fCTy9ya0HWCAuaeDj4LflT6px0rIJoUsl6fmWSooqybbZnzMBZqPyanBqrixKtuRA5Vksy9SlTPQlxKnrhgp/BcjiBnuAD0H8bfjf4uFc0//3a9EPAjeBRyrA5Kt0MQw6LSn6STW93HOUCueUjq0hsGpePFmBkXmOugrEHUfG23zuz5X+ORftO/69bjYai9EDr69sMr0sVvW0oNESRVlgvmjrHhGpbEWwHZp5CVz61oVXukPl/SKK6P3GG4OQyeJpZzLNpFY3+uaZ9hdknc4XsWgTed95Cgi/vGmck3oVP01sSVUhJ46IavU/o7hvDKWiwmgQnQ41TgJKqiWOHYWHZtswgBwmnNnVafy+UP/WZ3M0LZX6iHFYUlTKvrM8d8x2uJnPAINCe2rDTfR3XSShsyJwjsUcpz3L7FYOYHT9syYTfHEELDzceyZ09Vu/lEVKgsYCcWEeOBciO28YfH7+HxQoPtHg0BR8TvTN+epqR5cqtvCN6E92PSfHd6pkwXuTUQ3CajTViptlRtmLL2ioABmMtuhf1QNCa1WhWJlLFFi08huB/EdPeCC9XEaPHpqZ1BeL1EP1CIIiGKZ1PAkalevWvKMGKTvLfiWDoRcInMXIRwC8gCla0zclnrgd7/0TRZKkuCQP1Za8nHmPqqMIqVAHl5fQMBYbY/CmnDVb9W9SvdR53uABnI6l/oQ+Ia28jxCi1vsFyqC1psrf20ZQhGAM+4=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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The default for RIL support used\nto be set to on, but we change it to match what the host IOMMU\nproperties report so that users do not have to introspect host IDR3 for\nRange Invalidation support. Include the previous default for ril in the\n11.0 compat.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3.c | 2 +-\n hw/core/machine.c | 1 +\n 2 files changed, 2 insertions(+), 1 deletion(-)", "diff": "diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex a2d2f0e3bc..74cc81ae32 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -2153,7 +2153,7 @@ static const Property smmuv3_properties[] = {\n /* GPA of MSI doorbell, for SMMUv3 accel use. */\n DEFINE_PROP_UINT64(\"msi-gpa\", SMMUv3State, msi_gpa, 0),\n /* RIL can be turned off for accel cases */\n- DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_ON),\n+ DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_AUTO),\n DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_AUTO),\n DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_44),\n DEFINE_PROP_SSIDSIZE_MODE(\"ssidsize\", SMMUv3State, ssidsize,\ndiff --git a/hw/core/machine.c b/hw/core/machine.c\nindex 6796ab63cc..8f8c26bbe8 100644\n--- a/hw/core/machine.c\n+++ b/hw/core/machine.c\n@@ -41,6 +41,7 @@\n \n GlobalProperty hw_compat_11_0[] = {\n { TYPE_ARM_SMMUV3, \"ats\", \"off\" },\n+ { TYPE_ARM_SMMUV3, \"ril\", \"on\" },\n };\n \n GlobalProperty hw_compat_10_2[] = {\n", "prefixes": [ "06/11" ] }