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GET /api/patches/2218327/?format=api
{ "id": 2218327, "url": "http://patchwork.ozlabs.org/api/patches/2218327/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-10-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-10-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:29", "name": "[09/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"oas\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "54b74133730ff123b9494b210d05bc7f846b6269", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-10-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218327/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218327/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=BLQXnIul;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=WUHoBIjDprUNYARsb32QzIyv8QGHcCNHMsyg0xCShXw=;\n b=J3WSf/+qi/9jipWCwPD3pr35oPIjjPZua2385yyKa/UQKmGt0byd0D4oPpTap/ce3lGpgPH8Jie6m0QJIrRjuEL3Fd/U+EH20ob0/PAOG+vUYv5WUi9ENg/kh3xlWKT1CZ/99ddiAXZL3odJpEM3uROQXsNBao9CHCKq8VmTx63+AXsEo1jmgb4VhQHb3nMcuAnxgojyyZMn5JCMfspjyx/epOdDr7kjmJgm/exmD33lXNUw5/lZfkECq1KTcqKPyrGhiHerIgrv8LAOPAsDTQPNuZKudVvDrCcDFIsGcMzZy2UjA+3Q078HzGW8R5o0xooZXXopwBbdEAJNyHa/2A==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=WUHoBIjDprUNYARsb32QzIyv8QGHcCNHMsyg0xCShXw=;\n b=BLQXnIulJWdoL+QGFwY/wo8Wl7h2hgOyxHkvcaZ8g4qY9nW+tonkWVm6g3oTAUQtwD0IWldi5JpDChOH+2RWdgzNzSniPqpiIkZ0s1aASSEpekWGsbV18hQNdfF4x5Ucm075VhzTXD4f9dwHTUE9ea32OqSJoPRqYVem8/IRUE23amBy9VPLhNDqVQHUKcArJ3yk0b0SgTcRbaKT+AfiO7ep1IcQvlIC2WefsXFft5bTzQiBsyu+9xic01xCTqza3voZy4p0osSHoE6zl1MiLtnkyP6q55snQ0dqxFirMrt7eqwPwBRci95GYUjXyvd0qmrcM6wGGbzZ0+BS+dHbNg==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 09/11] hw/arm/smmuv3-accel: Implement \"auto\" value for \"oas\"", "Date": "Tue, 31 Mar 2026 18:02:29 -0700", "Message-ID": "<20260401010231.4166776-10-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BY1P220CA0007.NAMP220.PROD.OUTLOOK.COM\n (2603:10b6:a03:59d::13) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|IA1PR12MB6626:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6437de2f-b838-4967-374b-08de8f8a65b4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|376014|366016|7416014|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n rA1fzy1QwlncBjGnNIfAkbszjr0w63DSOWk/zN/PlIWMscu1zFE9yS9UbVjmGSKTfhQaYtKcRWB2t9e5cyI+b5ope6952OB0Z9TDIyqALdjXysGb4oPPTYsC/iRoSMifNgjsBYgmNMuiRJmX9y7pWcHTkWN8GKZ4lPjUtU4rgpS9HjdLPhiHOEM4gPZQCO0kgAihKcf4fctiTsTAHrjqGIJEvIs9RkiianjdfS4EORCe1YHw0e0jb/TKburtGvctKeF3WgPuHhtx5ZhBmoqeR4pP9+94ysjwUtIiHUKrhaVjkcLPGY6ZNL7j0MvIWrfITHf4o1db4FKMmzt9tfaxQWmR4OpMCTfCSMUYqF6r61BLc8N6mVrWnlDBzkpvh8/QzDD7swaSk9MJwPDP+1Y5yjomg8Ph+6dLK3S0mJcZ669mhjZas+hSHIZfnnyypu1POGMvjcFqppgmJBNRobW2COj9MWlrxC7jKfiKFJgCzauOiMj8HOLtUTOCE5MWBPJWhdwN4M1Z+edUrmby50gBaO8V1yUQMkbp6t0NN0O9DpLBVG1FnIFSZlD59bEbbBSD8U+4+xOKr8JIwoSdxKU9bc29kJLLCH3+RJmcTeM3GEmoxqxHBtwoA7O7qicX3p44NaOoBh6v1VyjX/d0peni9QcPMCCCy0ZB0fVjCKgMjqRbNw0CEUqzA7gwdBEHI7rO2ZZzS24NPNnFZrl25uJnWIEKz9kpDTT31tetVmwzrvg=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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Derive host values using IOMMU_GET_HW_INFO, retrieving\nOAS from IDR5.\n\nThis keeps the OAS value advertised by the virtual SMMU compatible with\nthe capabilities of the host SMMUv3, so that the intermediate physical\naddresses (IPA) consumed by host SMMU for stage-2 translation do not\nexceed the host's max supported IPA size.\n\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 9 ++++++++-\n hw/arm/smmuv3.c | 6 +++---\n 2 files changed, 11 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 03393fd7ba..105f6d26bf 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -63,6 +63,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n FIELD_EX32(info->idr[1], IDR1, SSIDSIZE));\n }\n \n+ /* Update OAS if auto from info */\n+ if (s->oas == OAS_MODE_AUTO) {\n+ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS,\n+ FIELD_EX32(info->idr[5], IDR5, OAS));\n+ }\n+\n accel->auto_finalised = true;\n }\n \n@@ -962,7 +968,8 @@ void smmuv3_accel_init(SMMUv3State *s)\n \n if (s->ats == ON_OFF_AUTO_AUTO ||\n s->ril == ON_OFF_AUTO_AUTO ||\n- s->ssidsize == SSID_SIZE_MODE_AUTO) {\n+ s->ssidsize == SSID_SIZE_MODE_AUTO ||\n+ s->oas == OAS_MODE_AUTO) {\n s->s_accel->auto_mode = true;\n }\n }\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex cb14a08a66..0ab6d1e762 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1976,7 +1976,8 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n- if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {\n+ if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48 &&\n+ s->oas != OAS_MODE_AUTO) {\n error_setg(errp, \"QEMU SMMUv3 model only implements 44 and 48 bit\"\n \"OAS; other OasMode values are not supported\");\n return false;\n@@ -2189,8 +2190,7 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"platform has ATS support before enabling this.\");\n object_class_property_set_description(klass, \"oas\",\n \"Specify Output Address Size (for accel=on). Supported values \"\n- \"are 44 or 48 bits. Defaults to 44 bits. oas=auto is not \"\n- \"supported.\");\n+ \"are 44 or 48 bits. Defaults to 44 bits.\");\n object_class_property_set_description(klass, \"ssidsize\",\n \"Number of bits used to represent SubstreamIDs (SSIDs). \"\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\n", "prefixes": [ "09/11" ] }