Patch Detail
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Show a patch.
patch:
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Update a patch.
GET /api/patches/2218325/?format=api
{ "id": 2218325, "url": "http://patchwork.ozlabs.org/api/patches/2218325/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-5-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-5-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:24", "name": "[04/11] vfio/pci: Add ats property and mask ATS cap when not exposed", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7f791a041b1e95bda80a940ec74425ab9e610f2b", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-5-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218325/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218325/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=gLSJE1i5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Tue, 31 Mar 2026 21:02:57 -0400", "from DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) by\n CH1PR12MB9647.namprd12.prod.outlook.com (2603:10b6:610:2b0::10) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.17; Wed, 1 Apr\n 2026 01:02:42 +0000", "from DS2PR12MB9567.namprd12.prod.outlook.com\n ([fe80::636:1b52:24ca:d7e5]) by DS2PR12MB9567.namprd12.prod.outlook.com\n ([fe80::636:1b52:24ca:d7e5%3]) with mapi id 15.20.9769.015; Wed, 1 Apr 2026\n 01:02:42 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=NaxJ5H8eDxWeFvid8+UKhbgpnnCmMOUERDLcxX/7H5dveghzB8qFhy4DAkzbEaIXAKnRaT7iEE29sdK7w6S0cdklyKRfOqIaYNBMnJJDJUsBbsahcRrRz5aJLYMpYOcK6Z/m2hFeridGH074bDPaJWmpTqK0KsYEeoeQg+t+cJ4iSp4crfCftDXES27fsUtxTqCQjuOum0VQ+5YIIntn5DwCH8E9mhdGsQbGXHUOib7MqiFDnIxqefQ53O1Gf4k9B/O+URpsa3s5ejaz7jbBM7h4TQ1RmWlCIdUw3EhkDjZr+HpRiMe253SH3G0T5sqVZXNPxo/tirbvXyr7I41slg==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=PuQI7z3NsOxpkKRptWijvCAUccDmjyqmCCM/xxp03qw=;\n b=vr+UY+Dqe69k4iWsnH6Jji4zJ7ywQG2N4HlrJIN9f0GjdXkA05+iyYv9aFyWLENsicDiJ3VxydoN3vJebDb+VYdyMPs7e3M9EAuyQnL9G07evI8kMwEtO4RapCwZH1T5H9LGPKH64Y2xt3p2f2ypfxcOtM8JVm8kYZI0azradgSXYQh6OIl0PTSzrF20dhjcCMYGMDmDqhEH+Jeu1rGudfX9xKUzlIl2xyd79y57124C0AJNJ4aW/tJORkc6kx1tYXMVjUTj3ifAMNKqpU6kBGBgPJb+IgJWUCELYkk0Igt+qr91cNQmKuUKKRFHxyVPAODLicG5GRhKgFV/fqB4cg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=PuQI7z3NsOxpkKRptWijvCAUccDmjyqmCCM/xxp03qw=;\n b=gLSJE1i5YkP9jspoHXG37WYZUHLW38UPqijMU+ochKPdWilMATwpnrwDxd0tvGx+gwFdk5WmCWlwEvxAJ650/fWvePHedYhhyp0mqL2Zo06XlImxLdljqwIfogZ1kqBdGdmH4nvSIzietD30XuC1k2hq7DE6gl6IpdAr51iFRHn5rSCYxvFRGpmWELG76wb/6oom9T52AlFsHAwJrIrEVLD7ImQPmKSNx0qbgqZNK6b6R6hROJz5/tWtzeQJoZWVDMh34vJjYxuWA2nA7NcY/LMXTsRRkN6nX/ztW4sfZ/8siO/Bvsz7CNPDIdeLhso5D10yxBS0JuccORu72rJC/A==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 04/11] vfio/pci: Add ats property and mask ATS cap when not\n exposed", "Date": "Tue, 31 Mar 2026 18:02:24 -0700", "Message-ID": "<20260401010231.4166776-5-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ2PR07CA0007.namprd07.prod.outlook.com\n (2603:10b6:a03:505::12) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "33273364-cc49-4ab6-dbb1-08de8f8a6088", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n qJrCcfEh1/m4d9FJjzZ9RkzYH9e85IWOKwL8DyQ/ZJX2lHAtMl+8Q7p7dr6pTpvhLqJfYeRhWNoL/xnVoFhndNj1UeBzFSmBuLluRGsbkjnEsMkHFdNc1ydAY00l4Lzq3jC54O3J1gmiPq3gFad685jAe40K2FO/5O6coKBKK1hPejl33SHkPsDqwn6BE8WiBVzaUgxyhrGsI1wHjCSKG6EALbDfcm1CuH3JpNCgQtr4IQvdNB4dRTCbIutz7BeYe4N6nk04qJvlmxRQ/5U6j7wJ7ToS96kG4EEhV3yrYXjeZP7WqNcx/6k/HRg4h8ngMbYWi9WFRNUuH/xf0cjNOmUCQFWh6g80Hk4Ef5jcEwtUPBTnSdnGL/hr3y97bAZBimM93HxmqHqqQypMA1w27r03dUSbw3Yt4WXHXcejPOJyWITUAk1FgU+vdPSsjtEzpghPANTVIGhBrNm9OqB90P5hYdE71sPA8Hk7y1EMvOwyS2uPO8viSi8H7GqEAreDk9dsgBSAP0M2BKRG3sn2RwKmj+gA6vuGuJ7yq/qFfKV3DAAAEgRejac174Z45Zq0Bdky4uGlvt1YHVUvk4z1skmaoYlzt2ztzt5nBqctvNTD9bk0hNgLvPJhixS42s1svTmJzZ9lXTbdOgrbMrHIhvwla0dYLxcefCQtL+qlTya43RU+JOhhs75ZsKaTN2o6GpTkbIR396HPoTrhr5i0iYhK3X1zfx92BpxvtcuLcSQ=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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When the device has an ATS\nextended capability in config space but we should not expose it (ats=off,\nor ats=auto and kernel reports IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED), mask\nthe capability so the guest does not see it.\n\nThis aligns with the kernel's per-device effective ATS reporting and\nallows omitting ATS capability when the vIOMMU has ats=off.\n\nSuggested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n backends/iommufd.c | 15 +++++++\n hw/vfio/pci.c | 63 ++++++++++++++++++++++++++++++\n hw/vfio/pci.h | 1 +\n include/system/host_iommu_device.h | 10 +++++\n 4 files changed, 89 insertions(+)", "diff": "diff --git a/backends/iommufd.c b/backends/iommufd.c\nindex e1fee16acf..52cb060454 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -22,6 +22,13 @@\n #include \"hw/vfio/vfio-device.h\"\n #include <sys/ioctl.h>\n #include <linux/iommufd.h>\n+/*\n+ * Until kernel UAPI is synced via scripts;\n+ * matches include/uapi/linux/iommufd.h\n+ */\n+#ifndef IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED\n+#define IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED (1 << 3)\n+#endif\n \n static const char *iommufd_fd_name(IOMMUFDBackend *be)\n {\n@@ -573,6 +580,13 @@ static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **errp)\n }\n }\n \n+static bool hiod_iommufd_support_ats(HostIOMMUDevice *hiod)\n+{\n+ HostIOMMUDeviceCaps *caps = &hiod->caps;\n+\n+ return !(caps->hw_caps & IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED);\n+}\n+\n static bool hiod_iommufd_get_pasid_info(HostIOMMUDevice *hiod,\n PasidInfo *pasid_info)\n {\n@@ -595,6 +609,7 @@ static void hiod_iommufd_class_init(ObjectClass *oc, const void *data)\n \n hioc->get_cap = hiod_iommufd_get_cap;\n hioc->get_pasid_info = hiod_iommufd_get_pasid_info;\n+ hioc->support_ats = hiod_iommufd_support_ats;\n };\n \n static const TypeInfo types[] = {\ndiff --git a/hw/vfio/pci.c b/hw/vfio/pci.c\nindex 1945751ffd..2d408e1d9a 100644\n--- a/hw/vfio/pci.c\n+++ b/hw/vfio/pci.c\n@@ -49,6 +49,10 @@\n #include \"system/iommufd.h\"\n #include \"vfio-migration-internal.h\"\n #include \"vfio-helpers.h\"\n+#ifdef CONFIG_IOMMUFD\n+#include \"system/host_iommu_device.h\"\n+#include \"linux/iommufd.h\"\n+#endif\n \n /* Protected by BQL */\n static KVMRouteChange vfio_route_change;\n@@ -2550,10 +2554,53 @@ static bool vfio_pci_synthesize_pasid_cap(VFIOPCIDevice *vdev, Error **errp)\n return true;\n }\n \n+/*\n+ * Determine whether ATS capability should be advertised for @vdev, based on\n+ * whether it was enabled on the command line and whether it is supported\n+ * according to the kernel's IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED bit.\n+ *\n+ * Store whether ATS capability should be advertised in @ats_need.\n+ *\n+ * Return false if kernel enables IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED\n+ * and ATS is effectively unsupported.\n+ */\n+static bool vfio_pci_ats_requested_and_supported(VFIOPCIDevice *vdev,\n+ bool *ats_need, Error **errp)\n+{\n+ HostIOMMUDevice *hiod = vdev->vbasedev.hiod;\n+ HostIOMMUDeviceClass *hiodc;\n+ bool ats_supported;\n+\n+ if (vdev->ats == ON_OFF_AUTO_OFF) {\n+ *ats_need = false;\n+ return true;\n+ }\n+\n+ *ats_need = true;\n+ if (!hiod) {\n+ return true;\n+ }\n+ hiodc = HOST_IOMMU_DEVICE_GET_CLASS(hiod);\n+ if (!hiodc || !hiodc->support_ats) {\n+ return true;\n+ }\n+\n+ ats_supported = hiodc->support_ats(hiod);\n+ if (vdev->ats == ON_OFF_AUTO_ON && !ats_supported) {\n+ error_setg(errp, \"vfio: ATS requested but not supported by kernel\");\n+ *ats_need = false;\n+ return false;\n+ }\n+\n+ *ats_need = ats_supported;\n+ return true;\n+}\n+\n static void vfio_add_ext_cap(VFIOPCIDevice *vdev)\n {\n PCIDevice *pdev = PCI_DEVICE(vdev);\n bool pasid_cap_added = false;\n+ bool ats_needed = false;\n Error *err = NULL;\n uint32_t header;\n uint16_t cap_id, next, size;\n@@ -2603,6 +2650,11 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev)\n pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0);\n pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0);\n \n+ if (!vfio_pci_ats_requested_and_supported(vdev, &ats_needed, &err)) {\n+ error_report_err(err);\n+ err = NULL;\n+ }\n+\n for (next = PCI_CONFIG_SPACE_SIZE; next;\n next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) {\n header = pci_get_long(config + next);\n@@ -2640,6 +2692,16 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev)\n case PCI_EXT_CAP_ID_PASID:\n pasid_cap_added = true;\n /* fallthrough */\n+ case PCI_EXT_CAP_ID_ATS:\n+ /*\n+ * If ATS is requested and supported according to the kernel, add\n+ * the ATS capability. If not supported according to the kernel or\n+ * disabled on the qemu command line, omit the ATS cap.\n+ */\n+ if (ats_needed) {\n+ pcie_add_capability(pdev, cap_id, cap_ver, next, size);\n+ }\n+ break;\n default:\n pcie_add_capability(pdev, cap_id, cap_ver, next, size);\n }\n@@ -3819,6 +3881,7 @@ static const Property vfio_pci_properties[] = {\n #ifdef CONFIG_IOMMUFD\n DEFINE_PROP_LINK(\"iommufd\", VFIOPCIDevice, vbasedev.iommufd,\n TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *),\n+ DEFINE_PROP_ON_OFF_AUTO(\"ats\", VFIOPCIDevice, ats, ON_OFF_AUTO_AUTO),\n #endif\n DEFINE_PROP_BOOL(\"skip-vsc-check\", VFIOPCIDevice, skip_vsc_check, true),\n DEFINE_PROP_UINT16(\"x-vpasid-cap-offset\", VFIOPCIDevice,\ndiff --git a/hw/vfio/pci.h b/hw/vfio/pci.h\nindex d6495d7f29..514a9197ce 100644\n--- a/hw/vfio/pci.h\n+++ b/hw/vfio/pci.h\n@@ -191,6 +191,7 @@ struct VFIOPCIDevice {\n VFIODisplay *dpy;\n Notifier irqchip_change_notifier;\n VFIOPCICPR cpr;\n+ OnOffAuto ats;\n };\n \n /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */\ndiff --git a/include/system/host_iommu_device.h b/include/system/host_iommu_device.h\nindex f000301583..44c56e87bb 100644\n--- a/include/system/host_iommu_device.h\n+++ b/include/system/host_iommu_device.h\n@@ -133,6 +133,16 @@ struct HostIOMMUDeviceClass {\n * Returns: true on success, false on failure.\n */\n bool (*get_pasid_info)(HostIOMMUDevice *hiod, PasidInfo *pasid_info);\n+ /**\n+ * @support_ats: Return whether ATS is supported for the device\n+ * associated with @hiod host IOMMU device, checking if the\n+ * IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED capability bit is set.\n+ *\n+ * @hiod: handle to the host IOMMU device\n+ *\n+ * Returns: true on success, false on failure\n+ */\n+ bool (*support_ats)(HostIOMMUDevice *hiod);\n };\n \n /*\n", "prefixes": [ "04/11" ] }