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GET /api/patches/2218323/?format=api
{ "id": 2218323, "url": "http://patchwork.ozlabs.org/api/patches/2218323/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-2-nathanc@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260401010231.4166776-2-nathanc@nvidia.com>", "list_archive_url": null, "date": "2026-04-01T01:02:21", "name": "[01/11] hw/arm/smmuv3-accel: Add helper for resolving auto parameters", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2eed9c6c9dc5e6afdfcf612ca2add558db797cf8", "submitter": { "id": 92820, "url": "http://patchwork.ozlabs.org/api/people/92820/?format=api", "name": "Nathan Chen", "email": "nathanc@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401010231.4166776-2-nathanc@nvidia.com/mbox/", "series": [ { "id": 498265, "url": "http://patchwork.ozlabs.org/api/series/498265/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498265", "date": "2026-04-01T01:02:20", "name": "hw/arm/smmuv3-accel: Resolve AUTO properties", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498265/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2218323/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218323/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ZU5m20Ua;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=jJ5M0spLOC7jaaaPGybjHhVhMsxlC1rDm3n/SvM4A40=;\n b=rpK8ZMfaTcEU8nU+hFNiV/kzwkuMlyAEVzaNDYCRe0lY5ZtF1c40VGjgflZoAJajWmEoja3VP4fYERaBoz66oodaT0Bqo9bZVvaKkcahVmSle6SFzAtItA+RNoUTo0rWMFgD+N7Hun3JqtOmVoJFQuSnyp8MEY94xQHa3yeRpHkUGJQm6+xo2ZWFGCNjsQNi/1KYJlHkOnvixq+X68i/6SWNCLRPLGfcMH4C9LA/L/rNb9/QSJYwtb6p6MmDzBmZXcS2PjN3fhU6hLdUYaI+obLf9mzhVJNc0eNxgfXX4cqGIX/7TYrWuNRUOch6kOtctlaNd+zFQqprFmiCun9tEQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=jJ5M0spLOC7jaaaPGybjHhVhMsxlC1rDm3n/SvM4A40=;\n b=ZU5m20UaS79oO7q4QwdS9ztr57ECda/Er/fbRX9iM+wVxjhqknA7fjzsROrlPeepvFVoDkNtAvzF1TRYgMrza47LBpFolP50Zls3aMRcR8U1kSaZXPT5mj7HSmEF2jWFkoYvsMmdsiRY3enaACTxx3x5h+3SBfxeAipEX4dIywK7cQpet1fNHON7WfnJKt9poTSetAOagnxCUiZVjoG/eTXwC6CaBZlickz/C0dkVGWQUEURYxZ2NM6yrsiq1Gsti+mSZWpEDWbs8WS/fjtMq4WC7eCVGHmeM4iaYVgiGap8XEzr9B78XxDOXjZXteIOPlqiTfZoyB1UR3gQAjwpZg==", "From": "Nathan Chen <nathanc@nvidia.com>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Cc": "Yi Liu <yi.l.liu@intel.com>, Eric Auger <eric.auger@redhat.com>,\n Zhenzhong Duan <zhenzhong.duan@intel.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, =?utf-8?q?Philippe_Mathieu-D?=\n\t=?utf-8?q?aud=C3=A9?= <philmd@linaro.org>,\n Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>,\n Alex Williamson <alex@shazbot.org>,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@redhat.com>,\n Shameer Kolothum <skolothumtho@nvidia.com>, Matt Ochs <mochs@nvidia.com>,\n Nicolin Chen <nicolinc@nvidia.com>, Nathan Chen <nathanc@nvidia.com>", "Subject": "[PATCH 01/11] hw/arm/smmuv3-accel: Add helper for resolving auto\n parameters", "Date": "Tue, 31 Mar 2026 18:02:21 -0700", "Message-ID": "<20260401010231.4166776-2-nathanc@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260401010231.4166776-1-nathanc@nvidia.com>", "References": "<20260401010231.4166776-1-nathanc@nvidia.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "SJ2PR07CA0004.namprd07.prod.outlook.com\n (2603:10b6:a03:505::10) To DS2PR12MB9567.namprd12.prod.outlook.com\n (2603:10b6:8:27c::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PR12MB9567:EE_|CH1PR12MB9647:EE_", "X-MS-Office365-Filtering-Correlation-Id": "090e9568-1615-49db-583f-08de8f8a5cf4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|1800799024|366016|376014|7416014|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n 2GoDOoidtvSAZSsB1JZ46qjqkauC9s8j2uuSJFlrDHWQCCJ0LQWxjGM2ZKANlUF3B8q6vIIO3ovfB2rXFt3uIqDXeQ6M4CzTMQwlJM/yVmz0e6vK48y2eZ/7xwNWLm8VO9wceOFAExcWfci9YWHnyM1+5lVN2tp6qGyYFcfFEtf6orbeRF2lYp4TWVWnranOlsTE6keQQd8O5YyjGaVH5L5dW+1/eq8IBzSHDpRKkmAY6x/E85wkryLSgVnQJBZB/YmUyWqWu8T8LI5jrEWnGOBDS2b9x4xoH0LK+tP6myJfU82R8yuo/5SGvvR3Fc2CvIBx2T1qcJzkEa0p1VJauR813DnTv2tRE3q6/Yv8DE+FDARUAntVnqNRNM+fVZTKHylw2fj0VTn1uyMUUrTUBjptmTh1K2kb/I6pypGEjrne46+XA8ZiWm9YqwqyAyhZiPY44oJHVMYwpiWKJ09gfJZvJp7rZWyq26gRcBQWwXzB9Av2GmZRzzBS2fQfIUpAje12bMRNsWV2BfDjv8keCKev8eK9TEIgW+2qADBCC+4jn6lXm2LPWTLzdC1ryOzfTgCPoVjZUdoS02z5/eW8lYN5SjwxDx/X2wIUn4oykD1aWgW2NXKk2tEZCjIyXzuudAsfYS47tCaKhhcpQvaiIFyWQbfaB3AKbu14o5l2cy0Z1ICa4HtWtrHXUu8welxznqafahV6QLVcSM7i95TmL/qP4FQ2bASqmK5Ab3bNLqA=", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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This helper function allows\nproperties such as ats, ril, ssidsize, and oas support to be resolved\nfrom host IOMMU capabilities via IOMMU_GET_HW_INFO.\n\nAuto mode requires at least one cold-plugged device to retrieve and\nfinalise these properties. Register a machine_init_done notifier to\nverify this requirement and fail boot if it is not met.\n\nHot-plugged devices into an accel SMMUv3-associated bus will re-use\nthe resolved host values from the initial cold-plug.\n\nSubsequent patches will make use of this helper to resolve 'auto' to\nwhat is reported by host IOMMU capabilities.\n\nSuggested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 14 ++++++++++++++\n hw/arm/smmuv3-accel.h | 2 ++\n hw/arm/smmuv3.c | 20 ++++++++++++++++++++\n include/hw/arm/smmuv3.h | 2 ++\n 4 files changed, 38 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 65c2f44880..a0146c8d31 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -35,11 +35,25 @@ static int smmuv3_oas_bits(uint32_t oas)\n return map[oas];\n }\n \n+static void smmuv3_accel_auto_finalise(SMMUv3State *s,\n+ struct iommu_hw_info_arm_smmuv3 *info) {\n+ SMMUv3AccelState *accel = s->s_accel;\n+\n+ /* Return if no auto for any or finalised already */\n+ if (!accel->auto_mode || accel->auto_finalised) {\n+ return;\n+ }\n+\n+ accel->auto_finalised = true;\n+}\n+\n static bool\n smmuv3_accel_check_hw_compatible(SMMUv3State *s,\n struct iommu_hw_info_arm_smmuv3 *info,\n Error **errp)\n {\n+ smmuv3_accel_auto_finalise(s, info);\n+\n /* QEMU SMMUv3 supports both linear and 2-level stream tables */\n if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=\n FIELD_EX32(s->idr[0], IDR0, STLEVEL)) {\ndiff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex dba6c71de5..3c1cd55714 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -26,6 +26,8 @@ typedef struct SMMUv3AccelState {\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n+ bool auto_mode;\n+ bool auto_finalised;\n } SMMUv3AccelState;\n \n typedef struct SMMUS1Hwpt {\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 7fead1c3cf..09ea08eb18 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -37,6 +37,7 @@\n #include \"smmuv3-accel.h\"\n #include \"smmuv3-internal.h\"\n #include \"smmu-internal.h\"\n+#include \"system/system.h\"\n \n #define PTW_RECORD_FAULT(ptw_info, cfg) (((ptw_info).stage == SMMU_STAGE_1 && \\\n (cfg)->record_faults) || \\\n@@ -2020,6 +2021,22 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n return true;\n }\n \n+static void smmuv3_machine_done(Notifier *notifier, void *data)\n+{\n+ SMMUv3State *s = container_of(notifier, SMMUv3State, machine_done);\n+ SMMUv3AccelState *accel = s->s_accel;\n+\n+ if (!s->accel) {\n+ return;\n+ }\n+\n+ if (accel->auto_mode && !accel->auto_finalised) {\n+ error_report(\"arm-smmuv3 accel=on with 'auto' properties requires \"\n+ \"at least one cold-plugged VFIO device\");\n+ exit(1);\n+ }\n+}\n+\n static void smmu_realize(DeviceState *d, Error **errp)\n {\n SMMUState *sys = ARM_SMMU(d);\n@@ -2058,6 +2075,9 @@ static void smmu_realize(DeviceState *d, Error **errp)\n \n smmu_init_irq(s, dev);\n smmuv3_init_id_regs(s);\n+\n+ s->machine_done.notify = smmuv3_machine_done;\n+ qemu_add_machine_init_done_notifier(&s->machine_done);\n }\n \n static const VMStateDescription vmstate_smmuv3_queue = {\ndiff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex 82f18eb090..fe0493c1aa 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -74,6 +74,8 @@ struct SMMUv3State {\n OnOffAuto ats;\n OasMode oas;\n SsidSizeMode ssidsize;\n+\n+ Notifier machine_done;\n };\n \n typedef enum {\n", "prefixes": [ "01/11" ] }