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GET /api/patches/2218267/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
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{
    "id": 2218267,
    "url": "http://patchwork.ozlabs.org/api/patches/2218267/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260331200658.1306-3-mailingradian@gmail.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260331200658.1306-3-mailingradian@gmail.com>",
    "list_archive_url": null,
    "date": "2026-03-31T20:06:56",
    "name": "[v5,2/4] dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "551bfe2dbfbf75aef3ee78bc06aceea4d5a9281d",
    "submitter": {
        "id": 84825,
        "url": "http://patchwork.ozlabs.org/api/people/84825/?format=api",
        "name": "Richard Acayan",
        "email": "mailingradian@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260331200658.1306-3-mailingradian@gmail.com/mbox/",
    "series": [
        {
            "id": 498247,
            "url": "http://patchwork.ozlabs.org/api/series/498247/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=498247",
            "date": "2026-03-31T20:06:55",
            "name": "SDM670 LPASS LPI pin controller support",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/498247/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2218267/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2218267/checks/",
    "tags": {},
    "related": [],
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        "From": "Richard Acayan <mailingradian@gmail.com>",
        "To": "Bjorn Andersson <andersson@kernel.org>,\n\tLinus Walleij <linusw@kernel.org>,\n\tRob Herring <robh@kernel.org>,\n\tKrzysztof Kozlowski <krzk+dt@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tKonrad Dybcio <konradybcio@kernel.org>,\n\tSrinivas Kandagatla <srini@kernel.org>,\n\tlinux-arm-msm@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tdevicetree@vger.kernel.org",
        "Cc": "Richard Acayan <mailingradian@gmail.com>",
        "Subject": "[PATCH v5 2/4] dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI\n pinctrl",
        "Date": "Tue, 31 Mar 2026 16:06:56 -0400",
        "Message-ID": "<20260331200658.1306-3-mailingradian@gmail.com>",
        "X-Mailer": "git-send-email 2.53.0",
        "In-Reply-To": "<20260331200658.1306-1-mailingradian@gmail.com>",
        "References": "<20260331200658.1306-1-mailingradian@gmail.com>",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-gpio@vger.kernel.org",
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        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit"
    },
    "content": "Add the pin controller for the audio Low-Power Island (LPI) on SDM670.\n\nSigned-off-by: Richard Acayan <mailingradian@gmail.com>\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n---\n .../qcom,sdm670-lpass-lpi-pinctrl.yaml        | 81 +++++++++++++++++++\n 1 file changed, 81 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml",
    "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml\nnew file mode 100644\nindex 000000000000..c76ad70e6b9f\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml\n@@ -0,0 +1,81 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm SDM670 SoC LPASS LPI TLMM\n+\n+maintainers:\n+  - Richard Acayan <mailingradian@gmail.com>\n+\n+description:\n+  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem\n+  (LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.\n+\n+properties:\n+  compatible:\n+    const: qcom,sdm670-lpass-lpi-pinctrl\n+\n+  reg:\n+    items:\n+      - description: LPASS LPI TLMM Control and Status registers\n+\n+patternProperties:\n+  \"-state$\":\n+    oneOf:\n+      - $ref: \"#/$defs/qcom-sdm670-lpass-state\"\n+      - patternProperties:\n+          \"-pins$\":\n+            $ref: \"#/$defs/qcom-sdm670-lpass-state\"\n+        additionalProperties: false\n+\n+$defs:\n+  qcom-sdm670-lpass-state:\n+    type: object\n+    description:\n+      Pinctrl node's client devices use subnodes for desired pin configuration.\n+      Client device subnodes use below standard properties.\n+    $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state\n+    unevaluatedProperties: false\n+\n+    properties:\n+      pins:\n+        description:\n+          List of gpio pins affected by the properties specified in this\n+          subnode.\n+        items:\n+          pattern: \"^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$\"\n+\n+      function:\n+        enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,\n+                i2s1_clk, i2s_data, i2s_ws, lpi_cdc_rst, mclk0, pdm_rx,\n+                pdm_sync, pdm_tx, slimbus_clk ]\n+        description:\n+          Specify the alternative function to be configured for the specified\n+          pins.\n+\n+allOf:\n+  - $ref: qcom,lpass-lpi-common.yaml#\n+\n+required:\n+  - compatible\n+  - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+  - |\n+    lpi_tlmm: pinctrl@62b40000 {\n+        compatible = \"qcom,sdm670-lpass-lpi-pinctrl\";\n+        reg = <0x62b40000 0x20000>;\n+        gpio-controller;\n+        #gpio-cells = <2>;\n+        gpio-ranges = <&lpi_tlmm 0 0 32>;\n+\n+        cdc_comp_default: cdc-comp-default-state {\n+            pins = \"gpio22\", \"gpio24\";\n+            function = \"comp_rx\";\n+            drive-strength = <4>;\n+        };\n+    };\n",
    "prefixes": [
        "v5",
        "2/4"
    ]
}