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GET /api/patches/2218229/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2218229,
    "url": "http://patchwork.ozlabs.org/api/patches/2218229/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260331175658.1015829-3-gaohan@iscas.ac.cn/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260331175658.1015829-3-gaohan@iscas.ac.cn>",
    "list_archive_url": null,
    "date": "2026-03-31T17:56:58",
    "name": "[2/2] PCI: Add quirk to disable PCIe port services on Sophgo SG2042",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "fd78ce684cfe3b54c0ec6ac2f9e019ed22495fb7",
    "submitter": {
        "id": 92681,
        "url": "http://patchwork.ozlabs.org/api/people/92681/?format=api",
        "name": "Han Gao",
        "email": "gaohan@iscas.ac.cn"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260331175658.1015829-3-gaohan@iscas.ac.cn/mbox/",
    "series": [
        {
            "id": 498236,
            "url": "http://patchwork.ozlabs.org/api/series/498236/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498236",
            "date": "2026-03-31T17:56:58",
            "name": "PCI: Allow disabling port services on broken root ports",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/498236/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2218229/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2218229/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "\n <linux-pci+bounces-51602-incoming=patchwork.ozlabs.org@vger.kernel.org>",
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        ],
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
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        "From": "Han Gao <gaohan@iscas.ac.cn>",
        "To": "Bjorn Helgaas <bhelgaas@google.com>,\n =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <u.kleine-koenig@baylibre.com>,\n Jonathan Cameron <jonathan.cameron@huawei.com>,\n Lukas Wunner <lukas@wunner.de>,\n =?utf-8?q?Ilpo_J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>,\n Kees Cook <kees@kernel.org>, Han Gao <gaohan@iscas.ac.cn>,\n Chen Wang <unicorn_wang@outlook.com>, Manivannan Sadhasivam <mani@kernel.org>",
        "Cc": "linux-pci@vger.kernel.org,\n\tsophgo@lists.linux.dev,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-riscv@lists.infradead.org,\n\tHan Gao <rabenda.cn@gmail.com>,\n\tIcenowy Zheng <zhengxingda@iscas.ac.cn>,\n\tInochi Amaoto <inochiama@gmail.com>,\n\tVivian Wang <wangruikang@iscas.ac.cn>,\n\tYao Zi <me@ziyao.cc>,\n\tstable@vger.kernel.org",
        "Subject": "[PATCH 2/2] PCI: Add quirk to disable PCIe port services on Sophgo\n SG2042",
        "Date": "Wed,  1 Apr 2026 01:56:58 +0800",
        "Message-ID": "<20260331175658.1015829-3-gaohan@iscas.ac.cn>",
        "X-Mailer": "git-send-email 2.47.3",
        "In-Reply-To": "<20260331175658.1015829-1-gaohan@iscas.ac.cn>",
        "References": "<20260331175658.1015829-1-gaohan@iscas.ac.cn>",
        "Precedence": "bulk",
        "X-Mailing-List": "linux-pci@vger.kernel.org",
        "List-Id": "<linux-pci.vger.kernel.org>",
        "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>",
        "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-CM-TRANSID": "qwCowABH8GvrCsxpCP3GCw--.20050S4",
        "X-Coremail-Antispam": "1UD129KBjvJXoWxJr4fXw1rAr17XrykAr48tFb_yoW8uw17pF\n\ts8GF9ayr4FgFyUGw4kZw1kuF9xua1vy34FkrZ3Wa9IvF1ay3s5XFsrtr9IyF47WFsrXFW5\n\tXwn8Cws8Wa4DWFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n\trVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2\n\tx26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0\n\tY4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2\n\t8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U\n\tM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx\n\tv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l\n\tF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2\n\tIY04v7MxkF7I0En4kS14v26r4a6rW5MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY\n\t6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17\n\tCEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF\n\t0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI\n\tIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnI\n\tWIevJa73UjIFyTuYvjTRNiSHDUUUU",
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    },
    "content": "SG2042's PCIe root ports [1f1c:2042] fail to deliver MSI interrupts to\ndownstream devices when native port services are enabled. Devices under\nan affected root port receive zero interrupts despite successful vector\nallocation, causing driver timeouts (e.g. amdgpu fence fallback timer\nexpired on all rings).\n\nSet PCI_DEV_FLAGS_NO_PORT_SERVICES on SG2042 root ports to prevent the\nport service driver from probing, restoring correct MSI delivery.\n\nFixes: 1c72774df028 (\"PCI: sg2042: Add Sophgo SG2042 PCIe driver\")\nCc: stable@vger.kernel.org\nSigned-off-by: Han Gao <gaohan@iscas.ac.cn>\n---\n drivers/pci/quirks.c    | 12 ++++++++++++\n include/linux/pci_ids.h |  2 ++\n 2 files changed, 14 insertions(+)",
    "diff": "diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 48946cca4be7..bbde482ff7cb 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -6380,3 +6380,15 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev)\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout);\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout);\n #endif\n+\n+/*\n+ * SG2042's PCIe root ports do not correctly deliver MSI interrupts to\n+ * downstream devices when native PCIe port services are enabled. All\n+ * services including bwctrl must be disabled, equivalent to pcie_ports=compat.\n+ */\n+static void quirk_sg2042_no_port_services(struct pci_dev *dev)\n+{\n+\tpci_info(dev, \"SG2042: disabling native PCIe port services\\n\");\n+\tdev->dev_flags |= PCI_DEV_FLAGS_NO_PORT_SERVICES;\n+}\n+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOPHGO, 0x2042, quirk_sg2042_no_port_services);\ndiff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h\nindex 406abf629be2..9663be526dd0 100644\n--- a/include/linux/pci_ids.h\n+++ b/include/linux/pci_ids.h\n@@ -2630,6 +2630,8 @@\n \n #define PCI_VENDOR_ID_CXL\t\t0x1e98\n \n+#define PCI_VENDOR_ID_SOPHGO\t\t0x1f1c\n+\n #define PCI_VENDOR_ID_TEHUTI\t\t0x1fc9\n #define PCI_DEVICE_ID_TEHUTI_3009\t0x3009\n #define PCI_DEVICE_ID_TEHUTI_3010\t0x3010\n",
    "prefixes": [
        "2/2"
    ]
}